Layout is the process of designing a PCB including placement of parts and routing of traces.

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11-lead TO-220 package & 16-pin MSOP eagle parts [on hold]

I need to realise a circuit with opa2544 amplifier it is an 11-lead TO-220 package so I search on any part with the same package on eagle to realize a layout but I can't found anyone also I need a ...
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1answer
26 views

How to remove pin name from Eagle Device Page? [See Image]

How to remove those pin name from Eagle Device Page?
2
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3answers
91 views

CAN bus layout design

I am trying to design a CAN bus node. The CAN bus shall be split-terminated with 120Ohm, 60Ohm for each line. Therefore i tried using this paper to calculate a characteristic impedance of 60Ohm for a ...
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1answer
59 views

USB 2.0 layout on 2-layer board

I have laid out this board that includes (among other lower speed connections) a 1 upstream and 2 downstream ports on a 0.5mm FR4. The USB differential traces are 0.6mm wide with 0.15mm spacing ...
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1answer
33 views

How to to design a PCB lib for components with variable dimensions?

I'm designing various PCB libraries for components. But sometimes they have variable dimensions: How should I design the pads for components with fluctuating values?
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2answers
44 views

Which layer contains the board outline in PADS Layout?

TL:DR If I create or import a board outline on PADS Layout, in which layer(s) is it drawn? Can I make it visible/invisible? On Mentor Graphics PADS, I'm trying to import a board outline from a ...
0
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1answer
84 views

Chess-Board schematic/pcb layout

Hey guys as described here I also want to make a chess board with some arduino support. Here I want to ask some questions regarding the schematic and the pcb layout I am planing to do. @Dmitry ...
4
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1answer
98 views

Optional feature in PCB layout of MMCX board edge connector. What's it for?

I'm designing a circuit requiring MMCX board edge connectors, specifically using the Molex 73415-0961 jack. When looking through the datasheet for suggested PCB layout, I see mention of an additional ...
20
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3answers
1k views

What's the purpose of traces that are later punched out?

I've found this odd feature on an FPC in a Camera than handles button and switch input. You can see there are traces that look like they were once connected and later punched out to be cut. The one ...
0
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2answers
75 views

How to Allow Shorts Between the same Net in Altium

I have some pads and tracks that are different primitives but are the same net in an Altium layout. Altium keeps flagging these as ShortCircuit DRC violations, but they're the same net, so I don't ...
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0answers
26 views

Can Inkscape be used for layout editing for photolithography?

Inkscape is capable of exporting DXF files, a format that is accepted by photolithography masks manufacturers. Before I start working on layouts with Inkscape I would like to know if the exported DXF ...
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1answer
35 views

Resolving airwires in EAGLE for valid wires

I have a board(brd) file in Eagle which shows several airwires for connected nets. I have tried to fix the airwire via ratsnesting, confirming net names and just about every resolution I could ...
3
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1answer
182 views

The need for SMD neck-down constraints

I am designing a PCB which has +5V input from a USB jack and I want this power trace to be as large as possible to reduce input resistance. While doing my large traces on my PCB tool, one of the stock ...
2
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1answer
161 views

Spikes induced on PCB. EMC problem?

I designed the following PCB, where after testing a faced a severe (EMC related?) problem. This board houses an STM32F103 developing board. On the right of the PCB, there are 6 thermistors connected ...
3
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3answers
164 views

PCB layout needs improvement

I have been working on this layout. Lack of my training, my layout looks amateurish. Can I please get some general direction/tips on improving this design? Some details: Breakout board with ...
5
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1answer
48 views

Placement of two independent crystals

This one is completely about PCB layout. I have two 26MHz crystals in the design, one for each processor on the board (TXC 7M-26.000MEEQ-T, datasheet: ...
6
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4answers
922 views

What does “V.A.” mean in datasheet dimensions?

I'm looking at a datasheet for an LCD panel (pdf link to datasheet). I don't understand these two encircled dimensions: What does the acronym "V.A." mean for these dimensions? I have referenced a ...
1
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3answers
75 views

routing of signals

My doubt relates to a routing style of signals. Speed is not the criteria as the signals are not high speed. Kindly refer the image below please - . There are 2 ways to route signals. They are both ...
7
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1answer
436 views

PCB microcontroller layout in a mixed-signal system

This is a direct continuation of this question. So here's my layout, what do you think about the microcontroller side? EDIT: based on Armandas' answer, I'm now under the impression that the ...
1
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2answers
92 views

Board to Wire Connector Type used between Small Display and Main PCB

I'm in the process of designing a PCB/Prototype and looking at different types of board-to-wire type connectors. In particular, I want to connect an SPI OLED display to the main PCB. It needs to be ...
6
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1answer
174 views

Two-sided connectorless USB on a PCB

This question is inspired by Connectorless USB on a PCB. I saw a cool USB LED on AliExpress that can be inserted in either direction: I'd like to build a board with a similar symmetric ...
11
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2answers
571 views

How many ground and power pins to have in a connector?

I'm designing a daughter board for a project. There are 35 I/O pins that need to go to the board. How do I determine the number of ground and power pins to include? How do I determine the placement of ...
35
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5answers
5k views

Why should you use two resistors in parallel on an LED?

So I was looking over the Arduino R3 schematics and noticed this little design choice: What is the reason for doing something like this? I mean it's hard to know what the designers were thinking, ...
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0answers
56 views

Crystal routing in layout

We started production for a project with RFID reader (13.56Mhz) which have an external crystal of 13.56Mhz. The layout was designed by a Chinese design house which I'm afraid that did a small mistake ...
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1answer
68 views

Where is pin 1 in Molex connector?

In 54722-0604, which is the pin #1? connector page at molex.com
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54 views

Layout recommendations for an older DC/DC

I'm currently working on getting an old voltage regulator chip from TI to work. The TPS65530 is an 8-channel DC/DC Converter and thus quite crowded. I have not been able to find a reference design ...
3
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1answer
189 views

Routing Digital Signals to an Analog Circuit

I'm working in a mixed (analog and digital) PCB layout where I need to route some tracks from digital to analog ground area. They are general I/Os signals to control MOSFETs and clocks/data signals ...
0
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4answers
93 views

analogue and digital ground connection

I have been reading up on grounding and what is AGND and DGND i.e / analogue ground and digital ground respectively. Suppose , I have an ADC chip and a MCU in a PCB. Now, previously I would have a ...
2
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1answer
72 views

Input filter pcb layout considerations

I have two options for input filter having ferrite bead and reverse polarity protection diode as shown below simulate this circuit – Schematic created using CircuitLab The input supply ...
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1answer
73 views

Crystal grounds and minimal trace distance to leads

Some questions have already been asked about crystals but there's a few competing designs and I have a few "obsessive" type questions on layout. Here's a almost completed layout with a PIC16F ...
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4answers
755 views

Why do PCBs have big interfaces?

I am not sure if this is a good question but I am curious. Consider the following PCB: I have realized that although the lines leaving the IC in the middle start fairly close to each other, they ...
2
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1answer
49 views

Chamfer Geometry for GCPW and Microstrip

I've seen various "recommended" chamfers for 90 degree grounded coplanar and microstrip traces. For example, or . Is there a "rule of thumb" for which type of chamber and which geometries work best ...
7
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3answers
894 views

Does this layout ever make sense to do?

Let's say I've got an power output and I want to power a chips Vin's with it. But, let's say it's a couple of different digital Vcc's on the chip that I want to power, like a rail for an LO, a rail ...
2
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2answers
130 views

BGA: capacitor placement and other pads

I'm doing my first BGA layout with a microcontroller. The bypass capacitors must be on the bottom side and I'd like to have the minimum capacitor size 0402. Now I just have the problem, that the ...
6
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1answer
435 views

What is the purpose of this layout feature

I have been researching some TI power supply ICs and came across the following diagram in the datasheet for TPS40200. Can anyone explain why the trace circled in red is connected as it is instead of ...
3
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1answer
348 views

Is this layout good? (RF - 2.45 GHz)

I finished laying out HACK, my first RF (2.45 GHz) layout. The sensitive part is the connection between the IC (Atmel SAM R21G18A), the balun (Johanson 2450BM15A0015), and the PCB antenna (copied from ...
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1answer
39 views

Eagle clearance issue

I don't know how to search this problem on google so I was hoping you guys could help out. I have made an eagle part by myself. I have used the top layer for the pads (just click pad and then adjust ...
1
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1answer
56 views

Where do the return currents go for a MCU with multiple Vdd and grounds?

I am reading this article on mixed signal design: https://www.maximintegrated.com/en/app-notes/index.mvp/id/5450 When signals have really high speed, the return current will tend to follow right ...
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1answer
56 views

How do corner vias in a QFN layout ensure stable operation?

In the picture below, from the recommended layout of the TGA-2513-SM: there are via holes in the four corners of the QFN package. The datasheet claims that this "ensures stable operation". In what ...
4
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1answer
95 views

How to route power in split-plane layout?

I'm working on a sensitive analog measurement board. The design currently has split ground planes for analog and digital which are tied under the ADCs, as described in Analog Devices note MT-031. ...
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109 views

Switching power supply layout review

In a previous question where a SMPS based on an LM5118 was presented, some aspects of the layout were pointed out as being problematic. I've taken another look at the layout of that section of the ...
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1answer
50 views

length matching impact in ADC chips

I am using the ADC4245-EP (enhanced product) adc chip. It has a normal version as well of it.There are 2 options of interfacing thiis ADC to an FPGA. They are CMOS or LVDS. The advantage of the LVDS ...
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2answers
171 views

KiCad net names

I'm trying to assign footprint's pad to a net in a schematic but for some reason nets in Eeschema aren't generated from components' pin names (EN, VIN etc.), but are always auto-generated ...
0
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1answer
53 views

extract gate level netlist from layout

My project is to extract a gate level netlist from layout, I am going write a parser for GDSII file format. However, I have trouble in relating the record information represented in the GDSII format ...
0
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0answers
55 views

Traces Perpendicular to QFN Pad

Is there any danger (esp. related to manufacturability, or ease of assembly) with running traces out from pads perpendicularly? The part is QFN, and it looks like part of the trace might be covered by ...
5
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3answers
257 views

For a 4 layers PCB (with ground plane), covering with ground polygon on Layer 1&4 necessary?

For a single or double layered PCB board, usually I will cover all the empty spaces in the layout with Ground. This is the 1st time I am designing a 4 layer PCB layout. Layer 1: top signal (high ...
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1answer
840 views

I2C PCB Layout Considerations

I wanted to ask, what general layout guidelines and/or routing concerns exist for I2C in a PCB design? Edit - Consider a 31mil thick, 4Layer PCB with stack up: L1 = signal - 0.5oz + 1oz plating L2 ...
3
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1answer
256 views

PCB Layout and Trace Widths for Buck Converter

I am doing a PCB layout for a simple 12V DC to 5VDC buck converter. The rated output is 3A continuous 5A peak. Here are links to the schematic and first go at the pcb layout. I realize the traces are ...
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96 views

Will the following circuit cause EMI-problems?

I'm trying to get a feel for which circuits will have EMI-problems and which won't. To make things a bit more concrete, I've designed a super-simple LED-blinking circuit using the PIC16F1788 ...
0
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2answers
82 views

Layout of doubled SW pin on buck converter IC

I'm working on a PCB for the MP2617. That IC integrates a buck converter and has two physical SW pins sandwiching the VIN pin, as shown in my tentative layout below. No other pins on the IC are ...