Layout is the process of designing a PCB including placement of parts and routing of traces.

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4answers
888 views

What does “V.A.” mean in datasheet dimensions?

I'm looking at a datasheet for an LCD panel (pdf link to datasheet). I don't understand these two encircled dimensions: What does the acronym "V.A." mean for these dimensions? I have referenced a ...
1
vote
3answers
69 views

routing of signals

My doubt relates to a routing style of signals. Speed is not the criteria as the signals are not high speed. Kindly refer the image below please - . There are 2 ways to route signals. They are both ...
7
votes
1answer
338 views

PCB microcontroller layout in a mixed-signal system

This is a direct continuation of this question. So here's my layout, what do you think about the microcontroller side? EDIT: based on Armandas' answer, I'm now under the impression that the ...
1
vote
2answers
57 views

Board to Wire Connector Type used between Small Display and Main PCB

I'm in the process of designing a PCB/Prototype and looking at different types of board-to-wire type connectors. In particular, I want to connect an SPI OLED display to the main PCB. It needs to be ...
6
votes
1answer
128 views

Two-sided connectorless USB on a PCB

This question is inspired by Connectorless USB on a PCB. I saw a cool USB LED on AliExpress that can be inserted in either direction: I'd like to build a board with a similar symmetric ...
11
votes
2answers
475 views

How many ground and power pins to have in a connector?

I'm designing a daughter board for a project. There are 35 I/O pins that need to go to the board. How do I determine the number of ground and power pins to include? How do I determine the placement of ...
35
votes
5answers
5k views

Why should you use two resistors in parallel on an LED?

So I was looking over the Arduino R3 schematics and noticed this little design choice: What is the reason for doing something like this? I mean it's hard to know what the designers were thinking, ...
0
votes
0answers
52 views

Crystal routing in layout

We started production for a project with RFID reader (13.56Mhz) which have an external crystal of 13.56Mhz. The layout was designed by a Chinese design house which I'm afraid that did a small mistake ...
0
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1answer
41 views

Where is pin 1 in Molex connector?

In 54722-0604, which is the pin #1? connector page at molex.com
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0answers
51 views

Layout recommendations for an older DC/DC

I'm currently working on getting an old voltage regulator chip from TI to work. The TPS65530 is an 8-channel DC/DC Converter and thus quite crowded. I have not been able to find a reference design ...
3
votes
1answer
128 views

Routing Digital Signals to an Analog Circuit

I'm working in a mixed (analog and digital) PCB layout where I need to route some tracks from digital to analog ground area. They are general I/Os signals to control MOSFETs and clocks/data signals ...
0
votes
4answers
70 views

analogue and digital ground connection

I have been reading up on grounding and what is AGND and DGND i.e / analogue ground and digital ground respectively. Suppose , I have an ADC chip and a MCU in a PCB. Now, previously I would have a ...
2
votes
1answer
47 views

Input filter pcb layout considerations

I have two options for input filter having ferrite bead and reverse polarity protection diode as shown below simulate this circuit – Schematic created using CircuitLab The input supply ...
1
vote
1answer
62 views

Crystal grounds and minimal trace distance to leads

Some questions have already been asked about crystals but there's a few competing designs and I have a few "obsessive" type questions on layout. Here's a almost completed layout with a PIC16F ...
5
votes
4answers
745 views

Why do PCBs have big interfaces?

I am not sure if this is a good question but I am curious. Consider the following PCB: I have realized that although the lines leaving the IC in the middle start fairly close to each other, they ...
2
votes
1answer
35 views

Chamfer Geometry for GCPW and Microstrip

I've seen various "recommended" chamfers for 90 degree grounded coplanar and microstrip traces. For example, or . Is there a "rule of thumb" for which type of chamber and which geometries work best ...
7
votes
3answers
884 views

Does this layout ever make sense to do?

Let's say I've got an power output and I want to power a chips Vin's with it. But, let's say it's a couple of different digital Vcc's on the chip that I want to power, like a rail for an LO, a rail ...
2
votes
2answers
95 views

BGA: capacitor placement and other pads

I'm doing my first BGA layout with a microcontroller. The bypass capacitors must be on the bottom side and I'd like to have the minimum capacitor size 0402. Now I just have the problem, that the ...
6
votes
1answer
409 views

What is the purpose of this layout feature

I have been researching some TI power supply ICs and came across the following diagram in the datasheet for TPS40200. Can anyone explain why the trace circled in red is connected as it is instead of ...
3
votes
1answer
219 views

Is this layout good? (RF - 2.45 GHz)

I finished laying out HACK, my first RF (2.45 GHz) layout. The sensitive part is the connection between the IC (Atmel SAM R21G18A), the balun (Johanson 2450BM15A0015), and the PCB antenna (copied from ...
0
votes
0answers
43 views

CMOS Layout, which size is better?

I'm trying to draw a NOR3 layout which has 3.93x of standard inverter size. I developed a simple excel formula to choose the width of PMOS and NMOS as well as how many legs are required. I'm coming ...
1
vote
1answer
34 views

Eagle clearance issue

I don't know how to search this problem on google so I was hoping you guys could help out. I have made an eagle part by myself. I have used the top layer for the pads (just click pad and then adjust ...
1
vote
1answer
50 views

Where do the return currents go for a MCU with multiple Vdd and grounds?

I am reading this article on mixed signal design: https://www.maximintegrated.com/en/app-notes/index.mvp/id/5450 When signals have really high speed, the return current will tend to follow right ...
1
vote
1answer
51 views

How do corner vias in a QFN layout ensure stable operation?

In the picture below, from the recommended layout of the TGA-2513-SM: there are via holes in the four corners of the QFN package. The datasheet claims that this "ensures stable operation". In what ...
4
votes
1answer
67 views

How to route power in split-plane layout?

I'm working on a sensitive analog measurement board. The design currently has split ground planes for analog and digital which are tied under the ADCs, as described in Analog Devices note MT-031. ...
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vote
0answers
92 views

Switching power supply layout review

In a previous question where a SMPS based on an LM5118 was presented, some aspects of the layout were pointed out as being problematic. I've taken another look at the layout of that section of the ...
0
votes
1answer
48 views

length matching impact in ADC chips

I am using the ADC4245-EP (enhanced product) adc chip. It has a normal version as well of it.There are 2 options of interfacing thiis ADC to an FPGA. They are CMOS or LVDS. The advantage of the LVDS ...
0
votes
2answers
87 views

KiCad net names

I'm trying to assign footprint's pad to a net in a schematic but for some reason nets in Eeschema aren't generated from components' pin names (EN, VIN etc.), but are always auto-generated ...
0
votes
1answer
47 views

extract gate level netlist from layout

My project is to extract a gate level netlist from layout, I am going write a parser for GDSII file format. However, I have trouble in relating the record information represented in the GDSII format ...
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0answers
50 views

Traces Perpendicular to QFN Pad

Is there any danger (esp. related to manufacturability, or ease of assembly) with running traces out from pads perpendicularly? The part is QFN, and it looks like part of the trace might be covered by ...
5
votes
3answers
199 views

For a 4 layers PCB (with ground plane), covering with ground polygon on Layer 1&4 necessary?

For a single or double layered PCB board, usually I will cover all the empty spaces in the layout with Ground. This is the 1st time I am designing a 4 layer PCB layout. Layer 1: top signal (high ...
1
vote
1answer
438 views

I2C PCB Layout Considerations

I wanted to ask, what general layout guidelines and/or routing concerns exist for I2C in a PCB design? Edit - Consider a 31mil thick, 4Layer PCB with stack up: L1 = signal - 0.5oz + 1oz plating L2 ...
3
votes
1answer
181 views

PCB Layout and Trace Widths for Buck Converter

I am doing a PCB layout for a simple 12V DC to 5VDC buck converter. The rated output is 3A continuous 5A peak. Here are links to the schematic and first go at the pcb layout. I realize the traces are ...
1
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0answers
91 views

Will the following circuit cause EMI-problems?

I'm trying to get a feel for which circuits will have EMI-problems and which won't. To make things a bit more concrete, I've designed a super-simple LED-blinking circuit using the PIC16F1788 ...
0
votes
2answers
73 views

Layout of doubled SW pin on buck converter IC

I'm working on a PCB for the MP2617. That IC integrates a buck converter and has two physical SW pins sandwiching the VIN pin, as shown in my tentative layout below. No other pins on the IC are ...
1
vote
3answers
173 views

PCB layout of buck converter: capacitor placement

I'm designing a PCB for an IC that includes a DC/DC buck converter (MP2617). This is my first PCB, so I've been using the following resources for the layout: 1 and 2 (PDF files, the first one is a ...
0
votes
1answer
99 views

PCB chip/trace antenna located away from board edge?

I'm looking to design a system that will require a 2.4GHz antenna. The only problem is, every single reference design I find has the antenna situated on at least one board edge. Unfortunately due to ...
15
votes
1answer
371 views

PCIe, diagnosing and improving an eye diagram

I have implemented a design that uses PCIe. It is somewhat different in that the PCIe interface is used as a chip-to-chip communication lane on a single PCB (e.g. no PCIe connector). The root ...
1
vote
1answer
85 views

Problem with GDS export of a layout in Agilent Advanced System Design (ADS)

I have a problem exporting my layout design in ADS. It gives me an error that the layer map file not found in the library and it creates an empty file. I'd appreciate if you could let me know what ...
2
votes
1answer
113 views

Crystal PCB track

This is my current PCB crystal set up. The crystal run at 16 Mhz. Any thoughts/comment? Links: MCU - Datasheet TI PCB guideline Tiva C - Here
4
votes
2answers
171 views

Can a high current trace be on outer and inner layers at the same time?

EDIT, COMMENTS: TL;DR: Data doesn't conclusively suggest you can do this, but it seems to be worth trying. The data from IPC-2152 (more in the answers below) is intriguing, but doesn't seem to ...
0
votes
1answer
85 views

Altium Designer - split plane

I want to make a plane for my supply on my PCB and a plane for my MCU to isolate the MCU from the power supply noise. I found this article in Altium designer resource: But it isn't clear how the ...
1
vote
2answers
391 views

Weird capacitor looking things shows up in altium when I zoom into the pcb layout

I am using altium for first time for my little circuit project. My layout start showing these weird capacitor looking things in PCB layout. What exactly are they and what are they used for and how do ...
1
vote
1answer
102 views

Stop mask error upon running DRC in Eagle 7.3.0

I'm working on my first board layout using Eagle (7.3.0). I've got the layout done, but when I run DRC, I get a number of Stop Mask errors: These seem to be due to small rectangles on the tStop ...
0
votes
2answers
81 views

Opamp constant on

I have a weak signal (from a photo-diode) which I need to amplify to drive an LED. I try to accomplish this with an OpAmp TL081 and the circuit given in the image. What the circuit does: When there ...
0
votes
1answer
95 views

Help Duplicating Altium PCB Layout With Different Silkscreen IDs

I have the layout for a 3.3V switching regulator module and I also made a 1.5V switching regulator module. The 3.3V layout is very nicely done and I would like to replicate it for the 1.5V. However, ...
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vote
1answer
24 views

How do I automate the size setting (or any property) of both NAME and VALUE in a PCB BRD file?

I would like to set the size parameter of both value and name of components on a PCB layout to have a readable silk screen. Now it seems that I have to smash everything and go by them one by one. Is ...
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1answer
195 views

How can I create a rectangle drill in Orcad Layout Plus 10.3?

I use Orcad Layout Plus 10.3 for PCB design and I have a problem at this topic. For example, I have to use power jack footprint, I have created but the drill can't be rectangle. I added a screenshot ...
0
votes
1answer
154 views

Will an 0603 capacitor fit on an 0805 pad?

I am in a pinch and just submit my final board design to a pcb house. Unfortunately, I messed up the design and had an 0805 pad in a spot where a an 0603 should have been. I will be getting the boards ...
0
votes
1answer
57 views

What does 4*1 Panel-up mean?

I believe the number 4 corresponds to the number of individual PCBs and the number 1 is for one panel. Is this the way panelized PCBs are commonly referenced? With an asterisk mark? What does the ...