Consider instead more specific tags, e.g., dram, sram, flash

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27 views

What are the variables that define the speed of a computer? [on hold]

What are the variables that define the speed of a computer? I mean, for example RAM memory, processor clock... what else?
2
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1answer
79 views

EEPROM Write Limit [duplicate]

Just curious as to why do non volatile memories like EEPROM in an AVR have a write limit ? Also is this limit per location/adress in the memory or on the memory as a whole ?
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1answer
61 views

How does digital patch memory work on an analog synthesizer?

Not an electrical engineer, but kicking around ideas for a polyphonic analog synth with digital memory, a simplified/modernized update of an older all-analog design. I've riffled through some of the ...
3
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2answers
165 views

Microcontroller on-chip flash consumption - size matters?

For a given MCU, all other things being equal, does the memory capacity impact the power consumption ? A 512kB flash memory would consume more than a 128kB ?
1
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1answer
59 views

MPU accessing busy memory

I didn't know whether to place this question here or on stackoverflow, but I finally decided to post it here. I want to build a simple system that would be able to work with basic peripherals (UART, ...
0
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0answers
22 views

Measuring power consumption of cache memories?

Is there any practical method to only measure the power consumption of combined cache memory. I am intereted in measuring the power conumption overhead when replacing blocks, and or filling the cache ...
1
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1answer
41 views

Magnetic core memory construction, and proper cores to use

I'm looking to experiment with magnetic core memory. I want to make a small magnetic memory module for use with a micro controller. There is a post on stack exchange itself that gave lots of relevant ...
1
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1answer
61 views

Precharging circuits in SRAM

I got to know 4 circuits used for Precharging in SRAM. I have few questions regarding circuits explanation: Diagram (a): Q1: It mentions it as diode-connected NMOS pair. Why? Q2: This burns more ...
2
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1answer
131 views

Sense Amplifiers in SRAM

The basic 6T structure used for storing data is same as one used in "Positive Feedback Differential Voltage Sense Amplifier", then how come while the data is stored in SRAM memory cell it doesn't get ...
1
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1answer
31 views

Real Time Data Capture System

I would like to build a system which could capture an analogue waveform data in real time. For the basic data acquisition system I can use an ADC to digitise an analogue waveform and store this in a ...
5
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1answer
161 views

DDR bus design review

In our last build we had issues with DDR stability in our prototype, simply because of lack of experience with this type of high speed memory connections. We managed to get it working with halving the ...
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1answer
128 views

Most reliable Flash memory for an embedded Linux system?

What would be the most reliable Flash memory hardware to use for an embedded Linux system? I.e. one that has the least chance of losing data or getting corrupt when the power goes down? The Flash ...
2
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0answers
23 views

Memory mapped peripheral on NAND bus

I have an embedded system that is not cost effective to roll a custom PCB therefore my access to certain buses are limited. I had the idea of hooking my FPGA up to the unused NAND port of the system ...
1
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1answer
152 views

Is there any tool to read/write EEPROM of STM32L from the host?

I'm using STM32L152RTC6 (link to similar MCU line) with a built-in EEPROM (8k). I wonder if there's any tool that allows me to read/write the EEPROM from the host side, other than programming the MCU ...
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1answer
48 views

One and Two Byte Wide

Ok can someone explain to me what is considered One Byte Wide or Two Byte Wide? I couldn't find much on it. From what I know 8 bits = 1 byte? So lets say there's 16 bits and it needs to be 2 byte wide ...
1
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1answer
156 views

Meaning of control pins: CE, OE, WE

Just understanding some syntax. On my Ram (6116) and Rom (27C64) it has a asserted low CE and OE pins. These I believe are control pins. I'm assuming to use the RAM for example, chip enable (CE) has ...
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1answer
33 views

Quartus II Memory Read Clock Problem

I used LPM_RAM to store data and made read and write operations. But it seems like placing the data to wrong addresses. Here is screenshots; Wave Result; Memory Block;
3
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2answers
480 views

What do hardware address pins do?

I have been delving deep into digital logic and am trying to understand some memory architecture basics. I have started looking at data sheets to get a grasp on some real-world components and noticed ...
0
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0answers
78 views

Can I use full-size 64/72 bit DDR2/DDR3 memory module with CycloneV hardware controller of 24 + 24 bits?

I thinking of using Cyclone V FPGA and its hardware memory controller: There is "Cyclone V FPGA Multiport Memory Controller" document from Altera: ...
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0answers
77 views

Can't read the SPI buffer of a PIC32MX

I have some problems with my SPI communication. Indeed, I have configurated the PIC32 as master, and it communicates with a slave which is a memory. The communication works perfectly. LEGEND : In ...
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1answer
51 views

How data recovery works in flash memory?

Flash memory is Electronically Erasable Programmable Read Only Memory. In this data is stored by the On or Off state of the transistor. Then How it is possible to recover the data stored in the device ...
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2answers
60 views

What are the various interfaces used on memory devices

There are various external memory devices for temporary and permanent storage of data. This may have interface as simple as RD/WR signal with data-address bus and chip select with output enable. ...
4
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3answers
242 views

Why is L1 cache faster than L2 cache?

I'm trying to understand why certain CPU cache memories are faster than others. When comparing cache memory to something like main memory, there are differences in memory type (SRAM vs DRAM), and ...
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0answers
66 views

DDR3 interface to Lattice ECP3 FPGA - TDQ

I'm looking at implementing a Lattice ECP3 FPGA with an interface to DDR3. I'm looking at the schematic for the evaluation board: Lattice ECP3-Versa Eval Board User's Guide I am unfamiliar with DDR3 ...
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2answers
351 views

What do memory configurations like “256Kx18” mean?

This is a beginner question here. When choosing memory ICs, one of the options is the memory size/configurations. I understand the size part, but what does the "16Kx9" mean? It seems the same memory ...
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1answer
69 views

Do design of a VHDL module as APB Master has any practical difficulty?

I went across VHDL codes for memory architectures, which contains modules designed as AHB masters, AHB slaves, Bridge, and APB slaves. But no APB slaves. Is there is any specific reason for excluding ...
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3answers
101 views

What sort of a ferrite core will I need to make core memory?

I am building a homebrew computer using core memory. What sort of a ferrite core will I need?
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2answers
307 views

CPU Cache implementation in VHDL

I have been assigned a project of designing a cache memory with some advanced features (using efficient cache algorithms) and implementing it in VHDL. I know the required theory for carrying out this ...
1
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1answer
108 views

Reading RAM externally in a running system by intercepting the memory bus or replacing the RAM chips?

I wonder if it is possible to modify a consumer electronic system (TV, phone, embedded device, etc.) so that it is possible to read and possibly write the contents of its RAM chips while system is ...
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2answers
141 views

Organization of large memory using memory blocks

I found the following question in a test. I am not looking for an answer to the question per se, but I am having difficulty understanding the part in bold, as explained below. A main memory unit ...
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2answers
125 views

How to design a Design a 32 x 4 memory using two 16 x 4 RAM chips

I have this task to "Design a 32 x 4 memory using two 16 x 4 chips". But on Google I can't find what a 16 x 4 RAM is. I know the basics of latch, flip-flops, TTL, CMOS etc. But I can't put this ...
0
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1answer
320 views

Writing and Reading From FLASH ROM on Nexys 2 Spartan 3-E FPGA

I am a newbie to VHDL and FPGA platform. I have a Nexys-2 Spartan 3E FPGA board which is provided with a 16 MB Flash ROM.I want to preload first 10-20 memory locations of this ROM,each location with ...
3
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0answers
198 views

FPGA link to external memory

I am trying to use the cellular ram on the Nexys 4 FPGA development board. I am using Xilinx Vivado and would like a Microblaze soft core processor to be able to perform reads and writes. So far I ...
21
votes
1answer
2k views

Why does flash memory have a lifespan?

I've read that flash memories can "only" be reprogrammed 100000 to 1000000 times, until the memory storage "deteriorates" Why exactly does this happen with flash and not other memory types, and what ...
2
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0answers
162 views

How to implement memory mapped IO

I am describing a system in VHDL. This system already contains a processor, a DDR SDRAM controller and a VGA controller. VGA reads pixels from SDRAM (already validated and proven in FPGA). Although ...
4
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1answer
225 views

Why must flash memory be written/erased in pages/blocks ?

Title says it all. I'm trying to understand the workings of flash memory technologies, at the transistor level. After quite some research, I got good intuitions about floating-gate transistors, and ...
0
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1answer
107 views

A program to add 6 bytes of data and store sum and carry in 8085 instruction set

I have a question on 8085 instruction set. A program to add 6 bytes of data stored in memory starting from 4500h. must use b register to save any carries and finally store the sum and carry at two ...
1
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2answers
108 views

How to predict the memory size and gate count given source code

Excuse my poor English :-) I am in a software (for face detection) team and we co-work with the hardware team. If we give the source code to the hardware team, they will try to implement it with ...
1
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2answers
307 views

Professor said my embedded system design is incorrect, what did I get wrong?

The problem: Your embedded system has an 8-bit microprocessor, which has a 16-bit address bus. In addition, you have a 32-Kbyte FLASH chip, and a 8 KByte RAM chip. You want to locate the FLASH chip ...
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1answer
77 views

What is the Global Descriptor Table memory type?

What type of memory type is used for the Global Descriptor Table in an Intel Core 2 CPU? Is it just EEPROM or does the CPU normally use another type of NVRAM?
2
votes
2answers
126 views

How does the Array allocated in the stack?

I was testing the code below on my STM32 board, but I could't understand how the array was being allocated in the stack. I'm assuming that there are 200 bytes of memory in STM32. Here is the code: ...
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0answers
67 views

Averlogic fifo experience?

I've got an fpga board that utilizes an averlogic fifo -- AL460. This should be the easiest part in the world to use -- it's basically a huge dual ported fifo with two independent clocks. I was ...
0
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1answer
80 views

Microchip, memory measured in IEC?

It doesn't say on the data-sheet, but I'm curious where i can find if Microchip uses IEC or SI as standard for there memory sizes. For example: ...
4
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2answers
135 views

Compilers and MSB identification for Data types

I would like to know two things that is making my head quite confusing these days. If i allocate an int in C18 compiler I know ...
0
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0answers
23 views

Direct-Mapped Cache [duplicate]

I am a bit confused about the tables with direct mapped cache. I've attached picture of the problem, I know some stuff but, I don't know how to determine the size of the tag, offset and set. Can ...
1
vote
3answers
76 views

Frame memory (SRAM) size for an image

I am now reviewing a paper about hardware implementation and it says by cropping the 128*96-pixels from 160*120-pixels, the size of the frame memory (SRAM) can be reduced to 1/10. I don't get it. ...
2
votes
3answers
85 views

How to write to block memory?

I need to write 16x16 bit data to block memory. I am using RS232 to send data. To get 16 bit data, I send 2x8bit. Now, how can I write my data to the memory? I have a write signal and 16 bit input ...
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2answers
128 views

Direct Mapped Cache [duplicate]

A computer using a direct-mapped cache has \$2^{24}\$ words of main memory and a cache of 256 blocks. Each cache block contains 64 words. How many blocks of main memory are there? What is the format ...
0
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0answers
92 views

Virtual Memory, Cache, and TLB's

I recently asked this question over at stackoverflow, but I was told by a user that it was off-topic, so I am posting it here since it's more of a hardware question. I'm trying to study for an exam ...
0
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2answers
210 views

Memory Addressing

How many bits would you need to address a 4M X 8 memory if the memory is byte-addressable? the memory is word-addressable with a word size of 16 bits? the memory is word-addressable with a word size ...