Consider instead more specific tags, e.g., dram, sram, flash

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How does Xilinx MIG AXI interface map to DDR PHY pinout?

At the bottom of page 156 of UG586 I can understand how the User Address maps to the PHY pinout. However, I can't understand page 155 of the same manual. How does the 32-bit Microblaze address space ...
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50 views

Determining memory address width from memory size

Given a computer A with 1024 x 16 memory and a computer B with 16K x 32 memory, how big are the registers of an Accumulator, program counter, instruction, temporary register, address register, data ...
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31 views

In an SDRAM how do address rows/columns and rank width and bank width relate to the total memory size?

I have a Micron SDRAM (MT16KTF1G64HZ-8GB). The size of the memory is 8GB. I did some calucaltions and 8GB of data means 2^36 bits capacity. Now when I look in the Micron data sheet, the row address is ...
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49 views

How to quickly fill up the entire DDR memory using Xilinx tools?

I have a board with a DDR3 memory and a Virtex 7 FPGA. I have used Xilinx MIG to create a memory controller and I am able to succesfully read/write to the memory using Microblaze registers. I would ...
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30 views

Calculate Instructions per second MIPS

I'm trying to solve this problem for a MIPS processor: Suppose the data cache is perfect but the instruction cache has a 5% miss rate. On a cache miss, the processor stalls for 20 ns to access main ...
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39 views

How many NAND flash chips (measured in Gb) are required for a 32GB USB drive? What is the economic relationship between the two?

NAND Flash Contract Price http://www.insye.com/dp/NANDFlashContractPrice.aspx Context, I am purchasing about 200k USB drives. I sent it out to competitive bid but I want greater insight into the BOM ...
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32 views

AT91SAM9260 Does not recognize 128 MBytes SDRAM

Recently began to use AT91SAM9260 processor on the Olimex board. From the data sheets of the processor, it seems to support up to 256 MBytes of SDRAM. So I replaced both of the old K4S561632C-TC/L75 ...
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26 views

Verilog module to read/write a register

I would like to create a module that can change the value of a register passed to it (+/- 1) using an inout port. I wrote this: ...
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1k views

How do you determine how much flash/RAM you need for a microcontroller?

Let's say you are starting an embedded project with some known functionality. When you select a microcontroller how do you select how much RAM you need? Do you use a developer board and code your ...
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32 views

Implementing Processor Core for Cache Module in Verilog

I have written a simulation module for a Direct Mapped Cache (consisting of data, tag, and valid rams and cache controller) in Verilog. I now want to implement a Processor Core/Driver (also in ...
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52 views

Small system on a chip : Power consumption [closed]

This question is lying somewhere between electrical engineering and computer science, however I felt that this forum suited my question the best. I post this question because I feel that this kind of ...
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216 views

Constructing decoder 5/32 using smaller ones, without enable

I need to construct a decoder 5/32 using any number of 2/4 and 3/8. How do I start? With Enable it's not hard to figure out, but without them it gets complicated. Advice?
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53 views

Estimating processing power required

I am currently in a computer engineering class and I have been asked to design a product that can guide blind people. In my fictitious product I am going to implement a module to detect distances (a ...
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2answers
45 views

Series Termination DDR

I was Going through some application notes for the placement of Series termination of DDR and found it should be placed near to the processor. But if I am not wrong termination resistor are placed to ...
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1answer
87 views

STM32F429 / STM32F439 read-while-write from two memory banks. Prevents stalling CPU?

I have been reading up on the STM32F429 flash memory (2MB version). From the STM32F4 reference manual I found out that it has two memory banks and supports read-while-write (RWW), which means it can ...
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43 views

Flash memory range on STM32F429II

I am reading the STM32F429II data sheet and looking at page 84, which shows the memory mapping. The chip has 2MB of internal flash memory, but the data sheet is general for all STM32F427xx/STM32F429xx ...
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136 views

What's the difference between a SRAM cell and a D-Latch?

They both seem identical - they both have an "enable" and a single input. When enable is high, the value stored in the element is set to the input. Are they functionally different in any way? (I know ...
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172 views

STM32F4 NAND flash via FSMC, difference between bytes written and read back

I have a Waveshare Open407V-D development board, basically a "motherboard" in which an STM32F4DISCOVERY kit is fitted (this kit, for those not familiar with it, is made by ST itself and based on the ...
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61 views

RAM memory modelling in Verilog

I am trying to model a 0.125GB RAM memory in Verilog using ModelSim of width 512 bit using memory chips of width 32 bit. So I have created a 32 * \$\2^{18}\$ memory array whose code is as follows: ...
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79 views

Exploring MCDRAM

I was going through the below link and found one peripheral named MCDRAM. If i am not wrong it looks like a Multichannel memory device which is integrated on same package. Can someone explain what ...
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2answers
35 views

Flash Memory Failure Modes - Block Failure

My understanding is that typical flash memory failures, such as those due to erase cycles, occur at the bit level. I have a flash in which entire blocks (actually two blocks) are failing. Is there a ...
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646 views

memory segmentation in 8086

If the external memory (1 MB) in 8086 based system is segmented into code, data, stack and extra which are all 64 kB, what do we do with the rest of the memory? Does it go waste?
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68 views

Calculate Paging System

I have this problem to solve and I have the answers, but I'm trying to understand the concepts behind it. A paging system has the following parameters: 2^32 bytes of physical memory; page size of ...
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33 views

Virtually indexed physically tagged cache

I'm trying to understand the concept and calculations for solving this problem. I know the answer is 10 bits. ...
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48 views

Determining physical address for logical address

I have a simple segmentation system with the following segment table: ...
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65 views

IC for 4 Kbytes of RAM [closed]

Is there a Memory IC for 4Kbytes of RAM? I'm trying to make a schematic capture in Proteus and I need a Memory IC for 4Kbytes of RAM, I've searched throughout the library and I can't find one, tried ...
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108 views

Why All DDR's (DDR, DDR2, DDR3) internal clock sets to 200MHz

If we see the DDR Upgrade technology explain below the internal clock of all DDR is set to 200 MHz. DDR For example,DDR-400 Efficient frequency data bus is 400 MHz True clock rate (IO buffer ...
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56 views

Role of the MMU in a Page Fault Swap

When a virtual memory address outside the range of loaded into physical RAM is referenced and a page fault occurs, does the Memory Management Unit rely on DMA (Direct Memory Access) to swap the ...
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96 views

How much power does a GPU actually use when only doing PCIe I/O, or only compute?

I hope this is the right sight to ask such a question, if not please be kind and direct me elsewhere. I have some discrete GPU with a TDP figure of X watts. Now, sometimes the GPU does Only ...
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3answers
83 views

How big is a single RAM cell?

I am studying on my own how the PC works and I can't understand one thing. A 32 or 64 bit processor differs for its ability to allocate 2 ^ 32 or 2 ^ 64 addresses for the cells of the RAM. What I do ...
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95 views

Role of the Memory Management Unit

I know that the first instruction stored in BIOS is "mapped" to memory address 0, and that a signal on the reset pin to the microprocessor causes this instruction to be fetched, beginning the POST and ...
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2answers
312 views

Memory alignment is always power of 2

I've found the memory alignment is always equal to power of 2. Google said that such amount of alignment allows modern computers to perform read more fast. Ok, what exactly problem we would gain if we ...
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73 views

LPC43xx External Static Memory - Multiplexing of Address/Data lines

We would like to tightly-couple a FPGA with a µC by means of the external static memory memory controller, thereby effectively mapping the FPGA registers into main memory of the µC with maximum ...
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74 views

Shape Memory Metal framed sail

I am working on a costume prop that utilizes a triangular cut sheet of emergency blanket spined with a single 12" long, .04" dia piece of nitinol wire that has a transistion temp of 115deg F. My plan ...
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46 views

Is a D Type Edge triggered Master Slave flip flop considered a 1bit memory cell?

So in class we talked about how a D-type edge triggered flip flop is considered a 1bit memory cell. I think this is the same for a D-type latch. My question is, since a D-type edge triggered master ...
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53 views

Calculating Cpi with Miss Rate

In my assignment I have the following question: The processor has a clock rate of 1 GHZ. The miss rate in the instruction cache is 1.5%. The miss rate in the data cache is 4%. 30% of the instruction ...
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3answers
24 views

Spatial Locality in Cache - Which addresses are loaded?

I don't understand quite well the concept of spatial locality in cache. I understand that when there is a miss in the cache, not only the specific address we write is loaded into the cache, but also ...
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63 views

Interpolate DDR3 timing from DDR3-1600 to DDR3-1866?

This is an interesting math + electrical engineering problem. I have DDR3-2133 memory but it had presets for DDR3-1600 and DDR3-2133 but the fastest my motherboard supports is DDR3-1833. That means I ...
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1answer
67 views

Why do dual-rank DIMMs have twice the bandwidth of quad-rank DIMMs? [closed]

I'm looking at the RAM compatibility table for my motherboard: and it shows that dual-rank (DRx4) memory modules can operate at twice the speed of quad-rank (QRx4) memory modules (1600 MT/s vs 800 ...
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63 views

Options for semi-permanent memory in a low-energy setting

(Hopefully this will be broad enough to be on-topic.) I'm looking for options to store several megabytes of data over the period of a few weeks in a coin-cell powered application. The data doesn't ...
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1answer
86 views

Selecting external RAM for an ARM static memory controller

So I'm going through the datasheet for a device by Atmel (AT91SAM) and it shows the followings: This SMC is capable of handling several types of external memory and peripheral devices, such as ...
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1answer
113 views

Designing Flash Memory to USB Mass Storage bridge

I've been scratching my head at this for a while now. I'm trying to build a device that records audio using a VS1053 encoder IC to some sort of SPI flash memory. I want to be able to download the ...
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46 views

Volatile and non-volatile memory for recording + which ARM?

I need to design a device that does audio recording for several minutes. It should be able to keep the data even with a battery removed. Data is sampled @ 96KHz 24bit depth so the MCU is not enough to ...
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261 views

RAM compression. Why hasn't it caught on?

I was reading an journal on Hardware Compression of RAM and I was wondering why something like this hasn't become commonly used. Something like this would be really useful to servers or the kid at ...
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1answer
44 views

Multi-processor memory controller chips

I am trying to find a controller chip for either SRAM or S/DRAM which can properly manage access of the memory from one or more devices (i.e. microprocessors). I have been up and down Google and all I ...
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4answers
555 views

How can one make an analog voltage memory circuit?

I am looking for a circuit that can, on input, remember a certain voltage and output that voltage indefinitely even after the input has been taken away. The circuit should not change its output until ...
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63 views

Microchip 23LC1024 driver for Atmel XMega

Is there driver or any example code available for 23LC1024 SRAM memory implemented with Atmel XMega or mega-series microcontroller?
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316 views

Are SR latches suitable to be used as RAM?

I've just recently started to become interested in electrical engineering after a couple years of programming and software development. I've built a 4 bit ALU using a logic gate simulator and now I ...
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114 views

MSP430F5438A: How can I see the flash memory content in CCS?

I have to establish a file transfer mode between C# and CCS. To make sure the text files has transferred properly, after sending a file I read it from C# to compare with the origin. I need to look at ...
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320 views

Three way set associative cache with LRU replacement

So I am going through a homework exercise, and I am not understanding the solution to the problem. We are given a sequence of memory references and we are to use a three-way set associative cache with ...