Consider instead more specific tags, e.g., dram, sram, flash

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13 views

does this ensure i am reading from the ram?

I at the moment trying to reverse engineer something i made a long time ago but never understood why it is running so slowly. I have a Zybo board, with an Zynq 7010s chip ons which has dual ...
0
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0answers
28 views

Where is the variable stored?

I at the moment programming on a Zybo board, which has a Zynq chip on it, which tightly integrates a dual arm processore with an FPGA. I an on the Arm implemented a game which stores the game image ...
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2answers
67 views

Why are two LEDs on? is 7489 broken?

This is a follow up question to this question. I have attempted to draw a schematics of my setup for the 7489 below. Without the switch closed, the LED D1 is on. Then the switch is closed, then also ...
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2answers
69 views

Schematics for using IC 7489 memory

I bought two SN7489 because I wanted to learn how the memory chip works. I followed the datasheet. I don't seem to be able to get it to work. After playing around for some time with the IC, it got ...
0
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1answer
30 views

Baseband Processor

If a device can only be activated by way of RF then I would tend to believe that the BB processor (embedded via ASIC design) would need to be active and powered on yes ? If correct then does it have ...
1
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1answer
61 views

A simple memory chip

I think I understand how one can use an Arduino to program an external EEPROM memory chip. I am wondering if there are any memory chips that don't need any type of micro controller to operate. So, for ...
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4answers
97 views

Shouldn't all the NAND gates in your computer activate at the same time? [closed]

When you plug in your computer, shouldn't all the NAND gates activate (because the output turns on when the both inputs are off) at the same time, causing chaos? For example: RAM is made of memory ...
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2answers
92 views

How does an SD card communicate with a computer? [closed]

Could someone please give me a concise explanation to how an SD card sends and receives data from a computer. Does it do this one bit at a time? How does the computer/SD card combine these individual ...
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2answers
45 views

How do SRAM bit line “gates” work?

I'm currently learning about the operation of 6 transistor static random access memory cells and I've hit a wall in understanding exactly how the read/write operations work. More specifically I don't ...
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0answers
60 views

Memory Interface with a Multiplexed Address/Data Bus

I want to implement a memory interface in VHDL between an FPGA and a processor. The address/data bus is a 16-bit multiplexed bus with an ALE, write protect and BusWait. According to the NVIDIA Tegra 3 ...
0
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2answers
72 views

Adding to a circuit the ability to “remember” the last chosen settings when turned off or disconnected

If you could please bear with me: I'm just starting out in electronics and I've had an idea for a nice experimental mod that will also be useful. I've recently bought a pretty cool little 8 x 8 LED ...
1
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1answer
50 views

conventions in signals naming in datasheets

What does it mean when the datasheets lists the signals between parentheses as shown in the figure below?
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1answer
102 views

DDRx Memory: Memory Clock vs I/O Bus Clock?

When referring to DDR/DDR2/DDR3/DDR4 memories, I am not able to understand the difference between memory clock and I/O clock. As per: https://en.wikipedia.org/wiki/Double_data_rate DDR-200 - Memory ...
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1answer
69 views

Where to store non-volitile variables on ARM microcontroller

Noob question here. I have only a little experience with microcontrollers and all that experience was limited to the 8051. I am working on a project and would like to use the ARM cortex M4 ...
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0answers
43 views

Is it possible to save the “END” address in program memory of 8051 uC inside a register?

I have just started learning 8051. One of the proposed exercises says that "immediately after" the end of the program code inside program memory, there's some data of interest that i should read. For ...
1
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1answer
71 views

Is my understanding of D-Flip Flop wrong?

So I am working on: http://www.nand2tetris.org/ and I am having a hard time understanding the D-Flip Flop, or maybe I should say, how Logism represents it. I have this circuit and this is the current ...
1
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1answer
31 views

What is traffic generator (while using Xilinx Memory Interface Generator)

I am trying to use the Memory controller Block in my Xilinx Spartan 6 FPGA to set up an interface with LPDDR memory. I read the MCB User guide, and I am quite clear about how it works, and how I would ...
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4answers
70 views

Best value to overwrite old to tell if memory is not used on eeprom

I have an EEPROM I want to store CRC32 hashes on between 0x0000 and 0x008C. In this range I need a way that I can erase one of the hashes and overwrite its bytes to a default number. By doing this I ...
4
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4answers
925 views

What is the densest part of an integrated circuit?

Also, which part of an integrated circuit has been affected by Moore's law most? Is it the memory (caches, embedded memory, etc.)? Or is it the logic (execution units, control units, etc.)? Or ...
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0answers
47 views

GDDR Power Calculation

I'm wondering if there is any publicly available documents or research papers that cover GDDR power estimation? Micron provides very nice documentation and calculators for DDR up to DDR4, however I ...
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3answers
85 views

How to record input from multiple microphones so there is no latency between microphones due to writing to memory

I am going to be doing some beam forming. I understand the concept and plan to record all the data then analyze the signals from multiple microphones to figure out locations of some noises (there will ...
-2
votes
1answer
83 views

A computer system has RAM of 32K bytes and 64 peripherals. What is the number of distinct addresses required? [closed]

Is it correct to assume that the number of addresses for 32k of ram is 2^15 addresses? Then for the peripherals is it 2^6 addresses?
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1answer
74 views

Terabyte memory controller ICs [closed]

I am thinking of creating a PCI-Express card to support from 1TB up to 8Terabytes of RAM (for servers). I will have to modify glibc in order to use it, but it is not a problem. The problem is to make ...
0
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1answer
67 views

Fast write/read on NVRAM with Windows

I am trying to find a solution to create a 4MBit NVRAM module (FRAM or SRAM, doesn't matter) with a standard PC with Windows. I want to store up to 1MB of data in less than 1 second with 50-100 write ...
3
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1answer
108 views

DDR4 frequency decrease if populated with more than one module per channel

I'm curious how one particular company Gigabyte ensures its server motherboards to run at the maximum supported memory frequency even when there're two or three DIMMs per channel (of coure we're ...
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3answers
256 views

Is cache memory unnecessary in microcontrollers?

Do we use cache memory in microcontrollers, if not, why not? If yes, what is its application in embedded systems or it is enough just to have RAM?
3
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1answer
67 views

Memory Power Supply

Kindly any one give the clarification on this. While going through a DDR Memory data sheet, I have found two (more than that) power supply pins. What is the necessity of this DLL power supply ...
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2answers
160 views

What is the main difference between SRAM and DRAM in the automotive industry? [closed]

What are the main differences between SRAM(static RAM) and DRAM(dynamic RAM) in the automotive industry? What kind of memory does the different ECUs use? I'm interested in the BCM(body control ...
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0answers
47 views

Index in block ram is offset by one from position of write

I am having an issue with block ram I am using to create a table to powers of a 64 bit floating point number. I store powers between x^1600 and x^-1600. For some reason when I try to read the table ...
9
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6answers
824 views

memory for the simplest possible computer (Pi0K)

I'd like to build the simplest possible computer. I don't care about speed or storage, indeed having slow speed and low storage is a huge advantage as I want to build it out of transistors (ideally ...
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0answers
80 views

Best device to read/write memory on multiple architectures?

tl;dr: I want to read/write memory from a PIC MCU and an EEPROM, both of which are soldered to an experiment board. I would like to explore programming and debugging ARM in the near future. Which ...
1
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3answers
42 views

Microcontroller Memory reliability : Info Memory vs External Flash

I had a small query which I couldnt find a short answer in google. for storing small amount of data ( say 8 bytes ) in an embedded system (containing an external Flash too), is it preferred to store ...
0
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3answers
193 views

Power of a microcontroller, but with more memory - what fulfils this need? [closed]

I'm a hobbyist with little experience. Usually I play with Arduino Pro Mini or ESP8266. I can make them do simple things I want, but for obvious reasons I can't give them too many features at once. ...
2
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0answers
113 views

How to interface with the Apple Watch for the purpose of accessing its internal memory? [closed]

Unlike other apple products which can be directly connected to a PC via USB, the Apple Watch is completely wireless from the point it exits the factory, as far as I am aware. Aside from a 6-pin ...
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1answer
45 views

Are there any performance effects of using radiation hardened memory units?

Are there any performance related effects of using radiation hardened memory units as compared to non-hardened ones having the same configuration except the protection it should provide from radiation ...
-1
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2answers
394 views

How do you calculate Byte Offset?

I am confused by the concept of byte offset. In my textbook the examples always show the word aligned byte offset as being two bits but doesn't really explain how they arrive at that value. It says ...
0
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1answer
44 views

Choosing components to clone ZX80

I have an idee fixe to make a clone of Sinclair's ZX80 computer. So now I'm trying to find out which ICs I need for the basic prototype - and here are a few questions: it seems ...
3
votes
1answer
234 views

STM32 chip specs do not match the datasheet?

I've recently purchased a couple of STM32L152R8T6 chips from a local electronics shop. According to the page 11 of the datasheet, this chip is supposed to have 10K of SRAM and 64K of FLASH. However, ...
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votes
1answer
103 views

how to determine the column address

Does a normal ram require to have row and column address decoder? From the ram verilog coding that i get from http://www.asic-world.com/examples/verilog/ram_sp_sr_sw.html. In the verilog coding, it ...
0
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1answer
73 views

Problem with glue logic/memory decoding on a 6502 project

I have a problem understanding the following schematic, specifically the "Glue Logic(Memory Decoding)" section in the lower half middle: This is a simple breadboard computer based on a 6502 CPU ...
1
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1answer
25 views

DRAM timing with row and column decoders

Consider a 64Kx1 DRAM memory which means the number of rows is 256 and the number of columns is 256. In other words, two 8x256 decoders are needed for selecting the right row and column. Since, each ...
0
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4answers
216 views

direct mapping cache question

I have been doing the question below in what I thought was the correct way. After doing some more reading I am now slightly confused and would appreciate some clarification. Previously I was just ...
0
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1answer
61 views

GB cart with Ram, Rom, no MBC. How do they work?

Gameboy cartridges, without memory banking, have 32KB of ROM and no RAM. To have more, carts tend to use a MBC (Memory Bank Controller) IC to add RAM and ROM, among other things. However, two ...
0
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1answer
38 views

memory interfacing with banks [closed]

In the concept of memory interfacing (cpu<=>memory), it is desirable to have two banks for odd and even addresses. The reason goes back to the history when manufacturers increased data bus width ...
0
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4answers
127 views

Can binary code such as an embedded OS or user application code be stored using silicon physical gates

Hello as the questions describes I'd like to know whether it's possible to do this ? Can binary executable code which is executed by a processor core possibly be stored using physical silicon gates ? ...
-1
votes
1answer
63 views

Hashtag Beside Pins names [duplicate]

What does Hashtag (#) means when it's added beside some pins names in datasheets..like WE# in the flash memeory pinout or RI# in RS232 FTDI datasheets??
1
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1answer
79 views

Memory timing values for microprocessor (8086)

There is something vague with the memory timing operation of 8086 microprocessor as I read from many sources. There is a TAVDV which is the time from when a valid address goes on the bus until a valid ...
0
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1answer
70 views

How does a flip-flop circuit keep it state?

When reading about the difference between SDRAM and SRAM (electronically), I understand that SDRAM requires the dynamically charging of the capacitors to maintain their states. I do not get how SRAM ...
2
votes
2answers
840 views

What is the difference between full and partial address decoding?

Could someone please explain the difference between full address decoding and partial address decoding? I am reading the chapter on digital logic in "Structured Computer Organization", 6th ed. by ...
2
votes
1answer
79 views

SRAM vs DRAM against single-event upsets

SRAM basically stores a bit in a flip-flop made of a few transistors, while DRAM stores a bit in a capacitor driven by a single transistor. Would this mean that SRAM is less likely to face ...