Consider instead more specific tags, e.g., dram, sram, flash

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38 views

Fast write/read on NVRAM with Windows

I am trying to find a solution to create a 4MBit NVRAM module (FRAM or SRAM, doesn't matter) with a standard PC with Windows. I want to store up to 1MB of data in less than 1 second with 50-100 write ...
0
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0answers
17 views

LPDDR minimal clock frequency

I found on an lpddr memory sheet, it is possible to use those rams with any low clock frequency as long as application meets with signaling standard and memory refresh requirements. Also some mention ...
3
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1answer
75 views

DDR4 frequency decrease if populated with more than one module per channel

I'm curious how one particular company Gigabyte ensures its server motherboards to run at the maximum supported memory frequency even when there're two or three DIMMs per channel (of coure we're ...
1
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3answers
167 views

Is cache memory unnecessary in microcontrollers?

Do we use cache memory in microcontrollers, if not, why not? If yes, what is its application in embedded systems or it is enough just to have RAM?
3
votes
1answer
61 views

Memory Power Supply

Kindly any one give the clarification on this. While going through a DDR Memory data sheet, I have found two (more than that) power supply pins. What is the necessity of this DLL power supply ...
0
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2answers
107 views

What is the main difference between SRAM and DRAM in the automotive industry? [closed]

What are the main differences between SRAM(static RAM) and DRAM(dynamic RAM) in the automotive industry? What kind of memory does the different ECUs use? I'm interested in the BCM(body control ...
0
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0answers
40 views

Index in block ram is offset by one from position of write

I am having an issue with block ram I am using to create a table to powers of a 64 bit floating point number. I store powers between x^1600 and x^-1600. For some reason when I try to read the table ...
9
votes
6answers
598 views

memory for the simplest possible computer (Pi0K)

I'd like to build the simplest possible computer. I don't care about speed or storage, indeed having slow speed and low storage is a huge advantage as I want to build it out of transistors (ideally ...
0
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0answers
26 views

LCD CGRam acting strangely

Ok, so I recently got an LCD with an I2C backpack attached and after a while I decided to try creating custom characters. For some reason I couldn't get it to work and every time I wrote the custom ...
1
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0answers
57 views

Best device to read/write memory on multiple architectures?

tl;dr: I want to read/write memory from a PIC MCU and an EEPROM, both of which are soldered to an experiment board. I would like to explore programming and debugging ARM in the near future. Which ...
1
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3answers
21 views

Microcontroller Memory reliability : Info Memory vs External Flash

I had a small query which I couldnt find a short answer in google. for storing small amount of data ( say 8 bytes ) in an embedded system (containing an external Flash too), is it preferred to store ...
0
votes
3answers
164 views

Power of a microcontroller, but with more memory - what fulfils this need? [closed]

I'm a hobbyist with little experience. Usually I play with Arduino Pro Mini or ESP8266. I can make them do simple things I want, but for obvious reasons I can't give them too many features at once. ...
2
votes
0answers
91 views

How to interface with the Apple Watch for the purpose of accessing its internal memory? [closed]

Unlike other apple products which can be directly connected to a PC via USB, the Apple Watch is completely wireless from the point it exits the factory, as far as I am aware. Aside from a 6-pin ...
1
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0answers
27 views

Are there any performance effects of using radiation hardened memory units?

Are there any performance related effects of using radiation hardened memory units as compared to non-hardened ones having the same configuration except the protection it should provide from radiation ...
-1
votes
2answers
86 views

How do you calculate Byte Offset?

I am confused by the concept of byte offset. In my textbook the examples always show the word aligned byte offset as being two bits but doesn't really explain how they arrive at that value. It says ...
0
votes
1answer
43 views

Choosing components to clone ZX80

I have an idee fixe to make a clone of Sinclair's ZX80 computer. So now I'm trying to find out which ICs I need for the basic prototype - and here are a few questions: it seems ...
3
votes
1answer
160 views

STM32 chip specs do not match the datasheet?

I've recently purchased a couple of STM32L152R8T6 chips from a local electronics shop. According to the page 11 of the datasheet, this chip is supposed to have 10K of SRAM and 64K of FLASH. However, ...
-1
votes
1answer
40 views

how to determine the column address

Does a normal ram require to have row and column address decoder? From the ram verilog coding that i get from http://www.asic-world.com/examples/verilog/ram_sp_sr_sw.html. In the verilog coding, it ...
0
votes
1answer
31 views

Problem with glue logic/memory decoding on a 6502 project

I have a problem understanding the following schematic, specifically the "Glue Logic(Memory Decoding)" section in the lower half middle: This is a simple breadboard computer based on a 6502 CPU ...
1
vote
1answer
23 views

DRAM timing with row and column decoders

Consider a 64Kx1 DRAM memory which means the number of rows is 256 and the number of columns is 256. In other words, two 8x256 decoders are needed for selecting the right row and column. Since, each ...
0
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4answers
93 views

direct mapping cache question

I have been doing the question below in what I thought was the correct way. After doing some more reading I am now slightly confused and would appreciate some clarification. Previously I was just ...
0
votes
1answer
51 views

GB cart with Ram, Rom, no MBC. How do they work?

Gameboy cartridges, without memory banking, have 32KB of ROM and no RAM. To have more, carts tend to use a MBC (Memory Bank Controller) IC to add RAM and ROM, among other things. However, two ...
0
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1answer
35 views

memory interfacing with banks [closed]

In the concept of memory interfacing (cpu<=>memory), it is desirable to have two banks for odd and even addresses. The reason goes back to the history when manufacturers increased data bus width ...
0
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4answers
101 views

Can binary code such as an embedded OS or user application code be stored using silicon physical gates

Hello as the questions describes I'd like to know whether it's possible to do this ? Can binary executable code which is executed by a processor core possibly be stored using physical silicon gates ? ...
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1answer
44 views

Hashtag Beside Pins names [duplicate]

What does Hashtag (#) means when it's added beside some pins names in datasheets..like WE# in the flash memeory pinout or RI# in RS232 FTDI datasheets??
1
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1answer
55 views

Memory timing values for microprocessor (8086)

There is something vague with the memory timing operation of 8086 microprocessor as I read from many sources. There is a TAVDV which is the time from when a valid address goes on the bus until a valid ...
0
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1answer
53 views

How does a flip-flop circuit keep it state?

When reading about the difference between SDRAM and SRAM (electronically), I understand that SDRAM requires the dynamically charging of the capacitors to maintain their states. I do not get how SRAM ...
2
votes
2answers
250 views

What is the difference between full and partial address decoding?

Could someone please explain the difference between full address decoding and partial address decoding? I am reading the chapter on digital logic in "Structured Computer Organization", 6th ed. by ...
2
votes
1answer
52 views

SRAM vs DRAM against single-event upsets

SRAM basically stores a bit in a flip-flop made of a few transistors, while DRAM stores a bit in a capacitor driven by a single transistor. Would this mean that SRAM is less likely to face ...
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0answers
82 views

Can this SDRAM be used with STM32F7?

I have STM32F7 (which has a Flexible Memory Controller capable of interfacing SDRAMs) and I want someone to check if it is able to interface this SDRAM - IS42S32800D ...
2
votes
2answers
314 views

Why am I 1 digit out, when calculating space from two addresses?

My STM32F407 microcontroller datasheet states that my flash region is between the following addresses: 0x08000000 to 0x080FFFFF I want to calculate the amount of ...
2
votes
1answer
50 views

how to save counter on lcd in mikroc

My code is about button counter .which appear on lcd 2x16 .pic18f46k20 .i want when i turn power off and turn on it again it should show the last number it count . how to make data saved in pic and ...
1
vote
1answer
522 views

Is there a way to build a 2k*12 RAM using only 2 4k*4 Chips

Okay so I know when I need to build a parallel design I can put them near each other and make a 4k*8 to expand the databus. But on this one I only need to use half of them and the databus length is ...
1
vote
2answers
100 views

What's the simplest way to store 1 bit after a device has been turned off? [duplicate]

Is there a simple way to store a boolean value that persists when power has been turned off?
0
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0answers
73 views

Can I use DDR RAM as SDR (single data rate) RAM?

I have STM32 microcontroller which has "Flexible External Memory Controller" (FEMC) which supports only SDRAM (SDR) memory. I want to know if I can connect DDR memory to this FEMC? I know ...
0
votes
1answer
49 views

What kinds of parallel RAM are there?

I have basically no experience in electrical engineering or hardware design, but as an experienced software engineer, I recently took an interest in designing my own CPU. I followed the ...
0
votes
1answer
103 views

What are the CPU activity steps for the fetch-decode-execute cycle

So in all the phases of the fetch-decode-execute cycle, it says that the "store" phase is used to store any resultant data from the execute phase. What are the CPU steps for that phase? I heard that ...
0
votes
2answers
69 views

How many addresses are required for this system?

If a system has RAM containing 16K bytes with each of them needing their own distinct address and on top of that it has 16 peripherals and they each require 2^4 distinct addresses, then how many total ...
0
votes
1answer
45 views

Read and Identify Memory Diagram

I am so confused, and the book's explanation confuses me more, can anyone explain how to get and identify the following questions displayed? the Book talks about a 2^2 * 3 bit memory but I cant seem ...
0
votes
1answer
91 views

How do I convert ldi R17, 129 to machine code

What I got was 1110 1000 0001 0001 when I converted it to machine language. Is that right? Also what are the CPU activity steps and where am I going to use the address 0xF000? Is this the right CPU ...
4
votes
3answers
137 views

My “flash VS RAM” speed test doesn't work. Why?

In trying to demonstrate that copying information from a string in flash memory to RAM takes longer than copying from the same information in an array in RAM to another, I ran the following code on ...
0
votes
1answer
57 views

What is the diffrences between Bitwise operations in terms of memory consumption, performance?

If I have two input, for example: a= 0110 b = 1010 which one is better (in terms of memory consumption, performance): x = a (XOR) b x = a (AND) b x = a (OR) b And why?
0
votes
1answer
53 views

Connect External Memory through SPI protocol

My idea is to connect a Chip which doesn't explicitly support external memory but has SPI protocol and I2C. So far I understand I have only 3 pins for SPI. Wasn't able to find an approach (schematics) ...
1
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0answers
61 views

Crypto key handling in a uC

What are the general guidelines for handling a cryptographic keys? I know that saving them in plaintext is generally frowned upon, does this hold for true uCs where no user code is run?
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votes
2answers
80 views

Best memory type for data logging

I'm gonna design a board which data logging it's mandatory! I don't think that i have sufficient space in pcb for large parts but i want an embedded flash (dedicated IC). For handling unexpected power ...
0
votes
1answer
54 views

CPU ports and cache controllers

I have seen CPUs conforming to Harvard architecture with dedicated ports for program memory and data memory. I have also seen that instruction and data caches (read-through caches) are connected to ...
0
votes
1answer
88 views

Address Decoding in 8085

RAM (8KB, requires 13 bits A0-A12) Start: 0110 0000 0101 0000 (6050h) End: 1000 0000 0100 1111 (804Fh) ROM1 (8KB, requires 13 bits A0-A12) Start: 1000 0000 0101 0000 (8050h) End: 1010 0000 0100 ...
2
votes
0answers
68 views

What happens after a page fault? [closed]

When a page fault occurs in a Linux system, the interrupt-handler has to figure out the reason why the page fault happened. But how ? Is there anywhere a special number for that !? If yes, where is ...
0
votes
2answers
90 views

Does the databus size matter for determining the range of the memory addresses?

If you have byte addressable memory, does it matter if you have a 32 bit or 64 bit databus for the range of the memory addresses for the words of the memory? E.g. : Assume a 32-bit word. If you have ...
0
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1answer
55 views

Looking into NAND Flash memory

I'm looking into NAND Flash memory to use with my AVR MCU (Atmel Tiny85). I am particularly looking at the 8Gb Spansion S34ML08G101TFI200. I would like to sequentially read the entire contents of the ...