Consider instead more specific tags, e.g., dram, sram, flash

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-4
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0answers
31 views

Calculate the physical address using the following 8086 registers

Calculate the physical address using the following 8086 registers:- (i) SS = 6789 h SP = 00FF h (ii) CS = 4412 h IP = 3900 h Please Help to solve this question .... !! and also tell me ...
0
votes
1answer
50 views

DDR2 decoupling/bypassing - 100nF or 10nF?

I am slightly confused in deciding decoupling/bypass capacitor for DDR2 power supply pins. Some recommendations mention using 100nF and some mention using 10nF. I know that lower capacitance is more ...
0
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3answers
54 views

How to simulate an 8x4 memory using VHDL?

Why does this code: ...
-2
votes
1answer
35 views

How is the concurrency control in hardware?

How a multicore's processor hardware implements concurrency read and write to memory? Is there a special dispatcher, and links that indicate memory usage?
-1
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2answers
75 views

“Not enough memory for stack (1040 bytes needed, 920 bytes available)”

I'm uploading my recent code into a PIC32MX575F512H-80I/PT and I'm getting this message: ...
1
vote
3answers
444 views

Realloc wasting lots of space in my MCU?

I am writing a simple task scheduler and using dynamic memory allocation on my cc430F5137. I agree that it is not a good practice but for the time being lets assume it is my application requirement to ...
11
votes
4answers
2k views

Does a USB mouse have memory that could be used to store malware?

I worry that this might get flagged as too broad, but here it goes: Lately I've been thinking about the possibility of loading data on peripheral devices. One of the most used peripherals is the ...
0
votes
1answer
30 views

DDR2 data rate and data bus confusion

I am reading on DDR2 memory from past few days and have got confused with some of the terms involved. I am mainly confused from discrete memory (single DDR2 memory IC) rather than DIMM module which ...
2
votes
3answers
124 views

How is byte addressable memory implemented?

How is byte addressable memory implemented? If the max word size is 8 bytes (64 bits), does the memory always read 8 bytes and then use logic to select the bytes you actually need (1, 2, 4, 8 bytes)? ...
0
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0answers
38 views

DDR2 memory interface and requirement of termination voltage VTT

I am currently designing a board with Freescale's K series microcontroller and a DDR2 SDRAM memory chip. The interface is point-to-point with only one DDR2 memory interfacing to the microcontroller. ...
3
votes
2answers
70 views

Flash and EEPROM

Atmega16 datasheet says that it has a) 16 Kbytes of In-System Self-programmable Flash program memory and b) 512 Bytes EEPROM. Can a microcontoller have two separate ROMs which can be programmed ...
0
votes
3answers
118 views

USB Flash drives up to 2TB? [closed]

I found USB Flash drives on aliexpress.com up to 2 TB. So much people bought them, and I'm reading feedbacks and 90% says: "It works perfectly, thanks", just a few customers have left a negative ...
1
vote
1answer
62 views

What type of memory allows for most parallel read/write operations per clock cycle in an FPGA?

If you imagine basic motion detection where you have two frames stored in memory: a previous 640x480 frame and the current 640x480 frame, what type of memory (SRAM, DRAM, SDRAM, DDR SDRAM, etc) would ...
0
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2answers
332 views

Designing an 8 x 3 memory chip given 2 4 x 3 chips

I'm working on a problem that asks me to design an 8 x 3 memory chip given 2 4 x 3 memory chips. I'm not sure how to approach this problem. I've looked at the textbook and found various online ...
1
vote
1answer
89 views

Sram in the ARM cortex m3

I load a project into the chip STM32f103ZC whose internal sram is 48kBytes , there are also 2MBytes external sram on the board. But when I download and debug the project,the map file tells that ...
0
votes
0answers
35 views

EMMC memory vs SD memory

I have an embedded application in which I intend to create a database in an external storage. The MCU will be a low power Cortex M4 such as TIVA 129X. I am interested in the types of memory I should ...
0
votes
1answer
35 views

Determine the PROM programming pattern for the memory system using TPB28L42, 512x8 PROM as an address decoder

Question The following figure shows a memory system using the TPB28L42, 512x8 PROM as an address decoder. Determine the PROM programming pattern for the circuit. My Problem My ...
0
votes
1answer
34 views

Memory address 32-bit

I'm working with a Zedboard and I'm printing to the screen memory addresses of consecutive 32-bit float numbers. So the print generates this: ...
0
votes
1answer
17 views

What is the difference between a virtually tagged and a physically tagged memory system?

I study computer architecture and this question came. What is the difference between a virtually tagged and a physically tagged memory system?
0
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0answers
35 views

Can't Search for specific value at RAM - verilog

My module has search for specific value at RAM and then return its location address. when I wrote a test bench, I see that the module didn't work correctly! always the output value is "don't care". ...
0
votes
1answer
44 views

searching in memory at verilog

I need to make a module which responsible to search overall memory to find a specific value and return the address location, but I have the following error after do Synthesize in Xilinx. ...
1
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0answers
54 views

How to know the memory occupied by the various memory segments in a microcontroller

I'm using STM32 based microcontroller, IAR embedded workbench and STlink v2 debugger. I just want to know how to check the memory utilized/used by the program/system in various memory segments like: ...
1
vote
2answers
193 views

When looped, memory address not being displayed sequentially while skipping intermediate memory

I am trying to run through a sequence of memory and display it on the command window. Here is the code: ...
1
vote
2answers
74 views

Will reading serial flash memory wear it out?

I know that a flash memory has limited write cycles. Does it also have limited read cycles? Datasheets of most serial flash memories (like SST25VF series) mention endurance cycles. Does this ...
0
votes
1answer
32 views

LPM equivalent for ATtiny10?

I would like to load some data from the program memory (e.g. a sine table) on my t10. Like on other AVRs the lpm command is for that purpose but it seems not to exist on the t10. I saw this crazy ...
4
votes
4answers
520 views

SRAM swapped address / data bits

Consider the following wiring from a microcontroller to a sram chip: ...
0
votes
0answers
45 views

DIY dual/hybrid pendrive

I have couple of damaged old pen drives lying around. The damage is related just to their fragile USB ports and adding a new port makes them work as new. Now since I am severing some cheap micro USB ...
0
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0answers
15 views

Process technology of Micron Parallel NOR Flash memory M29F200FT/B

I need to learn process technology of the part I stated in the title. Is it micron or nanometer? I am calling micron and the representative can't find anyone to answer my question. They forwarded me ...
3
votes
1answer
86 views

Hitachi HD44780 LCD works exactly 50% of the time

My Hitachi LCD works 50% of the time. Is it a problem is a deboucing reset button issue on the AVR? Why is this happening? Here's a video of what is happening. This does not happen if I write on the ...
2
votes
1answer
458 views

STM32 SPI Peripheral bug?

I'm using STM32F051R8T6 on STM32F0-Discovery board and M25P80 flash IC as a peripheral. I've got the SPI configured in 3-line (+ 1 software chip select line), full-duplex mode and I'm using polling to ...
0
votes
1answer
88 views

8051 micro controller on chip ROM address range? MEMORY SIZE

what is the size for each of these chip ? I know that when we add 1 bit to the memory we double the size. my question is what is the size for a chip range from (0FFF - 0000) so that i keep doubling ...
3
votes
1answer
86 views

What happens when VRAM fails?

When VRAM fails within a video device, there appear to be certain common patterns of visual artifacts. This got me thinking - when VRAM (and RAM in general) fails, what is it that's actually happening ...
0
votes
1answer
41 views

Interfacing 6116 RAM to a data bus

I have a question about interfacing IDT6116SA15TPG SRAM to a tri-state data bus controlled by 74LS244 tri-state buffer. I could not find an old memory like 74LS289 with separated inputs and outputs. ...
2
votes
2answers
160 views

EEPROM Write Cycle Time and Write Cycle Endurance

I have an embedded software application that is copying a buffer from RAM to EEPROM. In this case, the EPROM device is a 28C010 (128K x 8). The copying is done at non-regular intervals, generally in ...
0
votes
1answer
97 views

Why DIMM has 64 bit data width?

Wikipedia’s definition of DIMM says: Most DIMMs are built using "×4" ("by four") or "×8" ("by eight") memory chips with nine chips per side; "×4" and "×8" refer to the data width of the DRAM chips in ...
0
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1answer
66 views

Fundamental reason why RAM is faster then second storage device

Let's consider dynamic RAM - 1 cell = capacitor+ transistor and second storage device, - for example ordinary mmc NAND flash. DRAM, so called volatile memory, need to be refreshed to keep capacitors ...
0
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1answer
93 views

STM32 memory page size

I can't find the size of a page of memory in an STM32L0 (specifically STM32L053R8, see DocID 025844). I don't see a referenced as to the size of a page of memory. Note: This is also in reference to ...
2
votes
1answer
86 views

read all of 256MB NOR flash, but only erase first 139MB from Linux - uboot is all good [closed]

Background: I recently upgraded my 64 MB NOR flash on my PowerPC (P2020) embedded board to a 256 MB NOR flash. (The board has 2 GB of DDR RAM.) I had to decrease the page offset to provide enough ...
2
votes
1answer
216 views

problem with making 1 bit RAM memory using transistors?

I'm trying to make 1 bit RAM using four transistor ( 2 NOR Gates ). I built the 2 copies of the following circuit: I connected a LED to the output "F". Also, I connected Another LED to the output ...
0
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0answers
66 views

Why is asynchronous NAND negatively affected by compressed data in SSD benchmarks

Over the last year, the Kingston V300 SSD received lots of flack for having good benchmark scores but poor real world performance. PC building enthusiasts point the gun to Kingston's benchmark tool ...
0
votes
0answers
50 views

What is DRAM atom size? Does it have any relation to the channel size?

I have seen that the channel size is in bits (64b/128b) which I understand is the amount of data one channel can transfer at an edge. But I see that the atom size is in Bytes. So does an atom of ...
0
votes
2answers
207 views

How to calculate address range of memory chips

Hi I am not an Electrical Engineer but need to know something about Memory address ranges. I need to calculate address range of each memory chip(62256) from let suppose bank 1 in below diagram. How ...
1
vote
1answer
70 views

AVR local and global variable program size

I work on ATmega8 and I need to optimize my code as well as I can, because I am over limit and I saw something surprising. I have a few 8bit integers declared as global variables and a few 8bit ...
8
votes
4answers
468 views

What happens when microcontrollers run out of RAM?

It may just be a coincidence but I've noticed the microcontrollers I've used rebooted when they ran out of RAM (Atmega 328 if hardware specific). Is that what microcontrollers do when they run out of ...
0
votes
0answers
35 views

USB 3 Flash Memory

What chip configurations are in these new USB 3 keysticks that are achieving >100mb/s write and >200mb/s read speeds?
0
votes
1answer
98 views

SPICE model of DRAM

Is there a SPICE model for DRAM developed? I am interested in any type of model at any level starting from DRAM memory cell and towards to whole memory VLSI circuit. I am seeking for a DRAM operation ...
0
votes
1answer
97 views

How does Xilinx MIG AXI interface map to DDR PHY pinout?

At the bottom of page 156 of UG586 I can understand how the User Address maps to the PHY pinout. However, I can't understand page 155 of the same manual. How does the 32-bit Microblaze address space ...
0
votes
1answer
269 views

Determining memory address width from memory size

Given a computer A with 1024 x 16 memory and a computer B with 16K x 32 memory, how big are the registers of an Accumulator, program counter, instruction, temporary register, address register, data ...
0
votes
2answers
162 views

In an SDRAM how do address rows/columns and rank width and bank width relate to the total memory size?

I have a Micron SDRAM (MT16KTF1G64HZ-8GB). The size of the memory is 8GB. I did some calucaltions and 8GB of data means 2^36 bits capacity. Now when I look in the Micron data sheet, the row address is ...
2
votes
0answers
149 views

How to quickly fill up the entire DDR memory using Xilinx tools?

I have a board with a DDR3 memory and a Virtex 7 FPGA. I have used Xilinx MIG to create a memory controller and I am able to succesfully read/write to the memory using Microblaze registers. I would ...