Consider instead more specific tags, e.g., dram, sram, flash

learn more… | top users | synonyms

0
votes
1answer
30 views

Meaning of control pins: CE, OE, WE

Just understanding some syntax. On my Ram (6116) and Rom (27C64) it has a asserted low CE and OE pins. These I believe are control pins. I'm assuming to use the RAM for example, chip enable (CE) has ...
0
votes
1answer
19 views

Quartus II Memory Read Clock Problem

I used LPM_RAM to store data and made read and write operations. But it seems like placing the data to wrong addresses. Here is screenshots; Wave Result; Memory Block;
3
votes
2answers
438 views

What do hardware address pins do?

I have been delving deep into digital logic and am trying to understand some memory architecture basics. I have started looking at data sheets to get a grasp on some real-world components and noticed ...
0
votes
0answers
37 views

When doing IDE DMA on x86, can other CPUs access the memory? [migrated]

I am unfamiliar with hardware. I am studying the IDE disk I/O and DMA on x86. I want to know that when doing a IDE disk I/O with DMA, can other CPUs access the memory (or exactly, the same memory ...
0
votes
0answers
39 views

Can I use full-size 64/72 bit DDR2/DDR3 memory module with CycloneV hardware controller of 24 + 24 bits?

I thinking of using Cyclone V FPGA and its hardware memory controller: There is "Cyclone V FPGA Multiport Memory Controller" document from Altera: ...
0
votes
0answers
24 views

Can't read the SPI buffer of a PIC32MX

I have some problems with my SPI communication. Indeed, I have configurated the PIC32 as master, and it communicates with a slave which is a memory. The communication works perfectly. LEGEND : In ...
1
vote
1answer
43 views

How data recovery works in flash memory?

Flash memory is Electronically Erasable Programmable Read Only Memory. In this data is stored by the On or Off state of the transistor. Then How it is possible to recover the data stored in the device ...
0
votes
2answers
56 views

What are the various interfaces used on memory devices

There are various external memory devices for temporary and permanent storage of data. This may have interface as simple as RD/WR signal with data-address bus and chip select with output enable. ...
4
votes
3answers
180 views

Why is L1 cache faster than L2 cache?

I'm trying to understand why certain CPU cache memories are faster than others. When comparing cache memory to something like main memory, there are differences in memory type (SRAM vs DRAM), and ...
1
vote
0answers
42 views

DDR3 interface to Lattice ECP3 FPGA - TDQ

I'm looking at implementing a Lattice ECP3 FPGA with an interface to DDR3. I'm looking at the schematic for the evaluation board: Lattice ECP3-Versa Eval Board User's Guide I am unfamiliar with DDR3 ...
4
votes
2answers
335 views

What do memory configurations like “256Kx18” mean?

This is a beginner question here. When choosing memory ICs, one of the options is the memory size/configurations. I understand the size part, but what does the "16Kx9" mean? It seems the same memory ...
0
votes
1answer
45 views

Do design of a VHDL module as APB Master has any practical difficulty?

I went across VHDL codes for memory architectures, which contains modules designed as AHB masters, AHB slaves, Bridge, and APB slaves. But no APB slaves. Is there is any specific reason for excluding ...
1
vote
2answers
82 views

What sort of a ferrite core will I need to make core memory?

I am building a homebrew computer using core memory. What sort of a ferrite core will I need?
0
votes
2answers
135 views

CPU Cache implementation in VHDL

I have been assigned a project of designing a cache memory with some advanced features (using efficient cache algorithms) and implementing it in VHDL. I know the required theory for carrying out this ...
1
vote
1answer
87 views

Reading RAM externally in a running system by intercepting the memory bus or replacing the RAM chips?

I wonder if it is possible to modify a consumer electronic system (TV, phone, embedded device, etc.) so that it is possible to read and possibly write the contents of its RAM chips while system is ...
1
vote
2answers
108 views

Organization of large memory using memory blocks

I found the following question in a test. I am not looking for an answer to the question per se, but I am having difficulty understanding the part in bold, as explained below. A main memory unit ...
0
votes
2answers
82 views

How to design a Design a 32 x 4 memory using two 16 x 4 RAM chips

I have this task to "Design a 32 x 4 memory using two 16 x 4 chips". But on Google I can't find what a 16 x 4 RAM is. I know the basics of latch, flip-flops, TTL, CMOS etc. But I can't put this ...
0
votes
1answer
136 views

Writing and Reading From FLASH ROM on Nexys 2 Spartan 3-E FPGA

I am a newbie to VHDL and FPGA platform. I have a Nexys-2 Spartan 3E FPGA board which is provided with a 16 MB Flash ROM.I want to preload first 10-20 memory locations of this ROM,each location with ...
3
votes
0answers
115 views

FPGA link to external memory

I am trying to use the cellular ram on the Nexys 4 FPGA development board. I am using Xilinx Vivado and would like a Microblaze soft core processor to be able to perform reads and writes. So far I ...
20
votes
1answer
2k views

Why does flash memory have a lifespan?

I've read that flash memories can "only" be reprogrammed 100000 to 1000000 times, until the memory storage "deteriorates" Why exactly does this happen with flash and not other memory types, and what ...
2
votes
0answers
88 views

How to implement memory mapped IO

I am describing a system in VHDL. This system already contains a processor, a DDR SDRAM controller and a VGA controller. VGA reads pixels from SDRAM (already validated and proven in FPGA). Although ...
4
votes
1answer
186 views

Why must flash memory be written/erased in pages/blocks ?

Title says it all. I'm trying to understand the workings of flash memory technologies, at the transistor level. After quite some research, I got good intuitions about floating-gate transistors, and ...
0
votes
1answer
78 views

A program to add 6 bytes of data and store sum and carry in 8085 instruction set

I have a question on 8085 instruction set. A program to add 6 bytes of data stored in memory starting from 4500h. must use b register to save any carries and finally store the sum and carry at two ...
1
vote
2answers
98 views

How to predict the memory size and gate count given source code

Excuse my poor English :-) I am in a software (for face detection) team and we co-work with the hardware team. If we give the source code to the hardware team, they will try to implement it with ...
1
vote
2answers
289 views

Professor said my embedded system design is incorrect, what did I get wrong?

The problem: Your embedded system has an 8-bit microprocessor, which has a 16-bit address bus. In addition, you have a 32-Kbyte FLASH chip, and a 8 KByte RAM chip. You want to locate the FLASH chip ...
0
votes
1answer
58 views

What is the Global Descriptor Table memory type?

What type of memory type is used for the Global Descriptor Table in an Intel Core 2 CPU? Is it just EEPROM or does the CPU normally use another type of NVRAM?
2
votes
2answers
104 views

How does the Array allocated in the stack?

I was testing the code below on my STM32 board, but I could't understand how the array was being allocated in the stack. I'm assuming that there are 200 bytes of memory in STM32. Here is the code: ...
1
vote
0answers
65 views

Averlogic fifo experience?

I've got an fpga board that utilizes an averlogic fifo -- AL460. This should be the easiest part in the world to use -- it's basically a huge dual ported fifo with two independent clocks. I was ...
0
votes
1answer
78 views

Microchip, memory measured in IEC?

It doesn't say on the data-sheet, but I'm curious where i can find if Microchip uses IEC or SI as standard for there memory sizes. For example: ...
4
votes
2answers
125 views

Compilers and MSB identification for Data types

I would like to know two things that is making my head quite confusing these days. If i allocate an int in C18 compiler I know ...
0
votes
0answers
23 views

Direct-Mapped Cache [duplicate]

I am a bit confused about the tables with direct mapped cache. I've attached picture of the problem, I know some stuff but, I don't know how to determine the size of the tag, offset and set. Can ...
1
vote
3answers
70 views

Frame memory (SRAM) size for an image

I am now reviewing a paper about hardware implementation and it says by cropping the 128*96-pixels from 160*120-pixels, the size of the frame memory (SRAM) can be reduced to 1/10. I don't get it. ...
2
votes
3answers
80 views

How to write to block memory?

I need to write 16x16 bit data to block memory. I am using RS232 to send data. To get 16 bit data, I send 2x8bit. Now, how can I write my data to the memory? I have a write signal and 16 bit input ...
-1
votes
2answers
114 views

Direct Mapped Cache [duplicate]

A computer using a direct-mapped cache has \$2^{24}\$ words of main memory and a cache of 256 blocks. Each cache block contains 64 words. How many blocks of main memory are there? What is the format ...
0
votes
0answers
69 views

Virtual Memory, Cache, and TLB's

I recently asked this question over at stackoverflow, but I was told by a user that it was off-topic, so I am posting it here since it's more of a hardware question. I'm trying to study for an exam ...
0
votes
2answers
153 views

Memory Addressing

How many bits would you need to address a 4M X 8 memory if the memory is byte-addressable? the memory is word-addressable with a word size of 16 bits? the memory is word-addressable with a word size ...
2
votes
1answer
307 views

Writing data on EEPROM or Flash memory of the PIC18F47J53

So I am using the 18F47J53 in Hitech PICC18-PRO compiler with MPLAB-X IDE, and for some reason there happens to be absolutely no support for the reading/writing function to either the flash or the ...
1
vote
1answer
50 views

Memory logic array blocks VS M20K

I am looking at the Stratix V overview Table 1. In it, they distinguish two types of memories: M20K memory blocks Memory logic array blocks What are the ...
0
votes
1answer
95 views

BRAM memory FPGA

Can someone explain how does a BlockRam in FPGA work. I was creating a memory for 128k and could not figure out how would I create a memory module for it.
3
votes
1answer
133 views

How to add memory to an ARM Cortex Microcontroller

I am looking into a design that would use the ARM Cortex M4F core but am just the software engineer for the project. The EE tells me that there will be an 64 MByte sdram memory module connected to the ...
0
votes
1answer
74 views

Building memory system adresses with decoders

Well I got the following (multiple choice) question. Even with the result given I have 0 idea how they could come to the conclusion.. With 64 memory elements of size 1Mx4 and several 2-input ...
0
votes
1answer
92 views

Address decoding from memory map

I am struggling to find the bits which dont matter when I have a memory mapped system with several devices connected. The memory map is given by I need to figure out which bits I should pass to ...
2
votes
1answer
163 views

What is DDR software leveling?

What is DDR software leveling ? How it is different from DDR2 and DDR3 ? Why it is required and important ? Is there a hardware leveling ? I have found some explanation here about DDR3 and a ...
0
votes
3answers
53 views

K9F1208R0C-JIBO data extraction

I have a old PDA board, it is not working, but I want to see the content of memory chip for this board, as far as I know there [might be] some interesting software on it, but the PCB is dead, so I ...
0
votes
0answers
92 views

Doubts in two level cache system

A computer system has an L1 cache, an L2 cache, and a main memory unity connected as shown below. The block size in L1 cache is 4 words. The block size in L2 cache is 16 words. The memory access times ...
-1
votes
2answers
142 views

Terms (bank,latency) in main memory?

A CPU has a cache with block size 64 bytes. The main memory has k banks, each bank being c bytes wide. Consecutive c - byte chunks are mapped on consecutive banks with wrap-around. All the k banks ...
2
votes
5answers
151 views

How does register type modifier work on different CPU architectures?

This question is to clarify my doubt against this register storage class. when a variable is register qualified ,compiler puts the variable in a cpu register other than RAM for ease of access. so ...
0
votes
0answers
35 views

Memory technology survey?

I did a comparison on what I could find about access times for different memory systems, could you please say if these numbers are approimately correct (I use an Altera DE2 FPGA)? SDRAM: Slower that ...
-2
votes
1answer
121 views

How to make MCU with 256kB memory?

(Reposting) I have 48MHz clocked ADC that outputs data continuously. My MCU will take the data at some interrupts and need to send it to iPhone. The amount of data collected are abt 178k Bytes. I ...
0
votes
1answer
477 views

What's the usage of the three boot mode of STM32f103?

If you see in refrence manual of STM32f103, you can see three boot mode for it. well, What's the usage of the three boot mode? please say to me by example for each mode.