Consider instead more specific tags, e.g., dram, sram, flash

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Process technology of Micron Parallel NOR Flash memory M29F200FT/B

I need to learn process technology of the part I stated in the title. Is it micron or nanometer? I am calling micron and the representative can't find anyone to answer my question. They forwarded me ...
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50 views

Hitachi HD44780 LCD works exactly 50% of the time

My Hitachi LCD works 50% of the time. Is it a problem is a deboucing reset button issue on the AVR? Why is this happening? Here's a video of what is happening. This does not happen if I write on the ...
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85 views

STM32 SPI Peripheral bug?

I'm using STM32F051R8T6 on STM32F0-Discovery board and M25P80 flash IC as a peripheral. I've got the SPI configured in 3-line (+ 1 software chip select line), full-duplex mode and I'm using polling to ...
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1answer
50 views

8051 micro controller on chip ROM address range? MEMORY SIZE

what is the size for each of these chip ? I know that when we add 1 bit to the memory we double the size. my question is what is the size for a chip range from (0FFF - 0000) so that i keep doubling ...
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2answers
46 views

What happens when VRAM fails?

When VRAM fails within a video device, there appear to be certain common patterns of visual artifacts. This got me thinking - when VRAM (and RAM in general) fails, what is it that's actually happening ...
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20 views

Interfacing 6116 RAM to a data bus

I have a question about interfacing IDT6116SA15TPG SRAM to a tri-state data bus controlled by 74LS244 tri-state buffer. I could not find an old memory like 74LS289 with separated inputs and outputs. ...
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2answers
42 views

EEPROM Write Cycle Time and Write Cycle Endurance

I have an embedded software application that is copying a buffer from RAM to EEPROM. In this case, the EPROM device is a 28C010 (128K x 8). The copying is done at non-regular intervals, generally in ...
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59 views

Why DIMM has 64 bit data width?

Wikipedia’s definition of DIMM says: Most DIMMs are built using "×4" ("by four") or "×8" ("by eight") memory chips with nine chips per side; "×4" and "×8" refer to the data width of the DRAM chips in ...
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64 views

Fundamental reason why RAM is faster then second storage device

Let's consider dynamic RAM - 1 cell = capacitor+ transistor and second storage device, - for example ordinary mmc NAND flash. DRAM, so called volatile memory, need to be refreshed to keep capacitors ...
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50 views

STM32 memory page size

I can't find the size of a page of memory in an STM32L0 (specifically STM32L053R8, see DocID 025844). I don't see a referenced as to the size of a page of memory. Note: This is also in reference to ...
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43 views

read all of 256MB NOR flash, but only erase first 139MB from Linux - uboot is all good [closed]

Background: I recently upgraded my 64 MB NOR flash on my PowerPC (P2020) embedded board to a 256 MB NOR flash. (The board has 2 GB of DDR RAM.) I had to decrease the page offset to provide enough ...
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125 views

problem with making 1 bit RAM memory using transistors?

I'm trying to make 1 bit RAM using four transistor ( 2 NOR Gates ). I built the 2 copies of the following circuit: I connected a LED to the output "F". Also, I connected Another LED to the output ...
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49 views

Why is asynchronous NAND negatively affected by compressed data in SSD benchmarks

Over the last year, the Kingston V300 SSD received lots of flack for having good benchmark scores but poor real world performance. PC building enthusiasts point the gun to Kingston's benchmark tool ...
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43 views

What is DRAM atom size? Does it have any relation to the channel size?

I have seen that the channel size is in bits (64b/128b) which I understand is the amount of data one channel can transfer at an edge. But I see that the atom size is in Bytes. So does an atom of ...
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2answers
86 views

How to calculate address range of memory chips

Hi I am not an Electrical Engineer but need to know something about Memory address ranges. I need to calculate address range of each memory chip(62256) from let suppose bank 1 in below diagram. How ...
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1answer
43 views

AVR local and global variable program size

I work on ATmega8 and I need to optimize my code as well as I can, because I am over limit and I saw something surprising. I have a few 8bit integers declared as global variables and a few 8bit ...
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411 views

What happens when microcontrollers run out of RAM?

It may just be a coincidence but I've noticed the microcontrollers I've used rebooted when they ran out of RAM (Atmega 328 if hardware specific). Is that what microcontrollers do when they run out of ...
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34 views

USB 3 Flash Memory

What chip configurations are in these new USB 3 keysticks that are achieving >100mb/s write and >200mb/s read speeds?
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65 views

SPICE model of DRAM

Is there a SPICE model for DRAM developed? I am interested in any type of model at any level starting from DRAM memory cell and towards to whole memory VLSI circuit. I am seeking for a DRAM operation ...
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49 views

How does Xilinx MIG AXI interface map to DDR PHY pinout?

At the bottom of page 156 of UG586 I can understand how the User Address maps to the PHY pinout. However, I can't understand page 155 of the same manual. How does the 32-bit Microblaze address space ...
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117 views

Determining memory address width from memory size

Given a computer A with 1024 x 16 memory and a computer B with 16K x 32 memory, how big are the registers of an Accumulator, program counter, instruction, temporary register, address register, data ...
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57 views

In an SDRAM how do address rows/columns and rank width and bank width relate to the total memory size?

I have a Micron SDRAM (MT16KTF1G64HZ-8GB). The size of the memory is 8GB. I did some calucaltions and 8GB of data means 2^36 bits capacity. Now when I look in the Micron data sheet, the row address is ...
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How to quickly fill up the entire DDR memory using Xilinx tools?

I have a board with a DDR3 memory and a Virtex 7 FPGA. I have used Xilinx MIG to create a memory controller and I am able to succesfully read/write to the memory using Microblaze registers. I would ...
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47 views

Calculate Instructions per second MIPS

I'm trying to solve this problem for a MIPS processor: Suppose the data cache is perfect but the instruction cache has a 5% miss rate. On a cache miss, the processor stalls for 20 ns to access main ...
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1answer
56 views

How many NAND flash chips (measured in Gb) are required for a 32GB USB drive? What is the economic relationship between the two?

NAND Flash Contract Price http://www.insye.com/dp/NANDFlashContractPrice.aspx Context, I am purchasing about 200k USB drives. I sent it out to competitive bid but I want greater insight into the BOM ...
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44 views

AT91SAM9260 Does not recognize 128 MBytes SDRAM

Recently began to use AT91SAM9260 processor on the Olimex board. From the data sheets of the processor, it seems to support up to 256 MBytes of SDRAM. So I replaced both of the old K4S561632C-TC/L75 ...
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43 views

Verilog module to read/write a register

I would like to create a module that can change the value of a register passed to it (+/- 1) using an inout port. I wrote this: ...
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4answers
1k views

How do you determine how much flash/RAM you need for a microcontroller?

Let's say you are starting an embedded project with some known functionality. When you select a microcontroller how do you select how much RAM you need? Do you use a developer board and code your ...
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122 views

Implementing Processor Core for Cache Module in Verilog

I have written a simulation module for a Direct Mapped Cache (consisting of data, tag, and valid rams and cache controller) in Verilog. I now want to implement a Processor Core/Driver (also in ...
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1answer
54 views

Small system on a chip : Power consumption [closed]

This question is lying somewhere between electrical engineering and computer science, however I felt that this forum suited my question the best. I post this question because I feel that this kind of ...
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2answers
442 views

Constructing decoder 5/32 using smaller ones, without enable

I need to construct a decoder 5/32 using any number of 2/4 and 3/8. How do I start? With Enable it's not hard to figure out, but without them it gets complicated. Advice?
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56 views

Estimating processing power required

I am currently in a computer engineering class and I have been asked to design a product that can guide blind people. In my fictitious product I am going to implement a module to detect distances (a ...
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62 views

Series Termination DDR

I was Going through some application notes for the placement of Series termination of DDR and found it should be placed near to the processor. But if I am not wrong termination resistor are placed to ...
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1answer
179 views

STM32F429 / STM32F439 read-while-write from two memory banks. Prevents stalling CPU?

I have been reading up on the STM32F429 flash memory (2MB version). From the STM32F4 reference manual I found out that it has two memory banks and supports read-while-write (RWW), which means it can ...
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1answer
64 views

Flash memory range on STM32F429II

I am reading the STM32F429II data sheet and looking at page 84, which shows the memory mapping. The chip has 2MB of internal flash memory, but the data sheet is general for all STM32F427xx/STM32F429xx ...
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155 views

What's the difference between a SRAM cell and a D-Latch?

They both seem identical - they both have an "enable" and a single input. When enable is high, the value stored in the element is set to the input. Are they functionally different in any way? (I know ...
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550 views

STM32F4 NAND flash via FSMC, difference between bytes written and read back

I have a Waveshare Open407V-D development board, basically a "motherboard" in which an STM32F4DISCOVERY kit is fitted (this kit, for those not familiar with it, is made by ST itself and based on the ...
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92 views

RAM memory modelling in Verilog

I am trying to model a 0.125GB RAM memory in Verilog using ModelSim of width 512 bit using memory chips of width 32 bit. So I have created a 32 * \$\2^{18}\$ memory array whose code is as follows: ...
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165 views

Exploring MCDRAM

I was going through the below link and found one peripheral named MCDRAM. If i am not wrong it looks like a Multichannel memory device which is integrated on same package. Can someone explain what ...
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39 views

Flash Memory Failure Modes - Block Failure

My understanding is that typical flash memory failures, such as those due to erase cycles, occur at the bit level. I have a flash in which entire blocks (actually two blocks) are failing. Is there a ...
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686 views

memory segmentation in 8086

If the external memory (1 MB) in 8086 based system is segmented into code, data, stack and extra which are all 64 kB, what do we do with the rest of the memory? Does it go waste?
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132 views

Calculate Paging System

I have this problem to solve and I have the answers, but I'm trying to understand the concepts behind it. A paging system has the following parameters: 2^32 bytes of physical memory; page size of ...
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50 views

Virtually indexed physically tagged cache

I'm trying to understand the concept and calculations for solving this problem. I know the answer is 10 bits. ...
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1answer
53 views

Determining physical address for logical address

I have a simple segmentation system with the following segment table: ...
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68 views

IC for 4 Kbytes of RAM [closed]

Is there a Memory IC for 4Kbytes of RAM? I'm trying to make a schematic capture in Proteus and I need a Memory IC for 4Kbytes of RAM, I've searched throughout the library and I can't find one, tried ...
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173 views

Why All DDR's (DDR, DDR2, DDR3) internal clock sets to 200MHz

If we see the DDR Upgrade technology explain below the internal clock of all DDR is set to 200 MHz. DDR For example,DDR-400 Efficient frequency data bus is 400 MHz True clock rate (IO buffer ...
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67 views

Role of the MMU in a Page Fault Swap

When a virtual memory address outside the range of loaded into physical RAM is referenced and a page fault occurs, does the Memory Management Unit rely on DMA (Direct Memory Access) to swap the ...
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110 views

How much power does a GPU actually use when only doing PCIe I/O, or only compute?

I hope this is the right sight to ask such a question, if not please be kind and direct me elsewhere. I have some discrete GPU with a TDP figure of X watts. Now, sometimes the GPU does Only ...
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3answers
111 views

How big is a single RAM cell?

I am studying on my own how the PC works and I can't understand one thing. A 32 or 64 bit processor differs for its ability to allocate 2 ^ 32 or 2 ^ 64 addresses for the cells of the RAM. What I do ...
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119 views

Role of the Memory Management Unit

I know that the first instruction stored in BIOS is "mapped" to memory address 0, and that a signal on the reset pin to the microprocessor causes this instruction to be fetched, beginning the POST and ...