Tagged Questions
3
votes
1answer
52 views
How to best understand cache associativity?
AFAIK this definition is the most clear and physical:
Associativity number = Number of comparators.
Is it correct? Could you make a more precise / better definition?
The wikipedia illustration is ...
2
votes
1answer
177 views
How to calculate index and tag fields lengths for a cpu cache?
I study computer engeering notes for a cache memory and I try to understand what determines the length of the index and the tag fields. The first examples is for 64 bits and the second example is for ...
0
votes
2answers
110 views
What determines the number of bits for the address field in a cache memory?
I understand a cache memory is constructed for a basic block like this
Valid bit | Address bits | Data/Instruction
But what determines the length of the address bits? I understand that for a 32-bit ...
1
vote
3answers
148 views
Physical address vs virtual address
Physical address is hardware address of physical memory and virtual address is the one the processor will be seeing, it has it has a tag and offset. I understand this. Can any one describe it with an ...
1
vote
3answers
112 views
Cache write/read times?
I would like to devise certain rules of thumb to help solve certain computer design/architecture challenges. Hence, in memory, which operations typically take longer to execute: loads or stores?? I ...
5
votes
5answers
195 views
stack cache instead of registers
Is there a processor that do arithmetic operations on a stack and not on registers? To keep performance, of course, that processor should cache top block of a stack in the same type of memory that is ...
7
votes
2answers
370 views
Are page table walks cached?
On a microprocessor with hardware TLB management (say an Intel x86-64) if a TLB miss occurs and the processor is walking the page table, are these (off-chip) memory accesses going through the cache ...
2
votes
3answers
673 views
I know why DRAM is slower to write than to read, but why is the L1 & L2 cache RAM slower to write?
DRAM is slower to write than read because it takes time to either charge or discharge a DRAM memory cell. But what about the SRAM in my processor's L1 and L2 caches? It's slower to write as well but ...
