Tagged Questions
1
vote
1answer
69 views
Interfacing SJA1000 to Spartan6 FPGA
As the title says, I would like to interface an SJA1000 CAN controller to a Xilinx Spartan6 FPGA.
The SJA1000 has a shared 8-bit address&data bus with an address latch signal and either separate ...
0
votes
2answers
154 views
ARM (Cortex-A8) High Speed Bus?
I need to communicate from FPGA to ARM with about 16GBits/s...
Is there a Bus which I can use? Or how to solve this problem?
The FPGA receives data over LVDS. This data schould be post-processed in ...
2
votes
1answer
205 views
How to access RAM for use with an FPGA for high performance computing
I am exploring the idea of using an FPGA for linear algebra. I would like the ability to work on large matrices (> 4 GB). But modern high-end FPGAs have RAM on the order of megabytes.
Please describe ...
2
votes
1answer
368 views
Speed difference between SRAM (Static RAM) and DDR3 RAM
This is more of a computing question, but only electronics geeks would know such things. Today's computers use multiple layers of memory in order to work with data quickly. Currently CPU speeds are ...
5
votes
3answers
266 views
Interfacing static ram to fpga
I while ago I asked this question about interfacing static ram to an fpga for the purposes of a vga frame buffer I wanted to make as a little hobby project. It became clear to me at the time that the ...
1
vote
3answers
121 views
What are the “embedded” and “non-embedded” design flows?
I'm reading the Spartan 6 user guide on the Memory Controller Block (MCB). The following quote discusses two design flows:
There are two supported design flows for the MCB:
1) Non-embedded ...
0
votes
2answers
73 views
What is an “IP implementation”?
I'm reading the Spartan 6 user guides, specifically the Memory Controller Block guide. I quote the introduction:
The Memory Controller Block (MCB) is a dedicated embedded block
multi-port memory ...
0
votes
1answer
53 views
Attaching two identical PSRAMs to the same set of signals
I have an ARM microprocessor connected to an FPGA through one 47 pin memory bus. Also, two identical PSRAMs (datasheet available here) are connected to the FPGA through 65 pins (47 for first PSRAM + ...
1
vote
2answers
766 views
Transferring a 1MB bitstream to a FPGA and reading it out
I am using Spartan 3E Starter Kit and I need to store a sequence of bits around 1MB long. It is a constant bitstream and will be known to me at the time of programming the board. I need to be able to ...
1
vote
0answers
229 views
Interfacing memory to papilio fpga board
A while ago I asked this question about using a ram chip for generating VGA signal from an fpga. After reading the replies I realized there were considerable practical difficulties with doing that, ...
2
votes
3answers
252 views
What is wrong with this attempt at an SDR RAM in Verilog?
I have a Spartan-6 FPGA wired to the AEMIF memory interface on a TI DaVinci DM365 SoC that I control. The AEMIF is set up in Select Strobe mode. I'm trying to implement memory read/write on the FPGA ...
1
vote
3answers
533 views
RAM device / timings for small VGA project
For a personal hobby project I'm looking to make a small vga display using an fpga. I was thinking of making the display 640x480 pixels with one byte colour per pixel at 60hz (I believe those timings ...
