Tagged Questions

-4
votes
0answers
29 views

Can someone give me a DDR3 RAM for Dummy(ies) FPGA designers type of resource? [closed]

I want to understand how DDR3 RAM is used with a FPGA. Basically I want to know what ALL the signals on the interface do and what is required to read/write the data.
2
votes
1answer
209 views

How to access RAM for use with an FPGA for high performance computing

I am exploring the idea of using an FPGA for linear algebra. I would like the ability to work on large matrices (> 4 GB). But modern high-end FPGAs have RAM on the order of megabytes. Please describe ...
3
votes
5answers
181 views

Text editing memory management

I'm building a PIC-based text editing 'laptop'. I have an SD card connected to the PIC and am using a keyboard and an LCD screen. My problem is that I want to edit real big files like for example ...
2
votes
1answer
390 views

Speed difference between SRAM (Static RAM) and DDR3 RAM

This is more of a computing question, but only electronics geeks would know such things. Today's computers use multiple layers of memory in order to work with data quickly. Currently CPU speeds are ...
3
votes
3answers
178 views

How big variables are stored in RAM memory?

I've just made a simple RAM memory in Minecraft (with redstone), with 4 bits for the address and 4 bits stored in each cell. Our next goal is to store different kinds of variables in it and to process ...
4
votes
4answers
265 views

SDRAM advantages

As of RAM technologies (the basic ones) is concerned, I consider the initial classification (based on the storage) as SRAM: The basic entity for storage (each cell) is the flip-flop (comprised of ...
-1
votes
1answer
80 views

DRAM - is my frequency correct? [closed]

I have 4 Trident X (2400) DDR3 ram installed on my Maximum 5 Extreme motherboard. In the bios, I set the speed to 2400mhz. My motherboard will usually report on start-up if it is unable to accommodate ...
-2
votes
1answer
328 views

About ROM designing

My questions are: How is ROM Memory designed (with hardware design)? How RAM Memory is designed and How they divided the RAM Memory?
6
votes
1answer
279 views

Freezing DRAM for forensics (coldboot)

I've known about the coldboot trick for a while, but have never really considered the physics behind it. I've read the paper, but it doesn't really cover why it works. How does physically cooling a ...
2
votes
1answer
822 views

Controlling 23K256 SPI RAM with Arduino

I'm trying to interface with a 23K256 SPI RAM IC using an Arduino Mega 2560. I can't use the standard SPI pins, since I'm using an ethernet shield and it doesn't play nicely when SS is set high. So, ...
1
vote
0answers
85 views

Documents about Pseudo SRAM

I'm doing a small research about PSRAM. However, I found it difficult to get information about it. Does anyone have any document about PSRAM (the struture, the operation, ...)? I'll be very greateful ...
2
votes
2answers
717 views

Difference between RAM and internal storage chips in HTC Sensation

Just having a small discussion at work about my HTC Sensation phone. My question is: is there a difference (in chips) that are used for internal storage and RAM memory? Must they be using other ...
2
votes
3answers
252 views

What is wrong with this attempt at an SDR RAM in Verilog?

I have a Spartan-6 FPGA wired to the AEMIF memory interface on a TI DaVinci DM365 SoC that I control. The AEMIF is set up in Select Strobe mode. I'm trying to implement memory read/write on the FPGA ...
5
votes
3answers
338 views

Can you run an x86 class processor ramless?

Modern x86 processors have at least 512K of L2 cache. There are applications which would fit entirely into this amount of memory. Can you run these chips with no RAM attached? If so, is there a way to ...