Consider instead more specific tags, e.g., dram, sram, flash
-4
votes
0answers
29 views
Can someone give me a DDR3 RAM for Dummy(ies) FPGA designers type of resource? [closed]
I want to understand how DDR3 RAM is used with a FPGA. Basically I want to know what ALL the signals on the interface do and what is required to read/write the data.
39
votes
9answers
3k views
How can anyone use a microcontroller which has only 384 bytes of program memory?
For instance a PIC10F200T
Virtually any code you write will be larger than that, unless it is a single purpose chip. Is there any way to load more program memory from external storage or something? ...
0
votes
0answers
24 views
Problem running C++ function from STM32's SRAM in Keil microVision
I'm using Keil uVision 4.6 to write a C++ program for SMT32F103RE.
I need to run one of my program functions directly from SRAM, so I devided my SRAM into two separate regions:
...
1
vote
1answer
40 views
PIC16: Out of Data Space - Make use all available banks
I'm using a Microchip PIC16F1825 with the XC8 (v1.12) compiler and defining some arrays (size between 16 and 64 bytes). I was able to declare them (linker output below). However, as soon as I try to ...
0
votes
1answer
38 views
What are different media for uC (microcontroller) to store data that shall be input to a PC later [closed]
Well we can have a uC Embedded device that will use a chip to store data somewhere on the PCB. Than it can have firmware that will enable one to gain access to this data by means of a USB connection ...
7
votes
2answers
373 views
Are page table walks cached?
On a microprocessor with hardware TLB management (say an Intel x86-64) if a TLB miss occurs and the processor is walking the page table, are these (off-chip) memory accesses going through the cache ...
1
vote
1answer
70 views
Interfacing SJA1000 to Spartan6 FPGA
As the title says, I would like to interface an SJA1000 CAN controller to a Xilinx Spartan6 FPGA.
The SJA1000 has a shared 8-bit address&data bus with an address latch signal and either separate ...
5
votes
3answers
27 views
What are the implications of using PROGMEM?
With large amounts of text variables, I've found it necessary to store them in the Flash memory using PROGMEM. What are the positive and negative consequences of storing large variables in Flash ...
1
vote
3answers
81 views
Are most RAM/Memory cells done with Inverters?
As far as memory cells go (SRAM/ROM/Registers) in simple chips everything i've looked at seems to use the Two-Inverter CMOS schematic (Just from readings/googling and such).
In I guess "real life" ...
3
votes
1answer
52 views
How to best understand cache associativity?
AFAIK this definition is the most clear and physical:
Associativity number = Number of comparators.
Is it correct? Could you make a more precise / better definition?
The wikipedia illustration is ...
0
votes
2answers
88 views
8085 Memory address decoding with a NAND Gate
I have a problem for homework that has me stumped. Basically, what I'm given is 2 R/WMs, each 2048 bytes * 4. Connected to each of their CS pin is a NAND gate with pins A12-A15 connected from the 8085 ...
0
votes
0answers
52 views
Writting in a USB memory
I have a AT91SAM7X-EK card from atmel, and I'm trying to write a string into it's memory then I want to read it back.
I order to do that I parsed the available devices using
...
5
votes
9answers
403 views
Microprocessors/Microcontrollers - Do registers have addresses?
My Embedded Systems professor keeps referring to the memory locations of registers as their respective "addresses". I'm confused by this; I was always under the impression that in any microprocessor, ...
3
votes
3answers
184 views
Sequential Logic - Primarily For Signal Storage?
New here :D
I've been reading David M. & Sarah Harris's book "Digital Design and Computer Architecture" and came to wonder about the role of sequential logic. To me, it seems that the ...
0
votes
1answer
119 views
GDDR5 overclocking [closed]
Why does a GDDR5 memory which is designed to work at 1250MHz gets slow at 1450MHz? Because of ECC check start? Because it is not supposed to work at that frequency(hard-coded?)? Because of some ...
1
vote
1answer
86 views
How to erase stored data in MRAM memory devices
When searching in Google about MRAM I was only able to find the reading and writing process for MRAM. How does erasing happen in MRAM? Also why there is no need of error correction and checking ...
0
votes
3answers
202 views
Interfacing with RAM from a PC, e.g. SDRAM / DDR, to a microcontroller
I'm looking into interfacing standard PC form-factor SDRAM or DDR sticks to a microcontroller, but I can't find any definitive details on how they work in terms of how the bus works. I guess it's ...
4
votes
2answers
126 views
How NAND Flash controllers erase single pages efficiently?
I'm working on some code to manage a NAND flash and I need to erase single pages, given that the smallest erasable unit is a block, the only solution I could think of is to:
Erase a reserved block
...
1
vote
0answers
51 views
Interfacing NAND flash with USBMSD
I'm trying to read files from a NAND flash (K9LAG08U0M) that I took off an old MP3 player, so far I've been able to read the NAND contents successfully by interfacing it to my PC as a USBMSD (Mass ...
0
votes
2answers
154 views
ARM (Cortex-A8) High Speed Bus?
I need to communicate from FPGA to ARM with about 16GBits/s...
Is there a Bus which I can use? Or how to solve this problem?
The FPGA receives data over LVDS. This data schould be post-processed in ...
2
votes
1answer
209 views
How to access RAM for use with an FPGA for high performance computing
I am exploring the idea of using an FPGA for linear algebra. I would like the ability to work on large matrices (> 4 GB). But modern high-end FPGAs have RAM on the order of megabytes.
Please describe ...
0
votes
1answer
127 views
Ardupilot, atmega1280 and barometer
I'm working on a project and I need to know where the information taken by the barometer sensor are stored.
I think in the eeprom, but exactly where? Is there a specific address or register memory?
...
1
vote
1answer
154 views
Memory IC width vs depth
Given a need for a single 2G × 32 bit DDR3 memory block, which configuration would be ideal and why?
A: Two 2G × 16 bit memory ICs
or
B: Two 1G × 32 bit memory ICs
I think that A ...
-1
votes
3answers
181 views
Serial NOR Flash - Vague
What are the structural differences between Serial NOR Flash and Parallel NOR Flash? If there is a structural difference , then What are the differences between Serial NOR Flash and Serial NAND Flash?
...
0
votes
1answer
167 views
What is backdoor memory access?
There is a term in HDL simulation/verification called
"backdoor memory access".
I've heard this a lot of times though I'm
not sure how is this implemented.
Also, there are a few references for this ...
3
votes
5answers
181 views
Text editing memory management
I'm building a PIC-based text editing 'laptop'. I have an SD card connected to the PIC and am using a keyboard and an LCD screen.
My problem is that I want to edit real big files like for example ...
1
vote
1answer
99 views
SDRAM on opposite side of board with respect to uC
Just a quick question. Is it advised against to place a high speed memory device on the opposite side of the PCB with respect to the microcontroller? And if it is ill advised, how is it possible to ...
2
votes
1answer
145 views
Cannot understand how does Arduino memory work for program code
I am using Arduino Lilypad and Uno. At first, I've developed my code and ran it on the UNO because its easier to use, but after that I've uploaded it to the Lilypad and it worked too. The intersting ...
3
votes
1answer
106 views
Memory interface for video output
I am designing a system where a DSP (like the TMS320VC5501) processes some video data and outputs it to a PSP screen (the ones sold on sparkfun). The issue I'm having here is designing the video ...
2
votes
1answer
182 views
How to calculate index and tag fields lengths for a cpu cache?
I study computer engeering notes for a cache memory and I try to understand what determines the length of the index and the tag fields. The first examples is for 64 bits and the second example is for ...
7
votes
2answers
163 views
Need some help understanding PIC memory map
Some background. I use MPLABx with a PicKit2 to program different types of pics. At the moment its the 16F887. I try to stick to the Hi-Tech PICC Lite tool chain but I'm growing increasingly unhappy ...
0
votes
2answers
112 views
What determines the number of bits for the address field in a cache memory?
I understand a cache memory is constructed for a basic block like this
Valid bit | Address bits | Data/Instruction
But what determines the length of the address bits? I understand that for a 32-bit ...
3
votes
1answer
101 views
Advantage of SanDisk iNAND?
I'm looking for a low-power microSD card for a datalogger, when I came across SanDisk's iNAND technology. What are some real-world advantages of those vs. microSD cards, except for their smaller ...
2
votes
1answer
71 views
Buffering Micro-SD data for power saving useful?
I have a datalogger which has only 4KB of SRAM, and because of that it needs to flush its buffer to MicroSD every second. Would adding external SRAM to create a larger buffer safe any significant ...
3
votes
1answer
638 views
Verilog memory designs with multiple read/write ports - poor circuit performance when synthesized?
I am interested in designing (with verilog) some memory structures that have multiple (let's say 3) read/write ports. I've been doing some studying on architecture and what I've heard is that these ...
2
votes
1answer
389 views
Speed difference between SRAM (Static RAM) and DDR3 RAM
This is more of a computing question, but only electronics geeks would know such things. Today's computers use multiple layers of memory in order to work with data quickly. Currently CPU speeds are ...
-2
votes
2answers
217 views
1
vote
3answers
148 views
Physical address vs virtual address
Physical address is hardware address of physical memory and virtual address is the one the processor will be seeing, it has it has a tag and offset. I understand this. Can any one describe it with an ...
4
votes
1answer
217 views
Will DDR2 memory work with DM pins tied to LOW, if no data masking is required?
I have a board with the LDM and UDM pins swapped. If they are tied to low, will the memory still 'work', given that data is always written to mod 4 addresses and always using all 4 bytes?
Memory is ...
0
votes
0answers
53 views
reading P2 card with standard PC Card (PCMCIA) reader [closed]
I have a Panasonic professional video camera which uses P2 cards.
Looking for a way to connect them to the computer without using the camera, I found that the only P2 reader in the market is the one ...
1
vote
3answers
112 views
Cache write/read times?
I would like to devise certain rules of thumb to help solve certain computer design/architecture challenges. Hence, in memory, which operations typically take longer to execute: loads or stores?? I ...
3
votes
1answer
193 views
How does memory wear out?
I know that after time due to writing/re-writing memory wears out, and I was reading about a microcontroller from TI which uses "wear leveling" to insure the longest life of some EEPROM that the chip ...
5
votes
3answers
172 views
Storing an LED's previous state even when power is removed
Storing an LED's previous state even if power is removed
I want to build a simple circuit that consists of 2 push buttons and an LED. I want the LED to turn on when one pushbutton is pressed and off ...
3
votes
3answers
178 views
How big variables are stored in RAM memory?
I've just made a simple RAM memory in Minecraft (with redstone), with 4 bits for the address and 4 bits stored in each cell. Our next goal is to store different kinds of variables in it and to process ...
5
votes
5answers
196 views
stack cache instead of registers
Is there a processor that do arithmetic operations on a stack and not on registers? To keep performance, of course, that processor should cache top block of a stack in the same type of memory that is ...
6
votes
1answer
2k views
MSP430 Code Size in CCS
This should be pretty straight forward, but my google-ing is not turning anything up... I can build my project successfully in TI Code Composer Studio (CCSv5) and target my device.
Now I want to ...
0
votes
0answers
40 views
Exemples how to connect camera module with micro-controller (Record videos) [duplicate]
Possible Duplicate:
develop webcamera with battery and memory to SELF RECORDING (Disc Processing System)
i have searched everywhere on the net on how to connect the camera module with micro ...
1
vote
1answer
366 views
pic memory management examples in C
Can anybody recommend a good resource/website for EXAMPLES of pic memory usage in C? I'm having difficulty following all the TBLPTR/TBLRD stuff without seeing it used in lots of different, simple ...
4
votes
4answers
265 views
SDRAM advantages
As of RAM technologies (the basic ones) is concerned, I consider the initial classification (based on the storage) as
SRAM: The basic entity for storage (each cell) is the flip-flop (comprised of ...
4
votes
3answers
448 views
How does random memory access of RAM work?
HDD works in a partly sequential manner. However, RAM is known for random memory access, allowing equal speed of memory access for every location at every time.
So, what makes RAM so special? How ...
