MIPS is a reduced instruction set computer (RISC) architecture that has both 32 and 64-bit variants. The technology is often licensed as IP cores to manufacturers. The Microchip PIC32 series is an example of a common microcontroller based on the MIPS M4K core and several FPGAs include a MIPS ...

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Problems while trying to flash a memory using openocd and jtag

I'm using openocd and jtag for the very first time in my life (after 30 years of playing with electronics), when I dump the flash using dump_image, I got a 4 byte sequence (0x80 0x01 0x59 0x18) in ...
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Given an instruction sequence for MIPS, show cycle by cycle execution of instructions

I am continuing my practice on instruction sequences for the MIPS processor w/ standard 5 stage pipeline. Here is the problem I am working on: ...
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Writing MIPS assembly and machine code for instructions

I am continuing my practice with MIPS assembly and machine code. I am doing a problem that assumes the following: ...
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MIPS assembly instruction to machine code in hex

I am doing some practice problems involving MIPS assembly instructions and machine code(in hex). I am doing a problem but am uncertain if it is correct. This is the problem, and what I did: ...
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Assembly language that corresponds to machine instruction in MIPS

I am working on a problem that asks for the assembly language that would correspond to the following machine instruction in MIPS: OX3062FF80 Here is what I've ...
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How many clock cycles does a RISC/CISC instruction take to execute?

According to Digital Design and Computer Architecture by Harris and Harris, there are several ways to implement a MIPS processor, including the following: The single-cycle microarchitecture ...
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Why are words in reverse order when reading from a flash?

I dumped the contents of a NAND flash chip, and do not understand why would each of the words in the image be in the reverse order. This CFI-compatible flash is connected to a TI AR7 SoC that ...
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Range of MIPS j instruction

I understand that for MIPS-32, the first 4 bits of the address to jump to are taken from the first 4 bits of the address of j instruction, which means that we have a boundary of 2^28 bits around the ...
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98 views

How the lw (load word) instruction works on the MIPS Unicycle (Implementation)

I'm reading the Computer Organization and Design book from David A. Patterson and John L. Hennessy. Specifically, I have a question about the implementation of a MIPS Unicycle. So, in the book, they ...
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94 views

Finding Instruction Count

Computer A has an overall CPI of 1.3 and can be run at a clock rate of 600MHz. Computer B has a CPI of 2.5 and can be run at a clock rate of 750 Mhz. We have a particular program we wish to run. When ...
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implementing direct addressing mode for a load instruction on a mips archtitecture

Given a Mips machine with 26 bit addresses and 32 bits data-paths, where the load instruction is as follows |OPT code|rs|rd|immediate| |6 bits |5 bits|5 bits|16 bits| The OPT code is the ...
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Calculate Instructions per second MIPS

I'm trying to solve this problem for a MIPS processor: Suppose the data cache is perfect but the instruction cache has a 5% miss rate. On a cache miss, the processor stalls for 20 ns to access main ...
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240 views

Use of $at register in MIPS?

Register r1 or $at, is it's sole use in pseudoinstructions? If so, is this the sole solution to enable pseudoinstructions within the architecture?
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MIPS c.gt.s command throwing syntax errors

So basically, i am trying to do a comparison of an input between 2 values. I am asking it to return to the loop if the value is less than 45 or greater than 90. Here is the code: ...
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559 views

Difference in the datapath of Load Upper Immediate to Load Word in a 32 bit MIPS processor

For the MIPS insturction Load Word I have got the following Datapath: How does the datapath for the Instruction ...
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Difference between LW and SW in MIPS assembly

One of my homework questions was to find the 3rd element stored in an array in MIPS, here is my code ...
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Can `ADD` create a control hazard while in the `MEM` stage?

Imagine there is a machine that has shared memory for both data and instructions (which means a control hazard can occur between the MEM and ...
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112 views

Pipelining and Branches (MIPS)

I'm having some trouble determining how to figure out which cycle these instructions are in for the following question: For each instruction show which stage of the traditional MIPS five-stage ...
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How are the control signals determined for a jump instruction in the MIPS pipeline?

NOTE: Let me point out that I did try extensively to solve this on my own. The problem is that, based on that circuit, it would appear that this processor cannot jump. At best the jump instruction ...
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ARM9 vs ARM11 performance? [closed]

This may be a loaded question, but is there a general understanding of the performance increase per clock between ARM9 and ARM11? Say, for a math-heavy function (FFT)? Thanks!
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Atomic operations using extended inline assembler of C32

I'm trying to write atomic code, in my example below I need to perform simple operation a ^= 1; ...
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118 views

In disassembly, I see instruction LI, but I can't find such instruction in MIPS instruction set

I have little test project for PIC32MX CPU, here's a part of disassembly: (I know this code is not atomic, I'm just testing things. Actually, I'm pretty newbie in MIPS) ...
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1answer
372 views

PIC32: “16-bit code” doesn't work (many errors “unknown opcode”)

I have very little test project for PIC32MX440F512H, which builds (with XC32 v1.21) and works correctly. Then I tried to generate 16-bit code, set checkbox "Generate 16-bit code", additional option ...
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Classic RISC pipeline question

Consider the following instruction sequence: Add R3, R4, R5 (R4+R5->R3) Or R2, R4, R5 (R4 OR R5->R2) Add R1, R2, R3 (R2+R3->R1) Assuming no data ...
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How to know which element replaces which for a cache?

If I assume that the first element of the matrix that is fetched to the D-cache is a[0][0], for associativity 4, please tell me which element in which matrix that ...
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133 views

Understanding branch prediction

On page 376 of Hennesay's book Computer Organization And Design, the following illustration is listed to illustrate branch prediction. But what do "IM" and "DM" mean? Does IM stand for instruction ...
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How does the Store Word(SW) and Load Word(LW) instructions work, MIPS

The SW and LW instructions are defined as: ...
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163 views

Writing a method using MIPS code

I am trying to understand how convert C code to MIPS code and I have having trouble understanding why the stack pointer( $sp ) needs to be manipulated before and after the procedural code.Isn't the ...
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Parallel multiplication hardware

This picture is taken from Computer Organization and Design, Fourth Edition, David A. Patterson, John L. Hennessy. Sorry for the low resolution. I cannot get my head around it. I can see why the ...
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Stalling and Flushing in MIPS Piplining

I am learning MIPS data path with piplining and I am a little confused in the following two things? How do we perform Stall in MIPS data path? What is the difference between Stall and Flush? Here ...
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MIPS Relative Addressing

Can somebody please help me answer these three questions?: Two identified here: When we multiply the immediate operand by 4, do we multiply the binary or the decimal by 2^2? Is the addition sign for ...
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What was the advantage of a 64-bit processor in the N64?

The Nintendo 64 debuted in 1996 and featured a 64-bit MIPS processor. My understanding is that PCs didn't start appearing with 64-bit CPUs until 2003. What was the advantage of using a 64-bit CPU in ...
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Implementing Bne in MIPS Processor Circuit

I am trying to include BNE instruction in the following circuit without introducing a new control line. I have thought of many possible ways like adding muxes or and gates etc to implement it but ...
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280 views

Using JTAG to “explore” a board without damaging it?

I have one Amontec JTAGKey2 Generic USB JTAG cable interface. What I am looking for is some explanation of how to "explore" a device of which I don't know all exact details, but for which I have a ...
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Clarification on what the max freq of PIC24FJ64 is?

I'm confusing myself a bit here. The following is taken from this datasheet: High-Performance CPU: Modified Harvard Architecture Up to 16 MIPS Operation @ 32 MHz Now I want 16 MIPS, which is its ...
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MIPS (PIC32): branch vs. branch likely

It's been a while since I've looked at the recent Microchip processors & I've been trying to learn a little bit about the PIC32 MIPS instruction set. I noticed there are two sets of branch ...
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592 views

MIPS Pipeline Forwarding to MEM

Consider the following (incomplete) instruction schedule for a MIPS pipeline where loads and stores take three cycles: ...
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716 views

MIPS Main Control Logic

In the Patterson & Hennessy book, This is for these 4 instructions, if I need to implement instructions like andi, addi, ori, j, etc, do I add on to this table? Or do I do something else? ...
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How are various functions (eg. add, subtract, and, etc) implemented in ALU?

I am wondering since there are so many functions an ALU need to do, how might I start implementing one (a homework where I am supposed to implement a MIPS system with Logisim, using basic Gates, ...
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MIPS Assembly Memory Addressing “Pseudo Direct Addressing”

Could anyone explain how does Pseudo Direct Addressing work in MIPS? I don't really get how does using the last 4 bits from the PC (Program Counter) fit into the picture? Suppose I want to goto ...
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MIPS: MARS editor not showing correct value for ASCII string?

I'm using the MARS simulator to explore the MIPS cpu. I have a simple assembly program: .data ascii1: .asciiz "8C@2" I expect the value in the memory address ...