A n-channel metal-oxide semiconductor (nMOS) transistor has n-type carriers in the channel. A positive voltage on the gate turns inverts the substrate (PWell) creating the channel and turning the device on. The term may also be used to describe logic circuits built around nMOS transistors.

learn more… | top users | synonyms

0
votes
1answer
49 views

what would the drain voltage be if NMOS source voltage is not ground?

Hi I'm a beginner trying to learn CMOS cuicuit. Let's say we have two NMOS connected as shown. Given: A, B, C are connected to Vdd = 5V; VtM1 = 0.6V is the threshold voltage of M1; VtM2 = 0.5V ...
1
vote
0answers
28 views

NMOS saturation mode: why is there no channel?

I have a question about the saturation mode. The cross-section of an NMOS transistor in saturation mode is usually drawn like this: But it seems to me that there can be no current from source to ...
0
votes
0answers
29 views

What is the formula for the maximum permissible symmetrical input signal swing?

I have a common-source amplifier, and I am looking for the maximum no- load symmetrical output signal swing, and maximum permissible symmetrical input signal swing. I would like to know the formula ...
0
votes
1answer
23 views

NMOS amplifier simple question?

While studying the NMOS amplifiers in my book I came across operations with differential output voltages and this circuit specifically.I want to understand what are the drain voltages and what is the ...
1
vote
1answer
67 views

How to find the Q point of the NMOS trsistor in Voltage-Divider Biasing Circuit?

The following is the circuit needed to be analyzed to find the Q point(\$V_{GS_Q}, V_{DS_Q}, I_{D_Q}\$). \$V_{TN}=1\text{V}\$ \$K_n=0.5\text{mAV}^{-2}\$ simulate this circuit – Schematic ...
2
votes
1answer
32 views

Help with NMOS Gate question

In this picture, when v1 and v2 are 0, M1,M2 are on and M3,M4 are off. V_T(threshold) = 1.7V, V_DD = 5V. Why is it that M1 and M2 are ON under these conditions? I thought when there is no power ...
2
votes
2answers
65 views

DC analysis of common source MOSFET circuits to find gate voltage using different power supplies

simulate this circuit – Schematic created using CircuitLab strong text I am solving problems on DC analysis of MOSFET circuits. We are supposed to find various parameters like Id(Drain ...
0
votes
1answer
42 views

NMOS Channel Type

I've seen some conflicting information about the inversion channel for an NMOS device. Is NMOS n-channel or p-channel? And is the substrate n or p? I know PMOS is just the opposite for both and the ...
2
votes
2answers
98 views

Create a CMOS circuit from a logic function [duplicate]

I have to create a CMOS circuit from the logic function: F= ~A + B (notA or B). I made the truth table but I'm stuck here trying to make the CMOS circuit. Any ideas anyone? Thanks! I know it's the ...
3
votes
1answer
96 views

CMOS technology, use a NMOS or PMOS as series switch?

A general question regarding switches in CMOS. Have a look at the schematic below (symplified current mirror) There is a input reference current, on/off switch, a PMOS mirror and the resulting ...
0
votes
0answers
72 views

How to find small-signal output resistance?

Here is the exercise, I would appreciate any hint thank you: !
0
votes
1answer
63 views

Stable solution

To my understanding a stable solution for a transistors is when the voltage will not fluctuate due to to a change in Vin or something like that. My question I guess would be, where would I start ...
1
vote
1answer
86 views

Why feedback is activating at more than 4V?

In this circuit: I don't get why the current start flowing from more than 4V. I thought was due to threshold, but the same happens with an NPN as M2 or using an BS170. With this last one, ...
2
votes
2answers
69 views

Trying to find steady state

I'm taking my first course in electronic circuits and I'm a little lost when it comes to combining NMOS transistors with capacitors. In particular I am having trouble with finding the steady state for ...
0
votes
1answer
90 views

Source potential for MOSFET with grounded substrate

Considering the configuration below, the source's potential should be invariant with respect to Vg (as long as Vg>Vt). So Vs is equal to Vdd. But if the substrate is connected to the source, as ...
0
votes
0answers
116 views

Odd MOSFET behaviour (in Multisim)

I have this circuit that's behaving in a strange manner. I am getting a surprisingly low current value flowing through the inductor when the path includes the N-channel MOSFET. Please could someone ...
0
votes
0answers
19 views

Effects of threshold voltage and body effect in PMOS and NMOS devices [duplicate]

Why is it that in PMOS devices limitations due to voltage drop and body effect are not present unlike in NMOS?
1
vote
3answers
744 views

How can PMOS eliminate body effect but NMOS doesn't?

I have a question on the body effect of MOS transistor. In particular, how does the body effect in PMOS be eliminated (by connecting bulk to source together) while this similar technique doesn't do ...
1
vote
1answer
148 views

NMOS transistor: how does its structure relate to two interconnecting diode?

There is a popular idea that structure of NMOS transistor could be viewed as the inter-connecting diode across their PN junction. Therefore, when operating NMOS, you always want to keep the Source and ...
1
vote
0answers
58 views

Preference of MOS resistor as load in MOS inverter [closed]

Whys is a MOS resistor preferred over diffused resistor as load in design of a MOS inverter?
0
votes
1answer
46 views

Find Id of NMOS

I need to find the drain current in the above circuit where I also know \$V_{TH} = 1\,\mathrm{V}\$ and \$\mu_{n}C_{ox} = 2\cdot 10^{-4} \frac{\mathrm{A}}{\mathrm{V}^2}\$. I'm just not sure about ...
0
votes
2answers
123 views

NMOS: what exactly forms the inversion layer

I have a a question on forming of the inversion layer in NMOS. More specifically, please refer to the following figures The negative ions (in-mobile) are due to the the accumulation of the positive ...
0
votes
3answers
141 views

NMOS: why VGS instead of VG?

I am having lots of trouble trying to understand how the mosfet is triggered. The text I read assumes the source of the NMOS connect to ground, while a positive voltage is applied at the gate. ...
0
votes
0answers
51 views

Derivation of depletion layer in depletion mode in MOS Structure

First off, please understand my background. I am doing a course in Digital Integrated Circuits and following the book CMOS Digital Integrated Circuits and Design by Kang (3rd Edition). I barely have ...
1
vote
1answer
210 views

Charge Pump for driving NMOS

I was looking for a way to drive the gate of a power NMOS. Since I've already have a small FPGA available at a independent backup-3V3 rail, I was thinking I could use it's internal oscillator to build ...
0
votes
0answers
152 views

Voltage transfer characteristics of a C-mos inverter

How to determine the voltage transfer characteristics of a c-mos inverter during the region when both the p-mos and the n-mos transistors are in the saturation region.I know that both the transistors ...
0
votes
0answers
32 views

Using n-mos and p-mos transistors as pass transistors! [duplicate]

The n-mos passes a good '0' and the p-mos passes a good '1'.What is the logic behind this?Can anyone suggest a proper book to study Vlsi design?
1
vote
1answer
80 views

Short NMOS differential pair amplifier question?

In my book it says that in the NMOS differential pair: $$V_{G1}=V_{G2}=V_{CM}$$ But does not explain why. Can you please explain to me why the voltage in each gate is equal to the common mode ...
0
votes
1answer
274 views

n-type mosfet calculate AD AS PD PS

I have a nMOS and I want to calculate AD AS PD PS . Given: L=0.25μm and W = 2μm. We know that \$AD = W*L_D\$ and \$PD = W + 2*L_D\$ ...
1
vote
1answer
785 views

Using p-channel mosfet on high side of h-bridge, do I really need a driver chip?

I know there are fancy h-bridge ic's to drive high side of h-bridge but I guess that is when I have to drive n channel mosfet. I am planning on using p channel mosfets on high side and n channel ...
0
votes
3answers
143 views

term “fat” when referring to NMOS and PMOS

I'm uncertain of the term "fat" when referring to NMOS and PMOS. Tried google and nothing. Could I get a little clarification?
2
votes
1answer
488 views

Why doesn't a capacitor connected to a MOSFET charge to VDD

If an nmos which has the gate and drain connected to VDD, and the source connected to a grounded capacitor, the nmos will start conducting and the capacitor will start charging as long as VDD > VTn ...
1
vote
2answers
775 views

NMOS CS Amplifier PSpice Simulation Question

I have a rather peculiar question. I am attempting to recreate the circuit below (from one of my labs) of a Common-Source Amplifier design with a bypassed Source Resistance in PSpice. It has the ...
-1
votes
2answers
255 views

Pseudo-Nmos inverter in LTSPICE

In LTSPICE, I've built a pseudo-NMOS inverter and I've got 2 tasks to do using it. 1) I've a initial guess for Wn value of NMOS. I start the simulation with this value however, I need to optimize it ...
0
votes
2answers
329 views

Effect of Drain-source voltage on NMOS operation

I have been trying to understand the NMOS operation through various online tutorials but I am getting stuck in understanding the effect of increasing drain voltage on the flow of current and the ...
1
vote
1answer
92 views

Working principle of floating gate tunneling oxide

Floating gate tunneling oxide (FLOTOX) is used in electrically alterable rom. Tunneling of charge takes place through tunneling oxide into the floating gate. What is the working principle of this? How ...
4
votes
1answer
86 views

Presence of depletion layer in an N-MOSFET

The source and the substrate of an N-MOSFET are connected together and biased with zero potential. In spite of that, a thin depletion layer exists. Why?
1
vote
3answers
1k views

Low Drain-Source MOSFET Leakage

I've been looking at the SM74611 Smart Bypass Diode from Texas Instruments and am very impressed with the reported reverse leakage current (0.3uA at 25C). Considering the device has a N-Channel FET, ...
2
votes
1answer
724 views

nMOS passing 1's poorly and pMOS passing 0's poorly

I came across the statement in a digital design book that "nMOS transistors pass 0's well but pass 1's poorly" and "pMOS pass 1's well but 0's poorly". What exactly do these statements mean and why ...
3
votes
1answer
51 views

Mask Programmable Array Concept

I am having trouble understanding a lecture slide for Mask Programmable Arrays. The cell on the right is supposed to represent a 4-input NOR gate. But I just cant wrap my head around which pads ...
1
vote
3answers
431 views

Why does there have to be a load in MOS inverters?

I have been studying about inverters for a while. In the book that I was reading, inverters have been explained according to the type of load connected to the drain of the driving transistors ie. ...
1
vote
3answers
306 views

Digital Logic and Assertion levels

I'm struggling to get my head around assertion levels and how it relates to logic levels / functions. For example. Let's say we have 2 input signals, A and B So A assertive high and A assertive ...
0
votes
1answer
55 views

After all the transients have settled down what would be the output voltage

Vo(0)=5 , what is Vo(infinity) Can you please explain to me how i can get the answer.
3
votes
1answer
795 views

2 nmos in series

If we have 2 nmos transistors in series, as in the following circuit: simulate this circuit – Schematic created using CircuitLab Vth = 1v. My analysis is that M1 will allow it's source ...
4
votes
2answers
253 views

Does linearity of a N-MOSFET continue for \$V_{DS}\$ below \$0V\$?

I operate a N-MOSFET (2N7000) in a simulator in the linear region very close to \$V_{DS}=0\$. In fact \$V_{DS}\$ is between \$-50nV\$ and \$+50nV\$. In the simulator the output seems linear, but is ...
1
vote
1answer
100 views

Controlling a 300V node with 5V from a micro-controller

The goal is to drive a 47k load that requires at least 5mA of current. The design is as shown, with FET values matching their part number: An LTSpice simulation (with generic pmos and nmos devices) ...
0
votes
2answers
511 views

Using BSS138 in Level Switcher

I am trying to interface 1.8v UART and 3.3v UART using NXP app note here. Unfortunately, my circuit does not perform as expected. I am using BSS138 as mentioned in Adafruit and Spakrfun. When I ...
1
vote
1answer
172 views

Voltage regulator device selection

I intend to design a CMOS voltage regulator that takes 2.5V supply and outputs 1.2V. I am starting off with an opamp+pass transistor design. Will there be a specific advantage to using an NMOS ...
0
votes
1answer
196 views

Drawing VTC from IV

So I am given the IV characteristic plot along with the resistive load circuit which looks like: The load is a 25k resistor. I want to understand how to actually do the problem which is why i didn't ...
1
vote
1answer
816 views

CMOS Inverter Voltage Transfer Function

So let's say I have a perfectly symmetrical Voltage transfer function curve for my CMOS inverter. The curve looks like this: The question is, how would this curve change if the size of the NMOS ...