Tagged Questions

A n-channel metal-oxide semiconductor (nMOS) transistor has n-type carriers in the channel. A positive voltage on the gate turns inverts the substrate (PWell) creating the channel and turning the device on. The term may also be used to describe logic circuits built around nMOS transistors.

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Odd MOSFET behaviour (in Multisim)

I have this circuit that's behaving in a strange manner. I am getting a surprisingly low current value flowing through the inductor when the path includes the N-channel MOSFET. Please could someone ...
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19 views

Effects of threshold voltage and body effect in PMOS and NMOS devices [duplicate]

Why is it that in PMOS devices limitations due to voltage drop and body effect are not present unlike in NMOS?
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130 views

How can PMOS eliminate body effect but NMOS doesn't?

I have a question on the body effect of MOS transistor. In particular, how does the body effect in PMOS be eliminated (by connecting bulk to source together) while this similar technique doesn't do ...
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2answers
76 views

NMOS transistor: how does its structure relate to two interconnecting diode?

There is a popular idea that structure of NMOS transistor could be viewed as the inter-connecting diode across their PN junction. Therefore, when operating NMOS, you always want to keep the Source and ...
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43 views

Preference of MOS resistor as load in MOS inverter [closed]

Whys is a MOS resistor preferred over diffused resistor as load in design of a MOS inverter?
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1answer
31 views

Find Id of NMOS

I need to find the drain current in the above circuit where I also know \$V_{TH} = 1\,\mathrm{V}\$ and \$\mu_{n}C_{ox} = 2\cdot 10^{-4} \frac{\mathrm{A}}{\mathrm{V}^2}\$. I'm just not sure about ...
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50 views

NMOS: what exactly forms the inversion layer

I have a a question on forming of the inversion layer in NMOS. More specifically, please refer to the following figures The negative ions (in-mobile) are due to the the accumulation of the positive ...
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3answers
103 views

NMOS: why VGS instead of VG?

I am having lots of trouble trying to understand how the mosfet is triggered. The text I read assumes the source of the NMOS connect to ground, while a positive voltage is applied at the gate. ...
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30 views

Derivation of depletion layer in depletion mode in MOS Structure

First off, please understand my background. I am doing a course in Digital Integrated Circuits and following the book CMOS Digital Integrated Circuits and Design by Kang (3rd Edition). I barely have ...
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1answer
99 views

Charge Pump for driving NMOS

I was looking for a way to drive the gate of a power NMOS. Since I've already have a small FPGA available at a independent backup-3V3 rail, I was thinking I could use it's internal oscillator to build ...
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68 views

Voltage transfer characteristics of a C-mos inverter

How to determine the voltage transfer characteristics of a c-mos inverter during the region when both the p-mos and the n-mos transistors are in the saturation region.I know that both the transistors ...
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30 views

Using n-mos and p-mos transistors as pass transistors! [duplicate]

The n-mos passes a good '0' and the p-mos passes a good '1'.What is the logic behind this?Can anyone suggest a proper book to study Vlsi design?
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1answer
57 views

Short NMOS differential pair amplifier question?

In my book it says that in the NMOS differential pair: $$V_{G1}=V_{G2}=V_{CM}$$ But does not explain why. Can you please explain to me why the voltage in each gate is equal to the common mode ...
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1answer
171 views

n-type mosfet calculate AD AS PD PS

I have a nMOS and I want to calculate AD AS PD PS . Given: L=0.25μm and W = 2μm. We know that \$AD = W*L_D\$ and \$PD = W + 2*L_D\$ ...
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1answer
468 views

Using p-channel mosfet on high side of h-bridge, do I really need a driver chip?

I know there are fancy h-bridge ic's to drive high side of h-bridge but I guess that is when I have to drive n channel mosfet. I am planning on using p channel mosfets on high side and n channel ...
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3answers
116 views

term “fat” when referring to NMOS and PMOS

I'm uncertain of the term "fat" when referring to NMOS and PMOS. Tried google and nothing. Could I get a little clarification?
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1answer
213 views

Why doesn't a capacitor connected to a MOSFET charge to VDD

If an nmos which has the gate and drain connected to VDD, and the source connected to a grounded capacitor, the nmos will start conducting and the capacitor will start charging as long as VDD > VTn ...
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363 views

NMOS CS Amplifier PSpice Simulation Question

I have a rather peculiar question. I am attempting to recreate the circuit below (from one of my labs) of a Common-Source Amplifier design with a bypassed Source Resistance in PSpice. It has the ...
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2answers
192 views

Pseudo-Nmos inverter in LTSPICE

In LTSPICE, I've built a pseudo-NMOS inverter and I've got 2 tasks to do using it. 1) I've a initial guess for Wn value of NMOS. I start the simulation with this value however, I need to optimize it ...
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148 views

Effect of Drain-source voltage on NMOS operation

I have been trying to understand the NMOS operation through various online tutorials but I am getting stuck in understanding the effect of increasing drain voltage on the flow of current and the ...
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0answers
73 views

Gate capacitance in CMOS

Gate capacitance in an N-MOS consists of gate to body capacitance + gate to source capacitance + gate to drain capacitance. Now how does each component of this gate capacitance vary with different ...
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1answer
63 views

Working principle of floating gate tunneling oxide

Floating gate tunneling oxide (FLOTOX) is used in electrically alterable rom. Tunneling of charge takes place through tunneling oxide into the floating gate. What is the working principle of this? How ...
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1answer
84 views

Presence of depletion layer in an N-MOSFET

The source and the substrate of an N-MOSFET are connected together and biased with zero potential. In spite of that, a thin depletion layer exists. Why?
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633 views

Low Drain-Source MOSFET Leakage

I've been looking at the SM74611 Smart Bypass Diode from Texas Instruments and am very impressed with the reported reverse leakage current (0.3uA at 25C). Considering the device has a N-Channel FET, ...
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1answer
351 views

nMOS passing 1's poorly and pMOS passing 0's poorly

I came across the statement in a digital design book that "nMOS transistors pass 0's well but pass 1's poorly" and "pMOS pass 1's well but 0's poorly". What exactly do these statements mean and why ...
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1answer
42 views

Mask Programmable Array Concept

I am having trouble understanding a lecture slide for Mask Programmable Arrays. The cell on the right is supposed to represent a 4-input NOR gate. But I just cant wrap my head around which pads ...
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3answers
295 views

Why does there have to be a load in MOS inverters?

I have been studying about inverters for a while. In the book that I was reading, inverters have been explained according to the type of load connected to the drain of the driving transistors ie. ...
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3answers
170 views

Digital Logic and Assertion levels

I'm struggling to get my head around assertion levels and how it relates to logic levels / functions. For example. Let's say we have 2 input signals, A and B So A assertive high and A assertive ...
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1answer
54 views

After all the transients have settled down what would be the output voltage

Vo(0)=5 , what is Vo(infinity) Can you please explain to me how i can get the answer.
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554 views

2 nmos in series

If we have 2 nmos transistors in series, as in the following circuit: simulate this circuit – Schematic created using CircuitLab Vth = 1v. My analysis is that M1 will allow it's source ...
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2answers
222 views

Does linearity of a N-MOSFET continue for \$V_{DS}\$ below \$0V\$?

I operate a N-MOSFET (2N7000) in a simulator in the linear region very close to \$V_{DS}=0\$. In fact \$V_{DS}\$ is between \$-50nV\$ and \$+50nV\$. In the simulator the output seems linear, but is ...
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1answer
88 views

Controlling a 300V node with 5V from a micro-controller

The goal is to drive a 47k load that requires at least 5mA of current. The design is as shown, with FET values matching their part number: An LTSpice simulation (with generic pmos and nmos devices) ...
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2answers
327 views

Using BSS138 in Level Switcher

I am trying to interface 1.8v UART and 3.3v UART using NXP app note here. Unfortunately, my circuit does not perform as expected. I am using BSS138 as mentioned in Adafruit and Spakrfun. When I ...
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1answer
165 views

Voltage regulator device selection

I intend to design a CMOS voltage regulator that takes 2.5V supply and outputs 1.2V. I am starting off with an opamp+pass transistor design. Will there be a specific advantage to using an NMOS ...
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1answer
152 views

Drawing VTC from IV

So I am given the IV characteristic plot along with the resistive load circuit which looks like: The load is a 25k resistor. I want to understand how to actually do the problem which is why i didn't ...
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1answer
668 views

CMOS Inverter Voltage Transfer Function

So let's say I have a perfectly symmetrical Voltage transfer function curve for my CMOS inverter. The curve looks like this: The question is, how would this curve change if the size of the NMOS ...
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1answer
419 views

Nmos-bjt darlington pair dc bias. [Homework Help]

I have a homework assignment I need some help with. I wanted to know if someone could tell me if I'm doing the dc bias calculations correctly, if not, could someone nudge me in the right direction. ...
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3answers
944 views

what happens when transistors are interchanged in CMOS?

A basic cmos inverter will have a P-transistor upside and N-transistor down side. what happens if we reverse the p and n transistors?
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3answers
14k views

In an NMOS, does current flow from source to drain or vice-versa?

In an NMOS, does current flow from source to drain or vice-versa? This Wikipedia page is confusing me: http://en.wikipedia.org/wiki/MOSFET The above image confuses me. For the N-channel, it shows ...
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1answer
230 views

Mosfets with capacitor on drain?

I'm trying to understand nmos mosfets. My textbook has plenty of examples dealing with the nmos with resistors. But I'm currently dealing with a problem with a capacitor on the drain. I just haven't ...
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2answers
887 views

PSpice generates gray hair, not correct answers

I have an extremely simple circuit that involves a NMOS, three resistors, and a voltage source. The circuit and info are shown below. Please understand that I could probably analyze this circuit while ...
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3answers
220 views

Mixing NMOS and CMOS

I have an old system board for a pinball machine that I'm fixing up. One of the ROMs is failing post. The reason is because the 27S256 EPROM never had the sticker applied to the window, and due to a ...
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1answer
1k views

Where are the depletion PMOS transistors?

In school, I was taught about PMOS and NMOS transistors, and about enhancement- and depletion-mode transistors. Here's the short version of what I understand: Enhancement means that the channel is ...
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votes
1answer
3k views

How to determine Vth, Kn and delta from NMOS datasheet

Given this two graphs below, how do I determine Vth, Kn and delta from this? I used this formula's so far: The graphs are taken from the datasheet of Supertex VN10K Can someone please help me ...
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4answers
1k views

Strange behavior from n-channel MOSFET

I'm using BS170 N-channel enchantment enhancement mode MOSFET and have the following circuit: The idea behind it is that the MOSFET should act as a simple switch and turn the LED on and off ...
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4answers
2k views

Why old PMOS/NMOS logic needed multiple voltages?

Why does old PMOS/NMOS logic needed multiple voltages like +5, -5, and +12 volts? For example, old Intel 8080 processors, old DRAMs, e.t.c... I'm interested in the causes on the physical/layout ...