PCIe or PCI Express is a high-speed serial computer bus that offers higher speeds and a lower pin count than earlier standards such as PCI that it is designed to replace. Questions should relate to PCIe design issues not general consumer PC / peripheral issues.

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Mini PCIe switch with 1 lane 2 devices?

I have a doubt, I have a SoC with 1 lane of PCIeV2 and I want to connect 2 wifi modules through PCIe to the SoC, so I want to use a PCIe switch to do it (the 802.11n is 600 Mbit/s and the PCIeV2 is ...
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PCI-Express Processor/Co-processor cards [closed]

I am hoping someone might be able to help: In the days when I started with computing (C64 and later Amigas) expansion slot cards with co-processing ability were relatively common. I am looking for ...
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3answers
117 views

GPIO/PCIe programing

I want to connect a PCIe 16x 3.0 GPU card to a Raspberry pi. I don't mind lo loose bandwidth, i just want to use the core GPU capabilities. So, the only idea that came out to my mind is to use the 26 ...
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94 views

gold finger plating needed on prototype board edge connector?

I am making a PCIe card and will be ordering prototypes. I know that in my production cards I should order hard gold plating on the edge connector. Can I skip this plating on my prototype cards to ...
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161 views

pci express bifurcation - clock fanout buffer needed to split reference clock?

I am designing for a motherboard with a single PCIe x16 slot which can be bifurcated into 2 logical x8 slots with jumper settings. I am designing a board to handle the physical splitting of the port. ...
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148 views

Is it possible to only utilise SMBus on PCI Express 1X?

According to the Wikipedia page on PCI Express, the PCI-e 1X slots have 18 pin positions on two lanes (so 36 pins) and positions 5-9 represent SMBus and JTAG. I'd like to hook up a µC as an ...
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83 views

PCIE reference clock

I recently completed a PCI-E Gen 1.0 line card design. The line card consisted of 4 Spartan 6 FPGAs sharing one PCIE reference clock. Early on in the design there was a decision to solely use the PCIE ...
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79 views

PCIe branching - Requirement of Switch

Considering the following scenario: A designer wants to connect 3 devices on a PCIe x4 finger edge connector, commonly found on mother boards. All 3 devices will be populated on the same PCIe card. ...
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74 views

PCIe card powered but not recognized on custom interface

I have a black magic declink mini recorder card that I am trying to recognize on a small form factor linux machine (debian 3.2.46-1 x86_64). I have made a custom interface board with what I think are ...
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124 views

Motherboard with separate circuitry for PCIe, CPU, RAM etc [closed]

I asked this question on another forum (http://www.tomshardware.com/answers/id-1812014/motherboard-separate-circuitry-pcie-cpu-ram.html) but nobody replied yet so posting it here I am looking for an ...
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103 views

Can't read user-defined configuration space pci-express IP Virtex 6 Xilinx in testbench

I use IP core PCI-E for Virtex-6 v.2.5 There is configuration space in PCI-E It divides on standart space of PCI-E and vendor-specified or user-defined configuration space. There are two types of ...
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151 views

PCIe: Who's in charge here?

I want to construct a matrix of smart boards that receive ethernet packets, decode them, and place the decoded results onto a memory "matrix" for other boards to process and re-transmit. Given the ...
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709 views

What does “configuration” refer to in PCI and PCIe? How is this different from “Enumeration”

I am not being able to find a clear description of what configuration means in PCI and PCIe. I have found something called as configuration space, but without knowing what configuration means, it is ...
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1answer
660 views

What do the different interrupts in PCIe do? I referring to MSI, MSI-X and INTx

We have the following interrupts: MSI, MSI-X and INTx. What do these different type of interrupts do in PCIe? I only need a short description. I only know that in PCIe interrupts are generated as ...
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203 views

What is the utility of the reference clock in PCI express?

I understand that PCI express is a serial connection with clock embedded with the signals. So, what is the utility of the reference clock signal? What is it used for? Does the reference clock have to ...
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2answers
133 views

PC shares memory with external microcontroller

I'm looking for a PC hardware interface that matches these needs- The PC will constantly be busy performing calculations. Each time there is a calculation result (every ~1ms) I want it to share it ...
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1answer
97 views

Can a designer get hold of the PCI Express specification without being a member of the PCI SIG group? [closed]

I want to get hold of the PCI Express specification which is available here . But when I try to download it, it asks me to login as a member - which requires membership at $3000 per year. Is it ...
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413 views

PCIe fails on “polling compliance” state

I am using the PCIe block of Altera Cyclone IV FPGA, and I have an issue whereby about half the PCIe slots I have tried (on three different computers) do not work. Debugging with SignalTap shows that ...
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447 views

6-Layer Stackup for PCI express design

I'm pondering over a stackup for a 6-layer board using a couple of PCIe connected ICs. My first idea was to use the following Stackup: Signal GND Power (Multiple power supplies, so it's a split ...
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254 views

Can I remove unneeded 2 plugs from PCI-E power cable?

I have a PCI-E PSU power cable and I have two unneeded pins at the end (only need 6 power pins but have 6+2). Can I simply remove the pin where these two wires enter the PSU? I wouldn't think that ...
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1answer
238 views

PCIe Reference Clock logic level

I have a PCIe reference clock generator chip, ASVMPHC-100.000MHZ-LR (datasheet), but it generates a sinusoidal waveform at 100 MHz with an amplitude of ~750 mV. Should I be running this through a NOT ...
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334 views

PCIe Prototyping Backplane

I am trying to interface a TI c6678 8 core DSP evaluation board to a USB camera. The TI chip / board does not have USB, it has 1 SPI, 1 UART, 1 PCIe (2 lanes), and SRIO. The eval board only has an ...
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710 views

How do PCI Express Graphics Cards pull power from both the slot and the external 6-pin connector?

A x16 PCI Express slot can deliver 75W for PCI Express Graphics Card. Some graphics card today also use external PCI Express power to increase above this limit, the most basic of these is the 6-pin ...
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How can I power my 6-pin PCI Express card without using an ATX power supply?

One of my older computers has a 365-watt power supply that, for various reasons, cannot be replaced with a new power supply. I would like to upgrade the graphics card in that computer, but all the ...
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167 views

FPGA project sanity check, PCIE and video processeing

I have an Altera DE4 education FPGA that I'd like to use for video processing... But the thing doesn't have many ports to work with, and I don't have the funds to purchase any daughter boards. My ...
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175 views

Can Thunderbolt be used to power the host device?

Could the Thunderbolt interface be used to provide power to the PCIe host device? In this case, this would be a battery-powered mobile device, connecting to a range of peripherals. Thunderbolt here ...
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335 views

PCI-Express on SATA or SATA on PCI-Express damaging?

OK, at first this sounds like an obvious and serious design error. But I'm trying to figure out muxing the SERDES signals on a PCI-Express Mini card, such as WiFi cards in laptops and mSATA cards in ...
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4k views

WiFi module says “mini PCI-e format” with “USB host interface” - what does this mean?

The specifications of a WiFi module meant for embedded projects, says -- mini PCIe format Host interface supports USB.2.0 Works with any board with mini PCIe. Not sure about the interplay of mini ...
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2answers
492 views

Difference between busses

I think I am confusing the difference between some of the of busses, such as IDE, SATA, USB, and PCI. What is the relationship between all four, how are they connected to each other? From what I read ...
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3answers
2k views

AC coupling on PCIe layout

I'm working on a layout in which two chips connect to each other through a 1x PCIe bus. The two chips are on one board. One of the chips is the Xilinx Spartan6 LX75T so I've been working with the ...
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1answer
393 views

Low cost PCI Express development board

I'm looking for a low cost (less than $100) board with a PCI Express (x1) interface and with some kind of a programmable CPU that can use that interface. I don't need anything fancy, just something ...
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423 views

How can I get touchscreen (HID) data into Windows 7?

We have a hardware design in progress that is taking touch screen inputs and passing them along via I2C to an FPGA. The FPGA translates the I2C data to PCIe. The PCIe passes the touchscreen data to ...
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368 views

Guidelines on branching of a PCI express signal

We have 3 PCIe slots on a board, let's call them A, B and C. On this board, slot A will always be populated with a PCIe device, however, among slots B and C, only one of them will be populated. There ...
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457 views

PCIe over a short cable

For a new project I need to connect two boards via PCI express. For space reasons a custom cable assembly would be the best solution. But I'm not sure what is the best way to go here. I've seen ...
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What does the “posted” mean in posted PCIE transaction?

What is the etymology of the word "posted" in "posted PCIE transaction"? I've worked with PCIE and I understand the difference between "posted" and "non-posted" PCIE transactions, but I don't ...