PCIe or PCI Express is a high-speed serial computer bus that offers higher speeds and a lower pin count than earlier standards such as PCI that it is designed to replace. Questions should relate to PCIe design issues not general consumer PC / peripheral issues.

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PCIe Endpoint Enumeration

I have a x4 PCIe(Host) Lane which I am connecting to a PCIe Switch. With PCIe Switch , I have connected 8 PCIe SSD Drives(End points). When I am doing power up, the PCIe Bus is getting enumerated ...
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PCIe DIY protocol analyzer / packet spy / monitor - project

I'm interested in making a device that I can plug into a PCIe slot that can capture PCIe protocol packets. Along the same lines find a low cost solution so a hobbyist can make their own PCIe interface ...
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How PCI Express Hardware Interface communicate with device core?

I'm currently reading the book which name is "PCI Express System Architecture" and i need some answers; 1.)How PCI Express Interface sends TLPs(transaction layer packets) to device core(suppose that ...
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Setting up T2080 to FPGA PCie DMA

I'm doing an FPGA design using a T2080 MPC interfacing to an Altera Cyclone V FPGA. The goal is to use my FPGA to pump 2 other FPGAs on the same board. I need to create a scheme that allows the ...
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How PCIe can tranmit data at 2.5 GTps?

Serial transceiver for PCIe is using Reference clock of 100MHz. Then how data transfer at the rate of 2.5 GTs is possible?
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PCI-Express and FPGA Development Boards

I'm interested in using some high-performance FPGA development boards, but it seems like most of the high-end, modern options from both Xilinx (Digilent) and Altera (Terasic) seem to be PCIe-based ...
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What is the maximum rate at which two PCIe 1.0 device can communicate with each other?

I went through some PCIe documents. What I found is " transfer rate of PCIe is 2Gbits per second. So 2 Gbps is the maximum rate or is it the only rate at which two PCIe device can communicate? Edit: ...
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Can two PCIe endpoints communicate with each other through PCIe switch?

Figure shows basic architecture of PCIe. From what I understood, Root complex block will convert data into PCIe format. That means PCIe endpoint to endpoint communication will happens through Root ...
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Why there are two or more PCIe Hard IPs in some FPGAs?

I was looking for FPGA with PCIe Hard IPs. And I found some FPGAs with more than one Hard IPs. what is the advantage of having more than one Hard IPs in a single FPGA?
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71 views

How to feed data into a PCIe hard IP?

I want to implement FPGA module which can communicate using PCIe. I am using Stratix IV GX which has PCIe Hard IP in it. How I can use this Hard IP module to communicate. To develop my module I ...
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42 views

PCIe switch connection

I have designed a board with a SoC (I.MX6) and a PCIe switch (PEX8605), everthing it's working in the board exept the PCIe switch, we can't even recognise it with lspci, dmesg..., so I wanna check if ...
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USB 3.1 Alt-mode standards for PCI Express

Is there a central set of standards for USB 3.1 alt-modes? I have seen standards for DisplayPort and MHL but nothing else yet. Is PCI Express going to have a standard? I have seen suggestions that ...
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302 views

How to make an external PCI adapter that runs on USB3.0?

Motivated by old PCI (NOT PCIe) cards, and laptops without expansion slots, I want to try making a PCI-over-USB 3.0 solution. This is about 70% experimentation, and 30% actual use. Is this viable? I ...
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109 views

PCI Memory and I/O space

I'm currently reading Carl Hamacher's computer organization boook.At Chapter 3 he describes the generic i/o device interface like this : "An I/O device is connected to the interconnection network by ...
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68 views

Can I connect multiple computers with PCIe? [closed]

I've got an crazy idea about obtaining some Computer on Module boards having PCIe connection. Putting them in PCIe network, not ethernet network. Is it possible to connect multiple computers / CoMs ...
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197 views

Why doesn't PCIe and similar signaling systems use half-duplex links?

I'd like to get more PCIe bandwidth for GPU compute applications. It occurred to me that PCIe bidirectional links are really dual simplex (a pair of unidirectional links). That means if there's no ...
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Is USB-C a technically viable substitute for SATA Express connectors?

SATA Express, the successor to SATA, is too new to be widely used yet, but the advancing speed of SSDs appears to make it inevitable, the same as SATA replaced parallel IDE. Despite the name, it isn't ...
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379 views

Does the USB-C Alt Mode specification require support of the USB 3 protocol?

If a device is designed with a USB-C port that's intended for use exclusively in an alt mode such as Displayport or PCIe rather than for use as a general-purpose USB port, then the hardware to support ...
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Advice: how to integrate minipci cards to a board design

I'm designing a pcb card for one embedded device based on a Digi iMX28 module. In the design we included a couple of minipcie sockets to add 3G and wifi cards. However, there are two flavors of ...
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WiFi card without host device

So to start I wasn't quite sure about where this question should be asked, so feel fre to relocate it if you want. I'm setting up a system to notify me when a user enters an area. My plan is to use ...
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217 views

What Gerber file extension is used to specify PCIe edge connector plating?

I am designing a PCB in Eagle using the mini PCIe card format and am not sure how to specify finger plating the board edge connector to the PCB fabricator. These plating regions are specified in Eagle ...
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71 views

UART, USB… on cellular cards

Sierra Wireless and other manufacturer carry cellular cards in a variety of physical interfaces. There are different digital interfaces to hardware like USB, UART, USB OTG, HSIC... Additionally ...
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298 views

How to power an x16 PCIe card in an x8 slot?

In the cryptocurrency community, when GPU-mining was profitable, it was common for people to use ribbon cables to connect the graphics cards to PCIe slots. This lets one use more GPUs than there are ...
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PCI express. Connect of GP1-GP4 pins

We develop a PXI express peripheral card. The interface is by PLX8311 works as "endpoint mode". The interface beginning to work fine but we don't understand how to connect these pins(GP1-GP4). Right ...
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108 views

Switch PCIe connections

I'm trying to implement a PCI express switch; one lane from SoC and, two for mini PCIe ports. Something like the picture below. But I'm confused with the Tx and Rx connections, the transmitter ...
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335 views

How to simulate PCIe to debug my FPGA endpoint

I'm working on an FPGA controller connected through PCIe. The only way I can debug the hardware is using chipscope. So I execute commands through my driver and check out the signals from the FPGA. ...
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Ways to connect a PCIe/PCIe2 card and other PC parts to a breadboard?

Basically I have a bunch of rather old computer parts that I haven't been able to get rid of so I decided to do a few experiments with them but for that I need to be able to breadboard them. Things ...
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257 views

PCIe add-in card thickness tolerance

I can't find a tolerance measurement for the 62 mils thickness specified in the PCIe electromechanical spec. How much leeway do I have for board thickness in an add-in card. Additional details: I'm ...
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232 views

Why are there so many signal grounds for PCI Express?

PCIe connections have one to two ground contacts per differential signal pair. Why is this the case? On the boards that I have been studying, all of these pins are tied together onto the same ground ...
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263 views

PCI-Express Processor/Co-processor cards [closed]

I am hoping someone might be able to help: In the days when I started with computing (C64 and later Amigas) expansion slot cards with co-processing ability were relatively common. I am looking for ...
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683 views

GPIO/PCIe programing

I want to connect a PCIe 16x 3.0 GPU card to a Raspberry pi. I don't mind lo loose bandwidth, i just want to use the core GPU capabilities. So, the only idea that came out to my mind is to use the 26 ...
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350 views

gold finger plating needed on prototype board edge connector?

I am making a PCIe card and will be ordering prototypes. I know that in my production cards I should order hard gold plating on the edge connector. Can I skip this plating on my prototype cards to ...
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pci express bifurcation - clock fanout buffer needed to split reference clock?

I am designing for a motherboard with a single PCIe x16 slot which can be bifurcated into 2 logical x8 slots with jumper settings. I am designing a board to handle the physical splitting of the port. ...
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Is it possible to only utilise SMBus on PCI Express 1X?

According to the Wikipedia page on PCI Express, the PCI-e 1X slots have 18 pin positions on two lanes (so 36 pins) and positions 5-9 represent SMBus and JTAG. I'd like to hook up a µC as an ...
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PCIE reference clock

I recently completed a PCI-E Gen 1.0 line card design. The line card consisted of 4 Spartan 6 FPGAs sharing one PCIE reference clock. Early on in the design there was a decision to solely use the PCIE ...
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PCIe branching - Requirement of Switch

Considering the following scenario: A designer wants to connect 3 devices on a PCIe x4 finger edge connector, commonly found on mother boards. All 3 devices will be populated on the same PCIe card. ...
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PCIe card powered but not recognized on custom interface

I have a black magic declink mini recorder card that I am trying to recognize on a small form factor linux machine (debian 3.2.46-1 x86_64). I have made a custom interface board with what I think are ...
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Motherboard with separate circuitry for PCIe, CPU, RAM etc [closed]

I asked this question on another forum (http://www.tomshardware.com/answers/id-1812014/motherboard-separate-circuitry-pcie-cpu-ram.html) but nobody replied yet so posting it here I am looking for an ...
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Can't read user-defined configuration space pci-express IP Virtex 6 Xilinx in testbench

I use IP core PCI-E for Virtex-6 v.2.5 There is configuration space in PCI-E It divides on standart space of PCI-E and vendor-specified or user-defined configuration space. There are two types of ...
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PCIe: Who's in charge here?

I want to construct a matrix of smart boards that receive ethernet packets, decode them, and place the decoded results onto a memory "matrix" for other boards to process and re-transmit. Given the ...
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What does “configuration” refer to in PCI and PCIe? How is this different from “Enumeration”

I am not being able to find a clear description of what configuration means in PCI and PCIe. I have found something called as configuration space, but without knowing what configuration means, it is ...
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What do the different interrupts in PCIe do? I referring to MSI, MSI-X and INTx

We have the following interrupts: MSI, MSI-X and INTx. What do these different type of interrupts do in PCIe? I only need a short description. I only know that in PCIe interrupts are generated as ...
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559 views

What is the utility of the reference clock in PCI express?

I understand that PCI express is a serial connection with clock embedded with the signals. So, what is the utility of the reference clock signal? What is it used for? Does the reference clock have to ...
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307 views

PC shares memory with external microcontroller

I'm looking for a PC hardware interface that matches these needs- The PC will constantly be busy performing calculations. Each time there is a calculation result (every ~1ms) I want it to share it ...
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158 views

Can a designer get hold of the PCI Express specification without being a member of the PCI SIG group? [closed]

I want to get hold of the PCI Express specification which is available here . But when I try to download it, it asks me to login as a member - which requires membership at $3000 per year. Is it ...
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PCIe fails on “polling compliance” state

I am using the PCIe block of Altera Cyclone IV FPGA, and I have an issue whereby about half the PCIe slots I have tried (on three different computers) do not work. Debugging with SignalTap shows that ...
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727 views

6-Layer Stackup for PCI express design

I'm pondering over a stackup for a 6-layer board using a couple of PCIe connected ICs. My first idea was to use the following Stackup: Signal GND Power (Multiple power supplies, so it's a split ...
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Can I remove unneeded 2 plugs from PCI-E power cable?

I have a PCI-E PSU power cable and I have two unneeded pins at the end (only need 6 power pins but have 6+2). Can I simply remove the pin where these two wires enter the PSU? I wouldn't think that ...
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PCIe Reference Clock logic level

I have a PCIe reference clock generator chip, ASVMPHC-100.000MHZ-LR (datasheet), but it generates a sinusoidal waveform at 100 MHz with an amplitude of ~750 mV. Should I be running this through a NOT ...
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663 views

PCIe Prototyping Backplane

I am trying to interface a TI c6678 8 core DSP evaluation board to a USB camera. The TI chip / board does not have USB, it has 1 SPI, 1 UART, 1 PCIe (2 lanes), and SRIO. The eval board only has an ...