PCIe or PCI Express is a high-speed serial computer bus that offers higher speeds and a lower pin count than earlier standards such as PCI that it is designed to replace. Questions should relate to PCIe design issues not general consumer PC / peripheral issues.

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EEPROM for PXIe card [on hold]

I am working with an home made PXIe card. The PXie controller is a PEX8311. The EEPROM used to save name and configuration registers is a 93C66. I need more user space to save calibration data and ...
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19 views

PCI Clock from the PCIe to PCI bridge

I have designed PCI interface using PCIe to PCI in forward Bridge mode at 33MHz PCI clock. I have interfaced 4 identical PCI devices to bridge directly. The interface design seems correct as per PCI ...
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41 views

Can SSC be a problem if operating PCIe interface asynchronously through a re-driver?

I am operating PCIe over copper cables via re-drivers asynchronously. i.e. I only send over the RX/TX data. The clock is sourced locally at the end point. For the host root port, I am designing a ...
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1answer
23 views

Can I use sfp+ transceivers to interconnect PCIe x1 lane?

This is interesting because, sfp+ offers an inexpensive way to use optics to connect two PCIe x1 devices. But I do not know enough about sfp+ to know if I can simply connect up pcie lanes on a ...
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1answer
40 views

PCIe power when system off

I'm looking into developing a device that will be installed in a PCIe slot but not communicate with the CPU. It will be a standalone device using either the 3v3 or 12v supplies at fairly low current(~...
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2answers
127 views

Simple binary adder works only partially

LATER EDIT: 1. I've also investigated visually the Kintex7 device after implementation (i.e. interconnections, etc.) and everything looks OK - no connections that would indicate things would not be ...
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1answer
45 views

Can i run several links through single pcie x8 connector?

I want to use PCIe with four to eight remote devices, and preferably to avoid PCIe switch. In PCIe connector i can see enough lanes for that, but i definitely don't want to use eight separate cards ...
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2answers
179 views

Difference between General purpose PCIe signals and PCI Express Graphics (PEG)

What is the difference between General purpose PCIe signals and PCI Express Graphics (PEG) in standard COM modules (type-6) ?
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1answer
76 views

Fast write/read on NVRAM with Windows

I am trying to find a solution to create a 4MBit NVRAM module (FRAM or SRAM, doesn't matter) with a standard PC with Windows. I want to store up to 1MB of data in less than 1 second with 50-100 write ...
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3k views

Does PCIe hotplug actually work in practice?

I've got into a discussion in the comments of http://security.stackexchange.com/questions/109199/is-physical-security-less-important-now-for-securing-a-server?noredirect=1#comment194327_109199 The ...
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1answer
133 views

Can an FPGA connected to a CPU via PCIE access peripheral devices?

Is it possible for an FPGA connected via PCIE to a CPU, to directly access peripherals (USB Ports, data, Ethernet, etc) connected to the same CPU via a chipset? I had an Intel based system in mind, ...
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2answers
41 views

PCIe Data clocked refclk question

When only one clock is used in PCIe and let's assume the clock is connected to device A. How does device B transfer data to device A. Device B does not have a clock source.
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54 views

M.2 Daughter card interface

I am planning to use M.2 daughter card in a design. I know that M.2 form factor support various type of cards like LTE, Wifi, BT, SSD etc. My doubt is that what is the host side interface for these ...
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1answer
929 views

PCIe PRSNT# signal connection

I am using a PCIe x16 conn. It has 2 types of PRSNT# pins. My question is :- What is the purpose of PRSNT#1 pin. We have four PRSNT#2 pins in x16. (PRSNT#2_1/2/3/4). The purpose of these pins is hot ...
8
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1answer
268 views

enable/disable PCI interrupts

I'm implementing a PCIe driver, and I'd like to understand at what level the interrupts can be or should be enabled/disabled. I intentionally do not specify OS, as I'm assuming it should be relevant ...
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1answer
366 views

Pin dimensions on PCI Express card edge

I can see this as being 50/50 between here and Eng.SE, so I decided to ask here as it deals with the PCI Express standard. I'm attempting to create a library of PCI Express card edge footprints in ...
2
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1answer
140 views

CycloneIV PCIe hard IP fixedclk_serdes generation

I'm trying to build a minimal design with PCIe on CycloneIV, and have trouble getting the core_clk_out to actually run. In the PCIe user guide, page 13-9, it says ...
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2answers
306 views

PCI Express data transfer method? Serial VS Parallel

This is probably very basic, so please bare with me. In one hand, I read that PCIe is used for serial data communication, but on the other hand, it comes with x1, x2, x4, x8, x16 and x32 flavours. But ...
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1answer
457 views

Address Spaces in PCIe

There are four address spaces in PCI express: Memory Mapped I/O mapped Configuration Space Message Can anyone please explain significance of each address space, and it's purpose in brief ? As per ...
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1answer
455 views

Cheapest FPGA PCIe board for Software Acceleration [closed]

This question is somewhat related to an earlier question: Cheapest FPGA's. I have been searching for a cheap FPGA board with PCI express 2.0 or 3.x support. Such boards can be plugged in one of the ...
15
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1answer
532 views

PCIe, diagnosing and improving an eye diagram

I have implemented a design that uses PCIe. It is somewhat different in that the PCIe interface is used as a chip-to-chip communication lane on a single PCB (e.g. no PCIe connector). The root ...
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1answer
128 views

PCIe Endpoint Enumeration

I have a x4 PCIe(Host) Lane which I am connecting to a PCIe Switch. With PCIe Switch , I have connected 8 PCIe SSD Drives(End points). When I am doing power up, the PCIe Bus is getting enumerated &...
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2answers
440 views

PCIe DIY protocol analyzer / packet spy / monitor - project

I'm interested in making a device that I can plug into a PCIe slot that can capture PCIe protocol packets. Along the same lines find a low cost solution so a hobbyist can make their own PCIe interface ...
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2answers
158 views

How PCI Express Hardware Interface communicate with device core?

I'm currently reading the book which name is "PCI Express System Architecture" and i need some answers; 1.)How PCI Express Interface sends TLPs(transaction layer packets) to device core(suppose that ...
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92 views

Setting up T2080 to FPGA PCie DMA

I'm doing an FPGA design using a T2080 MPC interfacing to an Altera Cyclone V FPGA. The goal is to use my FPGA to pump 2 other FPGAs on the same board. I need to create a scheme that allows the ...
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2answers
93 views

How PCIe can tranmit data at 2.5 GTps?

Serial transceiver for PCIe is using Reference clock of 100MHz. Then how data transfer at the rate of 2.5 GTs is possible?
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3answers
296 views

PCI-Express and FPGA Development Boards

I'm interested in using some high-performance FPGA development boards, but it seems like most of the high-end, modern options from both Xilinx (Digilent) and Altera (Terasic) seem to be PCIe-based ...
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1answer
34 views

What is the maximum rate at which two PCIe 1.0 device can communicate with each other?

I went through some PCIe documents. What I found is " transfer rate of PCIe is 2Gbits per second. So 2 Gbps is the maximum rate or is it the only rate at which two PCIe device can communicate? Edit: ...
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1answer
607 views

Can two PCIe endpoints communicate with each other through PCIe switch?

Figure shows basic architecture of PCIe. From what I understood, Root complex block will convert data into PCIe format. That means PCIe endpoint to endpoint communication will happens through Root ...
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1answer
110 views

Why there are two or more PCIe Hard IPs in some FPGAs?

I was looking for FPGA with PCIe Hard IPs. And I found some FPGAs with more than one Hard IPs. what is the advantage of having more than one Hard IPs in a single FPGA?
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1answer
362 views

How to feed data into a PCIe hard IP?

I want to implement FPGA module which can communicate using PCIe. I am using Stratix IV GX which has PCIe Hard IP in it. How I can use this Hard IP module to communicate. To develop my module I ...
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2answers
2k views

How to make an external PCI adapter that runs on USB3.0?

Motivated by old PCI (NOT PCIe) cards, and laptops without expansion slots, I want to try making a PCI-over-USB 3.0 solution. This is about 70% experimentation, and 30% actual use. Is this viable? I ...
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1answer
322 views

Can I connect multiple computers with PCIe? [closed]

I've got an crazy idea about obtaining some Computer on Module boards having PCIe connection. Putting them in PCIe network, not ethernet network. Is it possible to connect multiple computers / CoMs ...
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3answers
498 views

Why doesn't PCIe and similar signaling systems use full-duplex links?

I'd like to get more PCIe bandwidth for GPU compute applications. It occurred to me that PCIe bidirectional links are really dual simplex (a pair of unidirectional links). That means if there's no ...
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2answers
3k views

Is USB-C a technically viable substitute for SATA Express connectors?

SATA Express, the successor to SATA, is too new to be widely used yet, but the advancing speed of SSDs appears to make it inevitable, the same as SATA replaced parallel IDE. Despite the name, it isn't ...
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1answer
719 views

Does the USB-C Alt Mode specification require support of the USB 3 protocol?

If a device is designed with a USB-C port that's intended for use exclusively in an alt mode such as Displayport or PCIe rather than for use as a general-purpose USB port, then the hardware to support ...
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1answer
49 views

WiFi card without host device

So to start I wasn't quite sure about where this question should be asked, so feel fre to relocate it if you want. I'm setting up a system to notify me when a user enters an area. My plan is to use ...
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2answers
361 views

What Gerber file extension is used to specify PCIe edge connector plating?

I am designing a PCB in Eagle using the mini PCIe card format and am not sure how to specify finger plating the board edge connector to the PCB fabricator. These plating regions are specified in Eagle ...
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1answer
117 views

UART, USB… on cellular cards

Sierra Wireless and other manufacturer carry cellular cards in a variety of physical interfaces. There are different digital interfaces to hardware like USB, UART, USB OTG, HSIC... Additionally ...
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213 views

Switch PCIe connections

I'm trying to implement a PCI express switch; one lane from SoC and, two for mini PCIe ports. Something like the picture below. But I'm confused with the Tx and Rx connections, the transmitter ...
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1answer
699 views

How to simulate PCIe to debug my FPGA endpoint

I'm working on an FPGA controller connected through PCIe. The only way I can debug the hardware is using chipscope. So I execute commands through my driver and check out the signals from the FPGA. ...
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3answers
529 views

Ways to connect a PCIe/PCIe2 card and other PC parts to a breadboard?

Basically I have a bunch of rather old computer parts that I haven't been able to get rid of so I decided to do a few experiments with them but for that I need to be able to breadboard them. Things ...
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1answer
704 views

PCIe add-in card thickness tolerance

I can't find a tolerance measurement for the 62 mils thickness specified in the PCIe electromechanical spec. How much leeway do I have for board thickness in an add-in card. Additional details: I'm ...
4
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1answer
368 views

Why are there so many signal grounds for PCI Express?

PCIe connections have one to two ground contacts per differential signal pair. Why is this the case? On the boards that I have been studying, all of these pins are tied together onto the same ground ...
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2answers
909 views

PCI-Express Processor/Co-processor cards [closed]

I am hoping someone might be able to help: In the days when I started with computing (C64 and later Amigas) expansion slot cards with co-processing ability were relatively common. I am looking for ...
0
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4answers
1k views

GPIO/PCIe programing

I want to connect a PCIe 16x 3.0 GPU card to a Raspberry pi. I don't mind lo loose bandwidth, i just want to use the core GPU capabilities. So, the only idea that came out to my mind is to use the 26 ...
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2answers
602 views

gold finger plating needed on prototype board edge connector?

I am making a PCIe card and will be ordering prototypes. I know that in my production cards I should order hard gold plating on the edge connector. Can I skip this plating on my prototype cards to ...
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1answer
1k views

pci express bifurcation - clock fanout buffer needed to split reference clock?

I am designing for a motherboard with a single PCIe x16 slot which can be bifurcated into 2 logical x8 slots with jumper settings. I am designing a board to handle the physical splitting of the port. ...
4
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1answer
1k views

Is it possible to only utilise SMBus on PCI Express 1X?

According to the Wikipedia page on PCI Express, the PCI-e 1X slots have 18 pin positions on two lanes (so 36 pins) and positions 5-9 represent SMBus and JTAG. I'd like to hook up a µC as an ...
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343 views

PCIE reference clock

I recently completed a PCI-E Gen 1.0 line card design. The line card consisted of 4 Spartan 6 FPGAs sharing one PCIE reference clock. Early on in the design there was a decision to solely use the PCIE ...