Questions tagged [pcie]
PCIe or PCI Express is a high-speed serial computer bus that offers higher speeds and a lower pin count than earlier standards such as PCI that it is designed to replace. Questions should relate to PCIe design issues not general consumer PC / peripheral issues.
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How many lanes of PCIe does Thunderbolt 4 use?
Searching shows that Thunderbolt 4 uses 4 lanes of PCIe 3.0; each lane should contain 3 twisted pairs, two for communication (TX and RX) and one for reference clock. The pinout of Thunderbolt 4 is ...
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Designing a U.2 to M.2 NVMe adapter
I'm considering designing my own U.2 to M.2 converter card to make use of the four U.2 (PCIe 3.0 x4) connectors on my motherboard. Commercial products are available for doing this type of conversion, ...
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PCIe PRST pin functionality at M2 connector (B) with SATA device (reboot detection)
M2 connector type (key B) support PCIe ×2, SATA, USB 2.0 and 3.0, audio, UIM, HSIC, SSIC, I2C and SMBus.
I want to use SATA interface with my device, but I need to detect the reboot of the host ...
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Why can't software capture PCIE packets?
I found this question in Stackoverflow and the answers say:
I don't believe so -- from a software viewpoint, PCI-E is quite well
disguised to look like (fast) PCI.
As far as I know, nearly the only ...
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Why is MSI and MSI-X enabling at the same time prohibited?
The PCIe spec says that only one of MSI or MSI-X can be enabled. Else system behavior is undefined. What is the reason behind this? What is the problem if both are enabled for a PCIe function? ...
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PCIe Domain, Bus, Device, Function limits
I am new to PCIe. I would like to understand 256 (bus), 32 (device), 8 (function). I am trying to visualise these PCIe slots on a motherboard. I am used to desktop motherboards where we have one ...
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What is the effect of disabling the scrambling on PCIe link stability?
In PCIe base specification document, it is mentioned that
Disabling scrambling is intended to help simplify test and debug equipment...
I am implementing my own custom gen2 PCIe IP in Verilog and I ...
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Problems in understanding PCIe blocks in Xilinx Vivado for Versal devices
AR 1215986 was mentioned on page 7 of PG344, Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide.
In this AR, the author mentioned several components, namely:
PCIe PHY
GT QUAD
...
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Can a PCIe Bridge connect to multiple downstream devices using different functions?
My understanding of PCIe bridges is as follows:
A PCIe bridge appears as 1 device on the upstream bus, creates a new bus downstream of it, and whatever connects to the downstream side will appear as ...
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Xilinx PCIe Integrated Endpoint - Using the other transceiver on the tile
This question is specifically about the Spartan 6-75LXT (FG676) but can be applied to any Spartan 6 (and possibly other Xilinx parts as well).
When using the GTP wizard by itself, there are 2 pairs ...
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The detail of External PCIe cabling specification?
As searching on the Internet, I found that the PCI group has released the "PCIe External cabling specifications". But I can not download the document because I am not a member of the PCI ...
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PCIe Bit Lock in LTSSM Polling.Active
My understand of PCIe bit lock which is for Tx and Rx sync the clock and lock PLL clock at Rx side to latch data correctly. But how does it do it? Any protocol flow needed for bit lock to work?
Thanks!...
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How to interface two Raspberry Pi CM4 modules and a SOM CN9130 module
I am working on project that requires two Raspberry Pi CM4 modules and a SOM CN9130 module to communicate each other with a data speed of 1GBPS.
Both modules have Ethernet and support the PCIe bus.
...
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Does PCIe hotplug actually work in practice?
I've got into a discussion in the comments of https://security.stackexchange.com/questions/109199/is-physical-security-less-important-now-for-securing-a-server?noredirect=1#comment194327_109199
The ...
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Is it bad to load one rail of a power supply vastly more than the other?
I am trying to modify a Delta DPS-400AB-17 server 1U power supply to support a desktop motherboard and graphics card. The power supply has an 8 pin 12V EPS connector attached to a 21A 12V (252W) rail. ...
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Connecting 1.8V USB and PCIe to 3.3V system
I'm working with a google coral module (ASIC) that has both PCIe gen2 1x and USB 2.0. From the datasheet (https://coral.ai/docs/module/datasheet/) the I/O levels are 1.8V maximum. The problem then ...
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PCIe hotplug hardware schematics reference design
I was going through this link, this was very wonderful
Does PCIe hotplug actually work in practice?
Following the above link, I had a question below:
I am looking for a "PCIe hotplug hardware ...
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What is the name / Part Number for PCIE 6+2 Power Connectors (Specifically the +2 connector without a retention clip)
This is the part I'm trying to find:
I can find the 6 pin connector (I think), but I can't seem to find the +2 pin connector. I'm attempting to make some cable assemblies for a weird but fun project ...
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Can someone explain to me why the math for PCIe bandwidth doesn't add up?
Since PCIe g1 x1 is based off PCI 32/66 bandwidth of 2133.33 Mb (...
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PCIe connector overhang
There are precise mechanical requirements for PCIe cards. Along the top edge, there's a 1mm strip where copper and components are not allowed. If you're designing a PCIe card, and have connectors and ...
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PCIe Clock Buffer Daisy Chain
I have a PCIe clock buffer with 4 outputs that I would like to use for more than 4 PCIe devices. My question is can I daisy chain the buffers such that one buffer output is the input to the next ...
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Do extra PCIe lanes improve latency?
If you connect a NVME SSD to a PCIe x4 slot it will have a higher maximum bandwith than if you connect it to a 1x or 2x slot. So logically it will transfer large files faster.
But if you never need ...
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Why does PCIe still hold on to 'transfers/second' instead of bits/second or symbols/second?
I think it is kinda all covered in the title. To my (incomplete) knowledge, PCIe is the only modern bus that still expresses its rate in transfers per second. Is there, apart from 'tradition' any ...
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What is the typical NVME SSD abrubt shutdown reaction time for a CC.SHN event until power loss?
The NVME standard under "7.6.2 Shutdown" defines the procedure for an abrupt shutdown event:
...
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Are PCIe and USB 3.0 the same interface?
I know the title may sound provocative, but I was looking for a PCI hub, and found solutions like these:
I noticed that on the PCIe side, there is actually only one adapter (which looks passive) with ...
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Can I avoid blind vias in this PCI-E gold finger fanout?
I'm planning a PCB project with PCI-E connector. After looking at some docs about PCI-E, I found one problem regarding the fanout the PCI-E gold fingers, the X16 pinout defines as below (part of whole ...
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PCIe mode in chip-to-chip communication
In my understanding, the most common PCIe usage is in computer systems which involves a processor host communicating with various endpoints through the PCIe tree topology. In this scenario, we will ...
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M2 Key E - can it host an NVMe SSD?
I found an SBC which has an M2 socket for WiFi cards. It's keying is E.
I couldn't decide whether I can plug an M2 NVMe SSD into this socket.
Key E normally has PCIe x2, which is not as fast as PCIe ...
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What does "configuration" refer to in PCI and PCIe? How is this different from "Enumeration"
I am not being able to find a clear description of what configuration means in PCI and PCIe. I have found something called as configuration space, but without knowing what configuration means, it is ...
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OCULink connector pin configuration for Root port and endpoint
We are using an OCUlink connector for the PCIe x4 interface in one of our new design which should support both root port and endpoint. We have a few queries to clarify on the same.
When our board is ...
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PCIe Data Transfer Rate vs Fundamental Frequency
The PCIe Gen 3 standard states that the link works at 8GT/s, while the fundamental frequency of the LVDS signals is maximum 4GHz. To my understanding PCIe doesn't use any sort of DDR technology, so ...
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Phase 2 equalization for downstream port in PCIe
Could you please clarify the following?
In phase 2 equalization, upstream port evaluates downstream port transmitter. In these process first upstream port sends preset values to down stream port. Then ...
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Can two PCIe endpoints communicate with each other through PCIe switch?
Figure shows basic architecture of PCIe. From what I understood, Root complex block will convert data into PCIe format. That means PCIe endpoint to endpoint communication will happens through Root ...
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PCIe Gen4: inter-pair skew: any limits?
For PCIe (and more particularly PCIe Gen 4), is there any recommendation on the maximum inter-pair skew, i.e. the maximum time/length difference between either:
2 TX differential pairs (of different ...
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3.3V in PCIe connector
What is the 3.3V used for in PCIe edge connect?
I have a PCIe connector that has 3.3V and another one that does not have the 3.3V and both are working fine which brings me to wonder why the 3.3V is ...
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PCIe "RefClk" impedance requirements?
I'm designing a very heavy impedance-requiremented PCB, with PCIe v2.
I know TX and RX diffpairs have strict differential ...
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Impedance-critical diff-pair routing
I need to route PCIe RX and TX diffpairs:
I can't change the bottom connector (fits into M.2 KeyE socket), neither the top (M.2 KeyM socket).
Normally, how shall I wire these diffpairs?
It seems I ...
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Frequency of PCIe differential pairs (RX, TX, CLOCK)
I'm planning to design a board for PCIe (v2).
For all impedance matching considerations, there is rule-of-thumb: if you can decrease the trace lengths below 1/10 of the wavelength, you're probably ...
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Designing M.2 socket for SSD
I'm designing a card adaptor which converts from M.2 Key E type to M.2 Key M type (to insert an NVMe SSD into a port designed originally for Wifi cards).
I found some reference design for the M.2 KeyM ...
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Why does PCIe hotplug capability require hardware support?
As far as I understand, hot-plugging a PCIe connection requires both hardware and software support.
Software-wise, it makes sense, since the OS has to re-scan the bus, and by default it doesn't do ...
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PCIe Present pin working principle
I have a doubt about the PCIe present pin working principle, As shown in the below image which is taken from PCI_Express_CEM_r3.0 Specification, How the Hot-plug control logic will detect the PCIe ...
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Is PCIe IO address space meaningless for ARM-based system?
According to here, the PCI Express TLP (Transaction Layer Packet) can target 4 different address spaces.
My question is about the IO and memory address spaces.
As we know, the PCI specification was ...
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PCI Express Lane Reversal for REFCLK
PCI Express supports lane reversal for the lanes.
Can REFCLK+ and REFCLK- also be swapped? That is, connect REFCLK+ from one device to REFCLK- on the other?
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Reverse PCIe bifurcation possible (two x4 into one x8)? [closed]
I'm just curious if this is possible in real world applications and if it is, what is it called? Reverse PCIe bifurcation?
Context: We know an example of PCIe bifurcation is converting an x8 into two ...
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Performance difference when comparing PCIe DMA vs. MMIO for same data access size
Some PCIe devices can map their own device memory region fully to contiguous host physical memory address space through a feature called PCIe Resizable BAR (base address register), which makes it ...
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Generic name for Molex(tm) Mini-Fit Jr(tm)? Standard definition?
The PC industry uses a large variety of power connectors which were originally introduced by Molex, using their trademarked (and search-engine unfriendly) brand name "Molex Mini-Fit Jr". This started ...
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Multiple PCIe devices in a single M.2 slot
I have a M.2 M-keyed slot on my laptop, and multiple M.2 PCI-e devices that I'd like to use at the same time. I've been looking for a M.2 switch or splitter of sorts but couldn't find anything, so I ...
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Trying to replace laptop's dGPU with eGPU. Is it possible?
I try to replace GT 840 dPGU with eGPU on V3-572PG mainboard for which I have circuit and boardview.
I'd desoldered dGPU. Then after study of boardview I could easy match pins from dGPU socket to pins ...
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What are these PCIe connectors that are slightly larger than SFF-8653 8i?
I have some computer motherboards that ware evidently a special-order for the ASRock Rack because the vendor does not have the model listed on their website, and when I contacted them they said they ...
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PCIe bus bandwidth
Calculate the bandwidth of a PCIe link with 8 lanes, 8b/10b encoding and 2.5 GHz frequency.
I tried the following formula but I am not sure of its correctness:
BW = lane data rate × encoding × no. of ...
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