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2
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1answer
50 views

RMII MAC side routing and signal integrity

I have some signal integrity and EMC questions. In my board LPC1768 RMII interface is connected to LAN8720. Because of pin locations some RMII signals must go through bottom layer. This is a four ...
1
vote
0answers
50 views

Wake On LAN to PMIC

I'm a connecting a WOL interrupt port of the PHY (an open drain port) to the ON-OFF port of the PMIC of my device. The idea is do a reset of the PMIC and then I'm going to turn on the MCU from a ...
2
votes
2answers
123 views

Problem with Ethernet PHY

One of my clients is experiencing problems with a SMSC LAN8710A PHY that is connected to a Xilinx FPGA. The Ethernet link works perfectly when the board is connected to my MacBook or to my office ...
0
votes
1answer
58 views

Vitesse VSC8221 Ethernet PHY for Media Converter Application

I'm currently designing a media converter board using Vitesse VSC8221. Just as an FYI, the documents for this product are all available at the product page. No NDA is required. When I say media ...
0
votes
0answers
113 views

How to config LAN8710A with PHY by STM32F4x7

I am using STM32F407ZGT6. FreeRTOS is running perfectly on board! I have included Ethernet files. According compilation of Windows Commander stating that it was compiled lacked free. But if one ...
0
votes
1answer
244 views

Media Independent Interface (MII) vs Media Dependent Interface (MDI)

Is my understanding about Ethernet - MII & MDI correct? MII - Media Independent Interface is about the connectivity between MAC and PHY. In other words, it is about TXD and RXD signals from MAC ...
5
votes
1answer
220 views

What ferrite for Ethernet Phy?

I'm using a Micrel KSZ8051 Phy in a 100mbps design. The datasheet specifies that it should have a small ferrite bead feeding the power. However, the datasheet doesn't suggest any specifications for ...
1
vote
2answers
270 views

KSZ8863RLL and external PHY (KSZ8051RNL)

I'm designing an Ethernet switch with KSZ8863RLL. It's a 3-way switch but only has 2 integrated PHYs and for the 3rd port it has an RMII interface. Datasheet says that the 3rd port can work in 'MII ...
1
vote
0answers
72 views

PHYs, Protocol Stacks and MACs, where can I find a simple good tutorial that uses a simple protocol to teach these concepts

With modern communication standards like USB, Ethernet, PCIe there is a lot of complexity involved as data is recieved/transmitted. I want to understand the concepts of PHY; Protocol Stack that ...
2
votes
2answers
103 views

An ethernet PHY chip speed support

I found ENC28J60 Ethernet PHY chip. The specifications say that the Physical Network Type is '10BASE-T' on the one hand, but on the other hand the data rate is ...
3
votes
2answers
192 views

Why is AC coupling needed between PHY and Fiber transceiver?

I'm using the DP83620 with the AFBR-5803 Avago transceiver. This question is not specific to these parts, but I'm including them for the sake of clarity. The datasheets for both devices indicates ...
7
votes
2answers
1k views

Schematic Critique: Phy interface with RJ45/Magnetics

I'm working on my first major schematic design and would really appreciate some feedback on the analog side of the 1000BASE-T Ethernet interface. I'm mostly concerned about the analog line termination ...
1
vote
1answer
454 views

RC pulldown on the MDI lines between the ethernet PHY and RJ45 Connector

I came across this circuit as part of the Xilinx Spartan 6 601 evaluation kit board diagram: Left hand IC is an 88E1111 (incidentally, the datasheet of which is incredibly difficult to obtain), the ...
1
vote
1answer
155 views

Datasheet: What is a unit interval (UI) for a PMA?

This datasheet has a table (see Table 3-2) detailing latencies for the two parts of a 10GB Ethernet PHY, namely the PCS (Physical Coding Sublayer) and PMA (Physical Medium Attachment Sublayer). While ...
7
votes
3answers
819 views

Do all PHY Ethernet chips have a hard-coded MAC address?

For example, this TI PHY chip DP83630 has two MAC addresses that can be used as destination and source MAC addresses for PHY control frames. (page 72 and 94) Does this means all PHY chips will have ...
5
votes
2answers
2k views

Ethernet 100 ohm differential pair layout

I'm finishing off the layout of a board in Eagle which has a LAN8710A 100Mbps ethernet PHY on it. The SMSC documentation is really pretty good but I'm stuck on the important detail of how to do the ...
4
votes
2answers
191 views

Is there any restriction in the choice of Ethernet PHY, depending on the TCP/IP stack?

I am new on the forum and am currently working on a project to design an ethernet electronic board. I will have a microcontroller 32-bit with an external PHY. I wanted to know : depending on the ...
2
votes
1answer
397 views

USB “Serial” Transceivers (PHY)

I am currently trying to incorporate a Freescale i.mx53 into a design. It has three USB High Speed hosts; one has a built in transceiver, the other two do not (OTG is not part of this discussion). ...
6
votes
1answer
666 views

DP83848 (Ethernet PHY) 1-bit serial receive data in 10Base-T

Having trouble getting a National Semi DP83848J working in 10BASE-T mode. The link partner and local status register agree that the link is in 10Mbps full-duplex mode. However, instead of receiving ...
5
votes
3answers
5k views

Connection of center tap for Ethernet transformer

I'm trying to connect an RJ-45 jack with integrated magnetics (Belfuse L829-1X1T-91 datasheet) to an Ethernet PHY chip (Micrel KSZ8041TL datasheet). The TX+/-, RX+/-, and the LED pins are all easy ...