PLL is short for "Phase Locked Loop". A PLL is a circuit that is able to keep a local (voltage controlled) oscillator synchronized with an independent given signal frequency.
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What is the difference between a PLL and a DLL?
Phase Locked Loops (PLL's) and Delay Locked Loops (DLL) are used in various applications but there isn't yet a salient discussion of the key aspects of these circuits, how they operate, in what ...
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1answer
64 views
How do I buffer a high Frequency clock on a Spartan 6?
I am trying to create a high speed clock on my Spartan 6 Atlys Board. The onboard clonck is 100MHz. I am trying to use an on chip PLL to get a faster clock. I am using a the clocking wizard IP to ...
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3answers
66 views
Add a Tunable delay to a TTL pulse?
How can you add a tunable delay to a TTL pulse?
My understanding is that this is the job of a PPL. I am not sure if a digital PLL delays a square wave or if it can also delay a single rising edge ...
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3answers
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Phase locked Loop in Demodulation
Can someone please clarify how a PLL works and how it can the result is used to deduce phase?
My understanding is that a PLL is used to demodulate in situations when the demodulator knows the ...
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3answers
92 views
Working and simple applications of PLL [closed]
Recently I am studying about Phase Locked Loop. My professor said that it is an amazing device with a variety of application. I understood the basic working of a PLL. But I couldn't appreciate his ...
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4answers
88 views
sub-kilohertz channel spacing with PLL
So I'm trying to use one of Analog's evaluation board PLL circuits (ADF4350, here). I need to generate frequencies around 1 GHz, ideally in a +/- 250 MHz range, but in steps of < 1 KHz.
Using the ...
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3answers
196 views
How to reduce the clock jitter for an ADC?
I am building a SDR (Software defined radio) and I am trying to clock my 16 bit 130 MS/s ADC. At this speed, the jitter of the clock is very important and a bad jitter can reduce the SNR of my ADC a ...
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1answer
110 views
Possible to tap a PLL signal as a clock for multiple devices
We have an oscillator providing a clock signal for an MCU. It has oscillator in and out pins: XTAL-IN and XTAL-OUT.
We'd like to use the same clock signal as a digital clock input to another MCU. ...
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1answer
153 views
Creating a clock multiplier using a PLL
I understand that PLLs can be used to modify the phase of a clock signal for various purposes. I have also heard that PLLs are often used to multiply clocks.
How can a PLL be used to multiply a ...
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1answer
149 views
Change in PLL settling time as a result of halving charge pump current/doubling loop filter capacitor
I have a PLL that is operating unstably at some temperatures. I have been able to show that reducing the charge pump current from 128uA to 64uA ensures that the PLL will operate stably at the same ...
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384 views
PLL - why compare phases not frequencies
I have a question about PLL's. The aim of PLL is to get two signals with the same frequencies (there can be a shift in phases, as I understand). So, in this case, why do you use a phase detector to ...
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2answers
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Clarification on what the max freq of PIC24FJ64 is?
I'm confusing myself a bit here. The following is taken from this datasheet:
High-Performance CPU:
Modified Harvard Architecture
Up to 16 MIPS Operation @ 32 MHz
Now I want 16 MIPS, which is its ...
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1answer
304 views
Generate a 4.25 GHz using 50 MHz crystal/oscillator and PLL
I want to generate a 4.25 GHz using a PLL and 50 MHz crystal/oscillator.
I am confused as to what I need to look for in a PLL. In a integer-N PLL, the prescalers are 16/17, 32/33, 64/65, etc. So, my ...
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1answer
358 views
How to generate a high-frequency clock?
I want to generate a high frequency (4.25 GHz) clock for a high frequency communication circuit. So, my question is:
What are the alternate ways of generating the high frequency clock and which would ...
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1answer
949 views
How do I produce a linearly chirp signal in spice?
I want to produce a chirp signal to test my PLL and found out the lock range.
There is the PWL and ...
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2answers
198 views
Linearized phase domain model of a PLL - what does a ratio of input phase over output phase mean?
I am trying to design a PLL and want to test it first in Matlab.
I have seen that the phase of the input and output are linearized, but I don't understand what is defined by the input/output phase.
...
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3answers
150 views
PLL versus putt-putt-skip, putt-putt-wait, fractional-rate division, or other approaches
Many applications use PLL's to generate frequencies where long-term frequency accuracy is necessary, but where a certain amount of short-term jitter might be acceptable. I've seen a number of devices ...
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2answers
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Injection locked frequency dividers
I am beginning to design a monolithic frequency synthesizer (around 2.4GHz) in which I need the maximum of spectral purity. I was looking at injection locked frequency dividers (ILFDs) for use as a ...
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1answer
2k views
How does a PLL inside a FPGA work?
I have used Altera FPGAs from last year and I would like to know how the PLLs inside works.
Mainly, really have any kind of analog circuitry inside in order to measure phase-offset between VCO and ...
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3answers
613 views
How can I generate a frequency of 5 GHZ with a crystal
How can I generate a frequency of 5 GHZ with a crystal
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2answers
262 views
Why do frequency synthesizers often use N/N+1 prescalers?
Frequency synthesizers, like Analog's ADF411x often have prescalers in their PLL which divide by 16/17, 32/33 or 64/65? What's the 2^N+1 value used for?
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1answer
621 views
All Digital Phase Lock Loop
I'm looking to implement a phase lock in an FPGA without using any external components (other than the ADC). For simplicity locking to a simple binary pulse is adequate. The frequency of the signals ...
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5answers
562 views
PLL usage in DIY hobby project [closed]
I was wondering if anybody was using PLL (Phase Locked Loop) in DIY hobby project? If yes what was the application? Did you made it from discrete components (as opposed from one placed in uController ...
