Programmable digital logic devices include FPGAs, CPLDs, and older devices such as GALs and PALs. Programmable logic enables flexibly implementing complex digital functions in a single chip, from a few gates of glue logic to entire microprocessors or complex signal processing systems.
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Why does CPLD has four clock sources?
Altera CPLD EPM570 series have four global clocks(GCLK0-GCLK3)，I want to assign two clock sources to CPLD: one from oscillator and one from a MCU. From "GLOBAL SIGNAL" part of "MAX II Architecture"MAX ...
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42 views
what are the things to keep in mind when interfacing two digital devices?
what are the things to keep in mind when interfacing two digital devices, e.g FPGA with a dual shock controller or CPLD with a PS/2 Mouse, Microcontroller with an FPGA, FPGA with an external RAM.
One ...
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1answer
80 views
microcontroller for heart rate meter [closed]
I have pulse meter which gives only filtered signal. I think it's form doesn't need explanations (periodic beats).
I need some microcontroller 3-5V, which would switch scheme (sensor) on, collect ...
4
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2answers
137 views
Trouble with VGA Controller on CPLD
What I am attempting to do is create a VGA controller from a Lattice MachXO CPLD in Verilog.
The Problem
I am attempting to display the color red with a resolution of 640x480 @ 60Hz using a 25.175 ...
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4answers
191 views
uC platforms to consider for faster CPU and 30+ GPIO pins
I am building a Persistence of Vision project with 120 RGB leds (=360 total lines to be controlled). We have settled on the TLC5940 for driving the LEDs (and could be open to changing this), however, ...
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1answer
100 views
Programmable Logic Controller
I have 4 DC powered electro magnets which I am currently running at 16 Volts @ 5 amps using a variable DC power supply. I want to build a programmable controller that would allow me to control the ...
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2answers
130 views
Need Quartis II CPLD tutorial for learning VHDL from ZERO [closed]
I am learning VHDL from zero using Altera CPLD. Already got Quartis II 12.1 and a 15-lines example VHDL (like Hello World for C learner).
To avoid learning bad coding style or digging too deep too ...
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2answers
265 views
Learn CPLD from zero [closed]
a) Should I learn VHDL or Verilog? Is one excel in some area while the other better fit another area?
For simple "glue logic", says, 5 to 30 TTL chips equivalant, which is better?
b) First ...
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1answer
119 views
Why is ISE / XLS is mapping a signal to the global clock GCK0?
I've synthesized a design for a Coolrunner II CPLD. I intend to use the CPLD's internal clock. I have an input named CLK. I look at the fitter report and I see this:
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6
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2answers
234 views
Why does this Verilog hog down 30 macrocells and hundreds of product terms?
I have a project that's consuming 34 of a Xilinx Coolrunner II's macrocells. I noticed I had an error and tracked it down to this:
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4
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1answer
130 views
CAN controller in a CPLD
As I cannot manage to find it done on internet, I wonder if it is possible to program a CAN controller in a CPLD ? It's look like it is going to require a least an FPGA.
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153 views
The best tool for PLC programming Mitsubishi Fx series [closed]
i am newbew in the electrical engineering, yet i have done my BS in software engineering, I want to programeladder logic for mitsubishi Fx PLC controllers, I have win7 in the computer and the setups ...
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2answers
146 views
Alternate programming software to program Altera CPLD
I am using a Altera MAX V CPLD. When I try to program the CPLD using QUARTUS II, it is reading the device ID and silicon ID correctly, but it failing during verification.
I tried to isolate the ...
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3answers
180 views
CPLD best practice for resetting a counter
My application has a bog-standard count-until-a-certain-number-then-reset-the-counter section. My experienced friend tells me that when using actual chips, it's common to increment the counter on the ...
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1answer
99 views
Why does changing an 'add' to a logical or devour 7 CPLD macrocells?
I have a design that's synthesizing to about 50 macrocells.
I have this section of code:
...
4
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1answer
150 views
Verilog - A line stays high, I need it to go low after a while
I'm working on a circuit in Verilog to be implemented on a CPLD. The output of the circuit will drive a stepper motor. The input is a stream of pulses from a machine.
I generate a stepper pulse ...
3
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1answer
177 views
Xilinx CPLD macrocell capacity
I'm a beginner who's become interested in Xilinx CPLDs. I get what CPLDs do, but I have no feel for the quantity of logic a macrocell can support or the sorts of situations where macrocells become ...
3
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1answer
148 views
Custom-CPU builder/simulator
I googled deeply but couldn't find any cpu constructor simulator.
I'm specifically hoping to learn about the operation of the northbridge, but When I googled "bridge simulator" or "bridge (the ...
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1answer
485 views
What is the difference between a GAL and a PAL?
I was reading this article (unfortunately a lengthy Dutch discussion) talking about a GAL. I have come across the GAL device before, but never really understood what a Generic Array Logic is. I know ...
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2answers
736 views
adc-fpga interface guidelines for vhdl
I want to interface 3 separate ADS8548 ADC with XC3S200AN fpga. The fpga masters the control lines of the ADCs and it also acquires the digital data from the ADCs through parallel bus.
I will have ...
2
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2answers
266 views
Arduino to CPLD to toggle an LEDs using I2C
I have a a CPLD (Lattice MachXO2) that echos a signal from an Arduino to turn on an LED.
Arduino:
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2answers
579 views
What happens when an FPGA is powered on and left unconfigured?
I am trying to get a general understanding on what happens if you leave an FPGA unprogrammed for a long duration of time.
Suppose you have an FPGA and you leave it unprogrammed for a long period of ...
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1answer
260 views
Programming Xilinx XC9572
Can I read and save the program from a Xilinx XC9572 and burn it to another blank DC9572? I have a Needhams EMP30 which has this device on its list. I need the adapter for the PLCC 44 pin to DIP. But ...
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3answers
282 views
How does CPLD propagation delay work?
My question is about CPLDs in general, but take for example this cheap Xilinx one.
I understand that unlike a microcontroller, a CPLD does not have a clock; external edges activate the logic ...
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1answer
152 views
Schneider EGX100 Gateway with AB PLC 5 series
I was investigating hooking up Modbus devices to an AllenBradley PLC 5/40E using a Schneider Electric EGX100 Ethernet gateway.
I can access the web server on the gateway device and monitor the slave ...
3
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5answers
512 views
Wrong outputs in VHDL entity
I have lessons about VHDL in one of my university class and I have to write simple entity which will generate clock from 1MHz source. I'm using CoolRunner-II CPLD ...
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2answers
138 views
Export restrictions on programming equipment
I have a friend that works for an overseas manufacturer. He sells programming equipment to companies that have products with multiple Programmable Controllers embedded. I raised the subject of "export ...
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3answers
458 views
Is this a good use of a CPLD?
I am trying to generate some waveforms which are phase shifted from an input signal.
The input signal is around 4.4 MHz and is a square wave at 50% duty. I need a 0 degree and 90 degree phase shift ...
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1answer
179 views
COM differences between input and output in PLC
See below for a wiring diagram of the I/O of a PLC (model: Omron CP1L).
Input:
Output:
What does the input side has many input but only one COM, but on the output side there are more COM ...
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1answer
280 views
How to wire the output of a PLC
I have question regarding the wiring of the output of PLC (mode: Omron CP1L). Below is the output wiring diagram.
The PLC is AC powered, and input are 24 VDC. As the image shows, the output has a ...
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4answers
1k views
Are there any Analog FPGAs?
As I understand it FPGAs are flexible "digital" circuits, that let you design and build and rebuild a digital circuit.
It might sound naive or silly but I was wondering if there are FPGAs or other ...
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1answer
403 views
What was the protocol for programming GAL devices?
What actually has to happen, at a pins and signals level, to program a GAL device? Let's say I have a GAL 22V10, and a .JED file with the desired fuse pattern. The usual way to proceed is to drop the ...
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3answers
321 views
Modular PCB Design
I'm designing a basic harness continuity checker based on shift registers implemented in Max V CPLDs. I'm aiming for a modular/extendable PCB design for the project as it has several benefits (cost, ...
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1answer
230 views
Logic Buffers for CPLDs Outputs (and Inputs?)
Today, I tried to use a ULN2003a darlington array as a buffer for my CPLD's outputs. While it works well, I have a concern. The max. voltage where the Max V is guaranteed to read a low is 0.8V. The ...
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3answers
348 views
How can I increase the number of hardware UARTs in a design with a single UART MCU?
I am using a TI CC430 MCU because it contains an embedded CC1101 radio frontend. I would really like to stick with this MCU. However, I need to simultaneously interact with a separate serial radio, a ...
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1answer
186 views
Increasing current capability of a Pin
This is a followup from my previous question.
Here's a summary of how the circuit works:
I'm designing a circuit that can test for short circuits and open circuits in a wiring harness. The wiring ...
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3answers
182 views
Bus Contention - Output Pin driving another Output Pin
I've run into an unusual problem. I'll start off by describing my goal: I'm designing a circuit that can test for short circuits and open circuits in a wiring harness. The wiring harness does not have ...
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4answers
488 views
What software I can use for CPLD programming?
I would like to learn more about CPLD circuits (because they are cheaper than FPGA), but I am facing a major problem. I cannot find any simple and userfriendly software for programing and debugging ...
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1answer
169 views
Any nice way to use unbonded CPLD pins as registers
Many CPLD product families offer each chip in multiple packages, some of which don't bond all I/O pads out to pins. Even I/O pads which aren't bonded to pins, however, may be useful if they have ...
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1answer
628 views
Strange bug when Interfacing with Shift Register (CPLD) via SPI
I've implemented a 8-bit Parallel in Serial Out (PISO) Shift register in VHDL on my Max V CPLD. I'm using SPI to interface with the CPLD using my AVR. The circuit works but only partially. Suppose I ...
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2answers
652 views
When is a FPGA preferred instead of a CPLD, and vice versa?
I am starting out with programmable logic, and I am mostly using schematic entry. (Hey, I like to see the schematic instead of VHDL/VERILOG :P)
I have been using a Xilinx CPLD originally that had 128 ...
3
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3answers
375 views
FPGAs or CPLDs for “Glue Logic” and Video/LCD Capabilities
Some of you may remember I posted a question in which it was suggested that I use CPLDs instead of a large number of multiplexers. Here is the question, for reference.
However, as I read and learn ...
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2answers
431 views
Getting Started with Altera CPLDs
I'm looking for recommendations regarding development kits for Altera CPLD prototyping but I'm afraid I'm not sure what to look for. The budget isn't too much - around $200. While I'm leaning towards ...
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1answer
276 views
Pull-down's on CPLD
So I have a Xilinx CoolRunner II CPLD that I'm working with that is talking to conditionally powered peripherals. I'm using the CPLD as a kind of logic level translator between a microcontroller and ...
0
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1answer
333 views
Video signal attenuation
Which is the best way to attenuate a video signal?
I need to reduce the Vpp (Peak-to-Peak Voltage) from 2V of a PAL video signal to 0.75V. I am familiar with filters and amplifiers (like Op-Amp ...
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7answers
548 views
Any programmable devices available for more modern languages?
Pardon my naïveté, but it seems like most programmable devices (FPGAs, PLCs, PICs, etc.) are programmable using the C or C++ languages, or a variant of one of these. Are there any devices out there ...
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578 views
What are my less expensive options for getting started with CPLDs
I would like to goof around with some CPLD stuff and I see I have a couple options out there. I don't have a particular application in mind; it just seems like there a lot of possibilities, some of ...
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2answers
264 views
Image processing on PAL/NTSC
I want to process a PAL or NTSC video signal and pick up colors, like green, orange, blue and red. Is there any way to decode RGB from NTSC/PAL easily, and then detect these colours? I'm looking for a ...
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2answers
658 views
How many transistors/logic gates are used in the signal path between a TV studio and the restitution of the image on my HD-TV?
How many transistors/logic gates are used in the signal path between a TV studio and the restitution of the image on my HD-TV ?
You see what I mean ? I need a rough estimation...:-)
I especially ...
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1answer
106 views
Is it standard for a VSD to pull its power from the controlling PLC? Is this the better solution?
We have an industrial floor that is opened and closed by a variable speed drive motor. This is controlled by a PLC device. Recently we had to do maintenance on the VSD. The serviceman incorrectly ...
