A special, high-speed storage area within the CPU.

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1answer
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What does banking mean when applied to registers?

This answer to a question on StackOverflow about what banking means in the context of ARM's banked registers indicates that there is some confusion about the meaning of banking when applied to ...
7
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3answers
2k views

Do AVR registers and ports need to be initialized to zero?

During the initialization routine of my code I use to do such things as: clr r0 ; will always stay zero and: ...
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5answers
492 views

stack cache instead of registers

Is there a processor that do arithmetic operations on a stack and not on registers? To keep performance, of course, that processor should cache top block of a stack in the same type of memory that is ...
6
votes
2answers
4k views

What actually is a shadow register?

I noticed the term Shadow Register while going through a datasheet of a TMS320F28335 DSP. What does it actually mean? Does it have a physical location in the CPU as ...
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votes
9answers
2k views

Microprocessors/Microcontrollers - Do registers have addresses?

My Embedded Systems professor keeps referring to the memory locations of registers as their respective "addresses". I'm confused by this; I was always under the impression that in any microprocessor, ...
5
votes
1answer
362 views

One-clock increment operation in a three-bus CPU architecture

In his chapter on CPU design, Edward Bosworth introduces the following three-bus architecture: One of the main design aims of this circuit is to be able to increment the program counter PC in a ...
5
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3answers
652 views

Clocked edge-triggered timing (contamination delay)

I'm reading a book about computer architecture, and it says that, in clocked edge-triggered devices, the contamination delay is usually nonzero, and that the contamination delay for registers is ...
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votes
3answers
1k views

What is the main difference between registers, bit fields, and flags?

In school I was accustomed to programming various registers when working with microcontrollers to manipulate their behavior. At my job registers are now referred to purely as bit fields. The word ...
4
votes
2answers
249 views

Problem in writing register maps using C structure for a TI Microcontroller

I am writing register maps in C for a TI ARM based Micro-controller board. Here is the link to the datasheet. I am using the following guidelines on how Register maps should be written in C: ...
4
votes
2answers
1k views

How can a shift register be used to debounce a switch?

This is the problem: This is the proposed solution: What I don't understand: The button bounces in the setup/hold time of the input of the circuit, making the FF go into a metastable state ...
3
votes
2answers
158 views

Is it possible to exchange the content of two registers in a single clock pulse?

There are two register R1 and R2. How is it possible to exchange the content of R1 and R2 in a single clock pulse using Common bus architecture?
3
votes
3answers
364 views

What is the mechanism behind RO or WO and WR registers?

In embedded systems you have read only and write only registers. How are the two type distinguished in the netlist? I can not understand how one build a flop which you can only write and not read ...
3
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1answer
694 views

Converting AVR assembly to machine code - addressing registers?

In AVR Assembly - I want to work out the machine code representation of the following: ANDI r18,$10 I know the opcode for ANDI is ...
3
votes
2answers
3k views

How do I select what values to load in CCPR1L register (for generating PWM signal with PIC)?

I need to generate PWM signal with PIC18F2550 microcontroller at near 20kHz. I read the datasheet, I found it too complex and confusing, then I started to search for a sample code on the net to ...
3
votes
2answers
198 views

Confusion between register size, address size, data size

I started learning about pointers in C++ and I figured I should educate myself a bit on how memory works and is accessed. I read that when we say a processor is 64-bit, it has a 64-bit register and ...
3
votes
3answers
927 views

Can I pass a bit register as a function argument in Hi-Tech C compiler for PIC16?

Is there a way to pass a bit from a PIC's register as a function parameter? Taking, for example, the PIC16F887, its registers (SFRs) and individual bits are defined as fallows in the corresponding ...
3
votes
1answer
108 views

VHDL code and unintended latches

I am working on coding a Regsiter a1 with input signals b1,rst and wra1 the register ...
2
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1answer
357 views

MSP430 RAM protection

I'm looking at the user guide for the MSP430x5xx family. It says there in section 9.1 that: ...
2
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5answers
224 views

How does register type modifier work on different CPU architectures?

This question is to clarify my doubt against this register storage class. when a variable is register qualified ,compiler puts the variable in a cpu register other than RAM for ease of access. so ...
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2answers
487 views

What is the meaning of “Register.Rd”?

Reading Hennesy's book "Computer Organization and Design" it is mentioned "Register.Rd" and "Register.Rs" but what does it mean? The .Rd, .Rt and .Rs parts I can't understand, on page 365:
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votes
2answers
825 views

Setup Time, Hold Time - What is the underlying principle for having them?

I'm learning about setup time and hold time of a FF connected to a bus. But the textbook fails to explain exactly why are those needed in an operation. Isn't a FF always powered on and attentive to ...
2
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2answers
614 views

Verilog asynchronous reads of regs - and design question

I'm trying to understand what the following bit of behavioral code, what kind of hardware it turns into: ...
2
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3answers
766 views

Understanding Flip Flops/Registers in Low Level

So I'm reading "Elements of Computing Systems" trying to really understand how everything works underneath (Any other book/article suggestions that would help would be amazing) Since eventually I want ...
2
votes
2answers
599 views

early accumulator based machines

Wikipedia says that many of the early machines were accumulator-based machines. My guess is that in those machines the accumulator did not play the role of a speed-up register as do registers in today ...
2
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1answer
196 views

Eliminating Signal Race Hazard in an IC dynamic latch/register!

I work in MAGIC Integrated Circuit software at layout-level. I got an 8bit dynamic register made of 1bit dynamic flipflops that write input on the positive edge of the signal: (Note: I used ...
2
votes
2answers
4k views

What is the difference between TCCR1A and TCCR1B [closed]

I had an error in the configuration of PWM for the atmega8 because I didn't set my register properly. But I thought that Timer 1 is timer 1, no matter is TCCR1A or TCCR1B. Why can I set all the timer ...
2
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4answers
696 views

What is important in computer clocks' signal: signal edges or intervals when signal is stable? Will multiple value propagation occur?

I am trying to figure out some basics of digital electronics. We have all seen the squared graph of the computer clock signal: I have read multiple articles on the Internet and still can't figure ...
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2answers
855 views

How many servos can I run on an ATtiny85?

This is my first time asking a question on this website, so please correct me if I'm doing something wrong... I have been working on a small project which runs three Servo motors on an ATtiny85, ...
2
votes
2answers
83 views

Register Syntax question

I was reading some code to use an on an arduino ATMEGA328P and I can't figure out what this line of code does. ASSR &= ~(_BV(EXCLK) | _BV(AS2)); I know that ...
2
votes
2answers
222 views

What does register and bus size depend on?

So here is a hardware sequential multiplier depicted. Number A is 51 bits width, number B is 48 bits width. I have to choose the most efficient size of buses and registers (optimize according to ...
2
votes
1answer
1k views

Access Register/signal from Multiple Modules (Shared Memory)

I want to implement a data register to store up to 256 8 bit chunks (VHDL). I also need to to be able to access and modify these values from multiple vhdl modules. One module will access the register ...
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1answer
128 views

Clearing Flag Bits By Writing 1

Most of the interface devices have various flag bits (that can also raise interrupts if that functionality is provided) used to check the status of the device/operation. Usually they are cleared by ...
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1answer
109 views

AVR registers location

There are four types of registers in AVR. \$r_0\$ - \$r_{15}\$ witch used for CPU's calculations. \$r_{16}\$ - \$r_{31}\$ witch used for user's temporary data storage. Registers for I/O statements. ...
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2answers
510 views

How to design a left shift register

I want a circuit in which I get the following sequence: 0001, 0010, 0100, 1000, 0001 I know that it's 4-bit shift register. But what is my approach to design ...
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2answers
654 views

VHDL: How to double read a register bank?

We have been tasked with creating a register bank that can dual read, but only single write. At the moment I've got it all working apart from the dual read. Could someone point me in the right ...
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1answer
105 views

Signed to unsigned for registers

I have just started to program some code at the lower levels. I have been told to change any signed integers into unsigned integers and store these in the HW registers. I have done this OK but I am ...
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2answers
97 views

register without clk

I'm designing a small system in VHDL using the datapath and contorller method. Is it okay if I design registers that don't have a clock input (load data on the rising edge of the load signal) as they ...
1
vote
1answer
130 views

Data transfer between FFs in a CPU

I was in computer organization lecture and when we wrote what the CPU does during an add instruction (like micro instructions) something got me thinking. I didn't understand how we let one of the FFs ...
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vote
3answers
450 views

what happens when the carry bit is zero in addition/subtraction algo for hardware

This is the algorithm in flow diagram for addition and subtraction in computers. A(s) is the sign bit of A B(s) is the sign bit of B //(s) denotes the subscript E is the register that has a ...
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1answer
68 views

implementing direct addressing mode for a load instruction on a mips archtitecture

Given a Mips machine with 26 bit addresses and 32 bits data-paths, where the load instruction is as follows |OPT code|rs|rd|immediate| |6 bits |5 bits|5 bits|16 bits| The OPT code is the ...
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vote
1answer
42 views

Verilog only assigns first bit of a bus

I'm trying to assign a 12bit parallel bus to a 12bit register. I've reduced the problem to this literal assignment but as with the previous case, only the first bit is being written to anything when ...
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1answer
192 views

Trying to start i2c communication on dspic33fj128gp802, but I cannot write on the SEN bit of the I2CxCON register

Good evening, I was trying to start the communication with the I2C on my pic. I only set the bits in the control register in the code for now and the inizialization of both the pins and the PLL, and I ...
1
vote
1answer
228 views

Integrated Circuit Layout Design - Dynamic Flip Flop?

I need to create a dynamic flip flop like this: In integrated circuit technology, at mask layout level. I then want to create an 8bit register, using 8 of these flip flops, with a common CLK ...
1
vote
1answer
237 views

What is the purpose of CRC_IDR in STM32 processors?

The STM32's CRC calculation unit has a register named CRC_IDR. This 32 bit register allows the user to store 8bits of data. There seems to be no link between this register and rest of the CRC ...
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2answers
590 views

Lighting 128 LEDs from shift registers

My question is on lighting 128 LED's from shift registers. I had originally considered using a string of 16 74HC595's but upon further research, it appears they would not supply enough current to ...
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2answers
59 views

Writing MIPS assembly and machine code for instructions

I am continuing my practice with MIPS assembly and machine code. I am doing a problem that assumes the following: ...
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0answers
30 views

Does Core Debugging Interface reveal state of Context Registers?

I need to know whether the Context Register states of the CPU are relayed to a hardware component called the Core Debugging Interface, and if so, where I can find any useful information on this ...
0
votes
2answers
123 views

Why are bitfields in register not sequential?

Why are the bit-fields in the register not sequential? For example, consider an 8 bit register X . X will have bits 0-2 with flags and 3-6 may be reserved and bit 7 may again represent some flag. Why ...
0
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2answers
698 views

How to avoid input/output conflicts with a bus

How does a system bus work? I don't understand how can a circuit avoid input/output issues with a bus. I included an image to better explain my thinking. The circuit has 2 general purpose ...
0
votes
1answer
40 views

Capturing x86 register value changes in hardware i.e. at circuit level

I need to find a way of observing (on another 'monitor' machine) changes to registers critical to the address translation process on x86 platforms - including IDTR, GDTR, CR3, etc. This monitoring ...