Anything related to the rise time of a signal. The rise time is a parameter used to characterize abrupt transitions in a signal waveform. It is usually defined as the time needed by the signal to go from the 10% to the 90% of the level it attains at the end of the transition.

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33 views

Reverse biased photodiode gain resistor selection

I have a reverse biased photodiode as shown below. where R1 = 100kΩ. The output is quite low around 50mV. I would like to replace R1 with 1MΩ to get 10x the output. My concern is, if it will have ...
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3answers
55 views

When does an RC Transient period end?

I have struggled with this question and read many articles and watched youtube videos but to no avail. For this circuit the time constant or "Tau" is 80 micro Farads (or$$80*10^-6$$) My issue lies ...
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2answers
142 views

LTSPICE - How to create PWM with rise time

A simple PWM circuit is simple to create using LTSPICE, such as: ...
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1answer
55 views

CMOS Gate and Coupling Noise from Loose Wires

I am currently working on this small circuit which as you can see, has to level shift a 3.3v 1Hz PPS signal into a 5v pulse. Everything is marvelous when I measure the level shifted pulse with ...
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3answers
78 views

RF FETs - how exactly are they different from regular FETs?

I've browsed through DigiKey and there are these RF FETs. Are they for final stage amplification? Say you have an opamp that doesn't go for the final desired voltage, so one uses these FETs as Common ...
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0answers
84 views

Impedance discontinuity problem at transmission line?

I am confused about how the waveform will be to the left of discontinuity. Please help me understand it better. Here is my understanding: When the unit step hits the inductive discontinuity, at ...
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1answer
71 views

Computing Rise Time on SPI Bus

I am designing a circuit board that has an SPI bus with 32 slaves. I plan to drive the bus at 8 MHz. Another individual on this site commented on a previous post of mine that the total capacitance ...
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2answers
361 views

Why is CMOS fall time faster than rise time?

I've just started a computer architecture class, and the slides from a lecture says that the reason why fall time is faster than rise time is that the NMOS electrons have more mobility than PMOS which ...
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0answers
67 views

how to calculate the Rise delay of the inverter

how do I calculate the rise delay of the inverter using the "non linear delay model" cell library which has 0.3ns input fall transition time and 0.16pf output load. ? ...
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1answer
53 views

Two cables, same resistance, different lengths, speed of current transfer

If I have two cables, with different size, but in total the same resistance, what will be the speed of the current transfer( how much time will it take the voltage to appear at the end of the cable). ...
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0answers
31 views

Rise time degradation by connecting to an input buffer

Suppose I have an imaginary 1.8V lvcmos output buffer and I know from the datasheet that it has an unloaded 10-90 rise time of 1ns. Now I'm going to hook up 6" of trace, to an input buffer who has an ...
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2answers
104 views

How come you cannot determine the capacitance of a MOSFET gate based on the other supplied values on the datasheet?

Conjecture If it's the case that $$ Cg = {Qg \over Vg} $$ It must be the case that $$ (Ciss + Coss + Crss)Vg = Qgon $$ But it turns out that it is not. I don't understand what I'm missing. I ...
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83 views

Improve DAC Pulse Rise/Fall Time

I have an older NI DAQ (PCI-6251) which comes equip with a bunch of ADC's, two DAC's and a hand full of DIO ports. I need to output a pulse of variable width, amplitude and DC offset which the DAQ ...
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1answer
83 views

Balancing Rise and fall times at input and output in CMOS Design

How do I make sure that my rise and fall times are balanced between input and output in a CMOS design?
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1answer
252 views

How does the improved transistor astable multivibrator work?

This is an astable multivibrator circuit. Assuming that TR2 is initially on, the right pin of C2 is grounded and since C2 isn't charged, the left pin of it is also at 0V. Now, Out 2 is low. C2 is ...
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1answer
346 views

LTspice MOSFET width sweep

I am trying to simulate the transfer characteristics of a CMOS inverter using LTspice. I want to sweep the MOSFET width and length and observe the effects on rise and fall times of the CMOS inverter. ...
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3answers
253 views

Improve rise-time of NPN current mirror

I'm looking for a way to improve the rise-time of a current mirror. My problem is as follows: I want to interface with an obscure single wire protocol. I'm starting with a digital signal that has a ...
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1answer
125 views

Attiny84 has a slow rising and falling edges

I'm using an Attiny84 to generate 100us pulses for a totem pole gate driver. I was expecting rise and fall times in the order of 10's of nanoseconds, what I got was rise times of 7.8us (10% to 90%) ...
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2answers
276 views

Do LED and photodiode rise times matter for time-of-flight (TOF) measurement?

Do I need small rise times of an LED and a photodiode/APD when considering time-of-flight measurement? Given I know rise time of both diodes I am always able to count time of flight by subtracting ...
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1answer
74 views

Delayed VCC rise time with Parallax Smart Card Adapter

While implementing a T=0/1 protocol using a smart card reader I had obtained from Parallax, I noticed a behavior when applying power to the card. It seems that once the 3.3v VCC pin is brought high, ...
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1answer
158 views

Rise/fall time constrains for ADC?

Does the sampling clock rise/fall times for ADCs matter, or they can be virtually 0 seconds? Can they be slow? In particular, I could not find anything about rise/fall time constrains for AD9235. ...
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2answers
320 views

74HCT14 schmitt trigger doesn't improve rise/fall times

I have a square wave signal whose rise and fall times are too big to feed into another 74xx-series logic chip, such as the 74HC175 flip-flop, which requires rise and fall times in the nanosecond ...
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2answers
165 views

Square signal's rise time and frequency

simulate this circuit – Schematic created using CircuitLab I am analyzing work of amplitude limiter built on transistor, and I can see an incoherence as far as rising times for different ...
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2answers
146 views

Signal distribution, buffers, rise times and EMC

I am designing a DSP based audio mixer. There are 4 AD/DA converters (AD1939 and AD1974) and a DSP (OMAP L138), which is on a carrier module. I am distributing the frame clock (48kHz) and the bit ...
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1answer
167 views

Measuring the rise time of remote device

Given a radio transmitter (like a cell-phone or wireless computer), how can you measure the rise time remotely? I understand that you can use an oscilloscopes to measure it on components at hand, ...
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1answer
914 views

How to determine BJT switching time

Is there some standard way to get information about BJT (Bipolar Junction Transistor) rise and fall times (the high power ones) ? In essence a IGBT is a BJT being driven by a FET, so there should be ...
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1answer
1k views

Is this measured rise time inaccurate because of limited oscilloscope bandwidth?

I don't have an LCR meter and wanted to learn how to use a fast edge pulse generator and an oscilloscope to do capacitance measurements as an academic exercise. In W2AEW's videos, he builds a simple ...
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1answer
188 views

Confusion regarding considering a transmission line as lumped or distributed

I am just elaborating my question. I have came across different formula's to say whether a Transmission line is lumped or distributed. in one of the books i read " Effective length of a electrical ...
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1answer
386 views

Do long transmission lines degrade rise/fall times, and if so, by what mechanism?

I remember someone telling me long ago that if a voltage step is sent down a transmission line, the step will become smeared as it travels down the line, and the rise time will become degraded. I'm ...
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1answer
227 views

What are fast and slow decay timings in the Allegro A3201 low voltage meter?

In the A3901 Low Voltage Meter Driver datasheet Figure 8 on pg. 10 shown below indicates what the output "IOUT 2/3-4" will look like given input "IN1/3 or IN2/4". But Figure 8 does not mention ...
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2answers
398 views

Square wave generator has nigh-useless output

I have a system that was designed for testing digital components. I have a device in the system which is used for generation and acquisition of digital signals. Now, I will happily admit to not ...
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2answers
773 views

Building an oscillator out of discrete gates

I want to buid an ocsillator out of discrete XOR gates, I want to acheive 80MHz. I've tried building one from SN74LVC2G86, but rise/fall times I get is about 25ns. Datasheet does not specify the ...
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3answers
5k views

How is rise time related to bandwidth of the signal?

Say, I want to limit the rise time of my digital signal edges to avoid dealing with transmission line effects. How do I determine the maximum frequency of harmonics in my signal knowing that my rise ...