SDRAM stands for synchronous dynamic random access memory. Being synchronous it relies on a seperate clock signal for moving commands and data to/from the device.
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Do I have to equate clock and Data Bus propagation delay for Transmission Lines?
My question is about SDRAM timings for clock and DataBUS. Som designer advice that clock pin has to be the shortest one. Data Bus may be longer than these because of the some problems. But clock trace ...
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5answers
343 views
How can 8-bit processor support more than 256 bytes of RAM?
If a 32 bit processor can handle 4GB of RAM(aproximately), why do my arduino mega 2560 has 8kB of SRAM, if being a 8-bit processor allows it to handle just 256 bytes?, or am i reading this next page ...
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3answers
192 views
Interfacing with RAM from a PC, e.g. SDRAM / DDR, to a microcontroller
I'm looking into interfacing standard PC form-factor SDRAM or DDR sticks to a microcontroller, but I can't find any definitive details on how they work in terms of how the bus works. I guess it's ...
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85 views
What is lead-in termination?
This term is mentioned in the Micron Application Note: Hardware Tips for Point-to-Point System Design on page 10 (...For signals with lead-in termination...), however I've been struggling to find out ...
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2answers
402 views
Why not SRAM for FPGA in image processing?
I'm beginning with VHDL coding and I've done some basic image processing on my development board.
I've noticed that most FPGA development boards often use DRAM (SDRAM, DDRAM) as RAM.
For example, I'm ...
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97 views
SDRAM on opposite side of board with respect to uC
Just a quick question. Is it advised against to place a high speed memory device on the opposite side of the PCB with respect to the microcontroller? And if it is ill advised, how is it possible to ...
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1answer
106 views
Memory interface for video output
I am designing a system where a DSP (like the TMS320VC5501) processes some video data and outputs it to a PSP screen (the ones sold on sparkfun). The issue I'm having here is designing the video ...
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79 views
How do they integrate logic into a DRAM process while manufacturing SDRAM?
When SDRAM is manufactured, how do they integrate logic into the IC while they are using a DRAM process for fabrication?
Because SDRAM requires logic to decode its inputs, do the burst ordering, etc.
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SDRAM chip selection
I need to buffer 1.5Gb/s of video data through SDRAM, which works out to be 3Gb/s total in and out combined.
This is my thinking so far:
Write/read burst length is set to max (16 clock cycles), and ...
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2answers
70 views
Can a disconnected pin on DDR3 SDRAM go undetected?
I was testing some DDR3 SODIMM modules using Memtest86+ on a Lenovo Thinkpad T520. I re-tested a module that I previously marked faulty and it came out fine.
So I wonder if it's possible that the ...
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1answer
243 views
SDRAM initialization issue (Freescale iMX31)
I'm trying to modify an existing init sequence (low level init of SDRAM) to accommodate a change in hardware configuration: an existing SDRAM on my iMX31 was replaced with a different size, otherwise ...
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264 views
SDRAM advantages
As of RAM technologies (the basic ones) is concerned, I consider the initial classification (based on the storage) as
SRAM: The basic entity for storage (each cell) is the flip-flop (comprised of ...
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3answers
439 views
How does random memory access of RAM work?
HDD works in a partly sequential manner. However, RAM is known for random memory access, allowing equal speed of memory access for every location at every time.
So, what makes RAM so special? How ...
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84 views
Sampling 133MHz bus with OWLS Logic Analyser
The OWLS specs state that it can operate in two sampling modes:
200Msps captures up to 100MHz waveforms on 16 channels
100Msps captures up to 50MHz waveforms on 32 channels
Does this mean that ...
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2answers
898 views
Termination resistors: are they needed?
For a project I'm designing, I'm using an IS42s32800 (TSOP) SDRAM with an LPC1788 (QFP) microcontroller. On the PCB I have 4 layers with a ground plane right below the top signal layer and a VDD plane ...
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254 views
Memory (RAM) of computers after shut down
After computer shuts down, is it possible to retrieve data in RAM? I heard that police was able to do that... so I felt that was somehow weird..
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279 views
Freezing DRAM for forensics (coldboot)
I've known about the coldboot trick for a while, but have never really considered the physics behind it. I've read the paper, but it doesn't really cover why it works.
How does physically cooling a ...
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3answers
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What is pseudo-open-drain-logic?
DDR4 reportedly uses something called pseudo-open-drain-logic or PODL. How does it work?
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SDRAM Prototype vs Production Woes
I have a design using an LPC1788 together with a SDRAM module from ISSI (IS42S32800D). This is a 32bit interface.
I have routed this design out and had a prototype made with a PCB manufacturer that ...
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0answers
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Expand RAM and flash on LPC2294
I have a project in mind. I want to buy an LPC2294 microcontroller, SDRAM IC, and flash IC (those IC's haven't yet been defined). What I want to do is connect those ICs to the microcontroller in order ...
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1answer
307 views
What are these pull ups for on this SDRAM?
Apologies for all these questions about SDRAM, but I want to get this next board run right.
I have an LPC1788 processor with an external memory controller I am interfacing with SDRAM. There is no ...
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1answer
247 views
Interface Mobile SDRAM (1.8V) with 3.3V SDRAM controller
I am looking for a 256Mbit SDRAM module in BGA format, to buy in units of 1000. However the cost for these modules are extremely high for packages using a 32bit bus in standard 3.3V voltages, however ...
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3answers
939 views
SDRAM issue - LPC1788
I have been using an NXP LPC1788 dev board which I have developed my application on (.NET Microframework Cortex-M3 Port).
Everything was well and good on this board, I had no issues with RAM or ...
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1answer
390 views
Using SDRAM with a MC68000
I'm currently working on developing myself a computer based on the Motorola 68000 CPU and am currently working on the RAM interface. Since I want a basic multitasking OS, I want to use 1 MB of RAM. ...
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742 views
Expose SDRAM as a USB 3 mass storage device
Challenge:
Build a device that can host one or more SDRAMs (e.g DDR2, DDR3) and expose them as a USB 3 (slave) mass storage device.
Goal:
Allow a USB 3 host to mount the device and allow near ...
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5answers
674 views
The precise reason why DRAM is slower to write than to read?
I just want to make sure I have my facts straight.
In the olden days when I was a teenager and the Internet was unknown outside of academia, I recall learning (I wasn't taught this per se) that ...
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3answers
672 views
I know why DRAM is slower to write than to read, but why is the L1 & L2 cache RAM slower to write?
DRAM is slower to write than read because it takes time to either charge or discharge a DRAM memory cell. But what about the SRAM in my processor's L1 and L2 caches? It's slower to write as well but ...
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1answer
256 views
Do DDR2 chips and controllers have on-die termination?
I am going to try to interface a low-speed 8-bit DDR2 chip with an FPGA, and I've got some questions crucial to make it work:
Is that correct that there is on-die termination on both DDR2 memory and ...
