SDRAM stands for synchronous dynamic random access memory. Being synchronous it relies on a seperate clock signal for moving commands and data to/from the device.

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Do I need to reset a DDR's DLL when I change clock frequencies?

I have a system that boots at one frequency and then the main PLL is reloaded to continue boot at a higher frequency. When this is done, the DDR is put in to self refresh. After the main PLL locks, ...
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36 views

Multi-processor memory controller chips

I am trying to find a controller chip for either SRAM or S/DRAM which can properly manage access of the memory from one or more devices (i.e. microprocessors). I have been up and down Google and all I ...
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3answers
90 views

Using 16bit SDRAM with 8bit bus?

I have a design with an 8bit SDRAM which I want to replace with a 16bit one,the problem is I don't have much pins left to connect all 16bit data bus, is it possible to access the whole memory using an ...
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1answer
48 views

Terminating SDRAM on opposite side of board

I have a 4-layer board with the micro and sdram on opposite sides, the ram signals are short, but I still want to terminate them (I can test the board later and determine if I really need ...
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2answers
135 views

How does DDR SDRAM work?

The figure is about how DDR SDRAM and DDR SDRAM2 works. After taking some time searching, I still cannot understand the figure. Can anyone please help me understand it? In this case, is the ...
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56 views

DDR SDRAM controller read data is half to that of write data

I have to use DDR SDRAM of Spartan 3E, where I have to write data and then read back the data on desired address. The read and write waveform for burst length 4 are given below: The read waveform ...
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48 views

Close Vias cause a Signal problem on high speeds?

I have designed a 4-layer board (signal + GND + PWR + signal). Have an SDRAM (using it about 80MHz). My stack up is: ...
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2answers
362 views

What do memory configurations like “256Kx18” mean?

This is a beginner question here. When choosing memory ICs, one of the options is the memory size/configurations. I understand the size part, but what does the "16Kx9" mean? It seems the same memory ...
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2answers
151 views

Organization of large memory using memory blocks

I found the following question in a test. I am not looking for an answer to the question per se, but I am having difficulty understanding the part in bold, as explained below. A main memory unit ...
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179 views

How to implement memory mapped IO

I am describing a system in VHDL. This system already contains a processor, a DDR SDRAM controller and a VGA controller. VGA reads pixels from SDRAM (already validated and proven in FPGA). Although ...
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2answers
90 views

SDRAM initialization

I've been trying to study how the ARM bootloader works, but initialization of SDRAM is still somewhat a mystery to me. For example AT91 Bootstrap uses following function for initialization. I think I ...
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2answers
383 views

SDRAM problem with LPC1788

This is my PCB layout: My problem is: When i tried to Access SDRam with my example code (Memory test Code) everything seems ok. All the SDRam Data changes what i need. But when i tried to Access ...
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727 views

Choosing a SDRAM pcb layout

I'm working on a project with the quite new STM32F429 in LQFP208 package. I need to solder the first couple of prototype by myself for low budget reason. I choose this package so I could check myself ...
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70 views

SDRAM Edge Rates

I've found older SDRAM sources with lower speed grades (133Mhz) are getting more difficult to find, while the higher speed grades (166Mhz+) are more readily available. Not being a memory expert, I'm ...
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38 views

How to chose a compatible, drop-in replacement for a TSOPII-54 SDRAM module with more space?

I have a device that uses a PSC (Powerchip) A2V64S40CTP-G7 TSOPII-54 SDRAM chip. It's a 64MBit (8MB) RAM module. I'd like to put a larger chip in that device, and what I need to wrap my head around, ...
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51 views

SDRAM timing requirements

I am interfacing a Micron MT48H16M32LFCM-75 SDRAM with an Atmel AT91SAM9G20 and I need to verify on paper (as far as possible), that the timing specifications between those two devices are compatible. ...
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2answers
201 views

How does SDRAM refresh interact with ECC

I'm trying to understand how SDRAM hardware works if it also has ECC capability. If a memory system has ECC capability it will be able to correct a single bit error in a block of memory and detect, ...
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2answers
358 views

How DDR2 SDRAM works?

I have the Xilinx Spartan-3AN Starter Kit and I need to use the on board DDR2 SDRAM (MT47H32M16CC-XX). Until now I only used Static RAM and this type of memory is new for me. Can someone explain me ...
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1answer
93 views

Do I have to equate clock and Data Bus propagation delay for Transmission Lines?

My question is about SDRAM timings for clock and DataBUS. Som designer advice that clock pin has to be the shortest one. Data Bus may be longer than these because of the some problems. But clock trace ...
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7answers
1k views

How can 8-bit processor support more than 256 bytes of RAM?

If a 32 bit processor can handle 4GB of RAM(aproximately), why do my arduino mega 2560 has 8kB of SRAM, if being a 8-bit processor allows it to handle just 256 bytes?, or am i reading this next page ...
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3answers
1k views

Interfacing with RAM from a PC, e.g. SDRAM / DDR, to a microcontroller

I'm looking into interfacing standard PC form-factor SDRAM or DDR sticks to a microcontroller, but I can't find any definitive details on how they work in terms of how the bus works. I guess it's ...
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137 views

What is lead-in termination?

This term is mentioned in the Micron Application Note: Hardware Tips for Point-to-Point System Design on page 10 (...For signals with lead-in termination...), however I've been struggling to find out ...
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1k views

Why not SRAM for FPGA in image processing?

I'm beginning with VHDL coding and I've done some basic image processing on my development board. I've noticed that most FPGA development boards often use DRAM (SDRAM, DDRAM) as RAM. For example, I'm ...
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145 views

SDRAM on opposite side of board with respect to uC

Just a quick question. Is it advised against to place a high speed memory device on the opposite side of the PCB with respect to the microcontroller? And if it is ill advised, how is it possible to ...
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139 views

Memory interface for video output

I am designing a system where a DSP (like the TMS320VC5501) processes some video data and outputs it to a PSP screen (the ones sold on sparkfun). The issue I'm having here is designing the video ...
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119 views

How do they integrate logic into a DRAM process while manufacturing SDRAM?

When SDRAM is manufactured, how do they integrate logic into the IC while they are using a DRAM process for fabrication? Because SDRAM requires logic to decode its inputs, do the burst ordering, etc. ...
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159 views

SDRAM chip selection

I need to buffer 1.5Gb/s of video data through SDRAM, which works out to be 3Gb/s total in and out combined. This is my thinking so far: Write/read burst length is set to max (16 clock cycles), and ...
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97 views

Can a disconnected pin on DDR3 SDRAM go undetected?

I was testing some DDR3 SODIMM modules using Memtest86+ on a Lenovo Thinkpad T520. I re-tested a module that I previously marked faulty and it came out fine. So I wonder if it's possible that the ...
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411 views

SDRAM initialization issue (Freescale iMX31)

I'm trying to modify an existing init sequence (low level init of SDRAM) to accommodate a change in hardware configuration: an existing SDRAM on my iMX31 was replaced with a different size, otherwise ...
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630 views

SDRAM advantages

As of RAM technologies (the basic ones) is concerned, I consider the initial classification (based on the storage) as SRAM: The basic entity for storage (each cell) is the flip-flop (comprised of ...
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3answers
1k views

How does random memory access of RAM work?

HDD works in a partly sequential manner. However, RAM is known for random memory access, allowing equal speed of memory access for every location at every time. So, what makes RAM so special? How ...
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116 views

Sampling 133MHz bus with OWLS Logic Analyser

The OWLS specs state that it can operate in two sampling modes: 200Msps captures up to 100MHz waveforms on 16 channels 100Msps captures up to 50MHz waveforms on 32 channels Does this mean that ...
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Termination resistors: are they needed?

For a project I'm designing, I'm using an IS42s32800 (TSOP) SDRAM with an LPC1788 (QFP) microcontroller. On the PCB I have 4 layers with a ground plane right below the top signal layer and a VDD plane ...
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Memory (RAM) of computers after shut down

After computer shuts down, is it possible to retrieve data in RAM? I heard that police was able to do that... so I felt that was somehow weird..
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450 views

Freezing DRAM for forensics (coldboot)

I've known about the coldboot trick for a while, but have never really considered the physics behind it. I've read the paper, but it doesn't really cover why it works. How does physically cooling a ...
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3answers
2k views

What is pseudo-open-drain-logic?

DDR4 reportedly uses something called pseudo-open-drain-logic or PODL. How does it work?
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SDRAM Prototype vs Production Woes

I have a design using an LPC1788 together with a SDRAM module from ISSI (IS42S32800D). This is a 32bit interface. I have routed this design out and had a prototype made with a PCB manufacturer that ...
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129 views

Expand RAM and flash on LPC2294

I have a project in mind. I want to buy an LPC2294 microcontroller, SDRAM IC, and flash IC (those IC's haven't yet been defined). What I want to do is connect those ICs to the microcontroller in order ...
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1answer
389 views

What are these pull ups for on this SDRAM?

Apologies for all these questions about SDRAM, but I want to get this next board run right. I have an LPC1788 processor with an external memory controller I am interfacing with SDRAM. There is no ...
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1answer
328 views

Interface Mobile SDRAM (1.8V) with 3.3V SDRAM controller

I am looking for a 256Mbit SDRAM module in BGA format, to buy in units of 1000. However the cost for these modules are extremely high for packages using a 32bit bus in standard 3.3V voltages, however ...
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3answers
1k views

SDRAM issue - LPC1788

I have been using an NXP LPC1788 dev board which I have developed my application on (.NET Microframework Cortex-M3 Port). Everything was well and good on this board, I had no issues with RAM or ...
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1answer
592 views

Using SDRAM with a MC68000

I'm currently working on developing myself a computer based on the Motorola 68000 CPU and am currently working on the RAM interface. Since I want a basic multitasking OS, I want to use 1 MB of RAM. ...
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1answer
1k views

Expose SDRAM as a USB 3 mass storage device

Challenge: Build a device that can host one or more SDRAMs (e.g DDR2, DDR3) and expose them as a USB 3 (slave) mass storage device. Goal: Allow a USB 3 host to mount the device and allow near ...
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5answers
1k views

The precise reason why DRAM is slower to write than to read?

I just want to make sure I have my facts straight. In the olden days when I was a teenager and the Internet was unknown outside of academia, I recall learning (I wasn't taught this per se) that ...
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3answers
1k views

I know why DRAM is slower to write than to read, but why is the L1 & L2 cache RAM slower to write?

DRAM is slower to write than read because it takes time to either charge or discharge a DRAM memory cell. But what about the SRAM in my processor's L1 and L2 caches? It's slower to write as well but ...
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1answer
307 views

Do DDR2 chips and controllers have on-die termination?

I am going to try to interface a low-speed 8-bit DDR2 chip with an FPGA, and I've got some questions crucial to make it work: Is that correct that there is on-die termination on both DDR2 memory and ...