SDRAM stands for synchronous dynamic random access memory. Being synchronous it relies on a seperate clock signal for moving commands and data to/from the device.

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Are all DDR3L (1.35V) DIMMS safe to use in a computer system that uses DDR3 (1.5V) DIMMs? [migrated]

The sales support of (the consumer/prosumer sales subsidiary of) a DRAM manufacturer answered a pre-sales question I made with (translated from an email in French): 1.35V Memory DIMMs are dual ...
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1answer
40 views

How to calculate how much data a Core 2 duo E8 can write to the RAM per second?

I'd like to know how exactly I could calculate how much data the Core 2 duo E8 can write to the RAM per second, given that it is not overclocked and the RAM is 333MHz-DDR3?
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1answer
78 views

DDR4 frequency decrease if populated with more than one module per channel

I'm curious how one particular company Gigabyte ensures its server motherboards to run at the maximum supported memory frequency even when there're two or three DIMMs per channel (of coure we're ...
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4answers
104 views

Why DRAM costs much more than flash memory?

Comparing prices at a local store, I calculated prices 0.36 USD/GB for SSD NAND flash memory and 5.41 USD/GB for DRAM memory. The difference is 15 times. Why so big difference? Both are semiconductor ...
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0answers
20 views

Is DQM latency during READ always two cycle and independent from CL in SDR SDRAM?

Reading SDR SDRAM datasheets, i found (and had been surprised) that during READs (with Burst Length >=2) DQM latency is always two cycles. That statement is given explicitly at least in one datasheet ...
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1answer
55 views

Is memory bandwidth advertised for DRAM (like 12800 MB/s for PC-12800) ever achievable?

Memory bandwidth for DRAM like DDR3-1600 / PC-12800 is a function (product) of memory frequency (1600 MHz) and memory bus characteristics (width and number of channels). But memory also has timings ...
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79 views

LTDC data starvation during simultaneous SD-RAM and NOR Flash access with STM32F429 rev 3

Application details: SDRAM is used as the LCD frame buffer. Memory for 2 LCD frame buffers are allocated(double buffering) in SDRAM. LTDC will be always accessing one of the frame buffer in the ...
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1answer
142 views

Loading and displaying on VGA monitor a Background image in DE2-115's SDRAM

I would like to load a background image which I currently have saved as a .bmp into the DE2-115's SDRAM. I would then like to display this background image on a VGA-monitor (640x480). I will then be ...
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1answer
81 views

DRAM - is data pins order important when routing on PCB?

Quick question: I have SDRAM (SDR) and trying to connect it to uC. Can I route data bits from SDRAM to uC in any order? So they aren't connected respectively (d0->d0, d1->d2 ... d15->d15) but in any ...
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1answer
54 views

How does a flip-flop circuit keep it state?

When reading about the difference between SDRAM and SRAM (electronically), I understand that SDRAM requires the dynamically charging of the capacitors to maintain their states. I do not get how SRAM ...
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87 views

Can this SDRAM be used with STM32F7?

I have STM32F7 (which has a Flexible Memory Controller capable of interfacing SDRAMs) and I want someone to check if it is able to interface this SDRAM - IS42S32800D ...
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2answers
143 views

Building a SDRAM Controller (VHDL)

I am using the Spartan SP601 Evaluation Board, which includes 1 GB Elpida EDE1116ACBG-8E-E SDRAM. I would like to build a RAM controller, but have no experience in working with RAM before. I largely ...
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54 views

One chip-select/die-termination/clock-enabler for multiple DDR3 DRAM chips

I'm struggling to know how one DRAM chip select pin, DRAM_CS below can help the processor/CPU manage four DRAM chips? And also how can one clock enabler ...
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0answers
84 views

Why DDR3 RAS timing have to be greater than RCD + CAS timing?

By definition, tRAS is the minimum delay from when a particular row in a bank is activated, to when it can be closed with a PRE command. I have seen claims numerous times that tRAS should be > tRCD + ...
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1answer
49 views

DDR3 bank activation

I've been trying to follow: http://www.anandtech.com/show/3851/everything-you-always-wanted-to-know-about-sdram-memory-but-were-afraid-to-ask/3 On this page, they say: "Following activation, the open ...
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0answers
32 views

Setting burst length SDRAM initialization

I'm trying to change the burst length in the DDR SDRAM initialization (more specifically, the Micron DDR SDRAM MT46V16M16). I have found the relevant data sheet and information on the ...
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1answer
49 views

What are the meanings of the fields of this cache memory?

I have a cache memory simulator with this cache memory shown. The cache size is 64 bytes and the block size is 8 bytes. What is the decomposition into fields? If block size is 8 bytes, then ...
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1answer
219 views

Why DIMM has 64 bit data width?

Wikipedia’s definition of DIMM says: Most DIMMs are built using "×4" ("by four") or "×8" ("by eight") memory chips with nine chips per side; "×4" and "×8" refer to the data width of the DRAM chips in ...
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2answers
791 views

In an SDRAM how do address rows/columns and rank width and bank width relate to the total memory size?

I have a Micron SDRAM (MT16KTF1G64HZ-8GB). The size of the memory is 8GB. I did some calucaltions and 8GB of data means 2^36 bits capacity. Now when I look in the Micron data sheet, the row address is ...
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2answers
210 views

Building a framebuffer

I'm trying to build a framebuffer using an FPGA and an external memory. I have a soft core CPU running on the FPGA as well a small chunk of logic to output signals to an LCD. My goal is to have the ...
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1answer
376 views

How is the DDR3 SDRAM addressing done?

In order to work on programming a DDR3 SDRAM, I was going through the JEDEC standard DDR3 SDRAM specification (link to pdf, pg 30). I got a bit confused about the DDR3 addressing, a snapshot of which ...
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2answers
87 views

understanding sdram geometry

I am trying to understand the SDRAM and in the datasheet I am not able to understand the geometry. The SDRAM is a Samsung K4S561632N 32MB. ...
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1answer
909 views

Exploring MCDRAM

I was going through the below link and found one peripheral named MCDRAM. If i am not wrong it looks like a Multichannel memory device which is integrated on same package. Can someone explain what ...
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566 views

Why All DDR's (DDR, DDR2, DDR3) internal clock sets to 200MHz

If we see the DDR Upgrade technology explain below the internal clock of all DDR is set to 200 MHz. DDR For example,DDR-400 Efficient frequency data bus is 400 MHz True clock rate (IO buffer ...
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1answer
237 views

Do I need to reset a DDR's DLL when I change clock frequencies?

I have a system that boots at one frequency and then the main PLL is reloaded to continue boot at a higher frequency. When this is done, the DDR is put in to self refresh. After the main PLL locks, ...
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1answer
62 views

Multi-processor memory controller chips

I am trying to find a controller chip for either SRAM or S/DRAM which can properly manage access of the memory from one or more devices (i.e. microprocessors). I have been up and down Google and all I ...
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3answers
391 views

Using 16bit SDRAM with 8bit bus?

I have a design with an 8bit SDRAM which I want to replace with a 16bit one,the problem is I don't have much pins left to connect all 16bit data bus, is it possible to access the whole memory using an ...
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1answer
112 views

Terminating SDRAM on opposite side of board

I have a 4-layer board with the micro and sdram on opposite sides, the ram signals are short, but I still want to terminate them (I can test the board later and determine if I really need ...
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2answers
2k views

How does DDR SDRAM work?

The figure is about how DDR SDRAM and DDR SDRAM2 works. After taking some time searching, I still cannot understand the figure. Can anyone please help me understand it? In this case, is the ...
4
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2answers
686 views

What do memory configurations like “256Kx18” mean?

This is a beginner question here. When choosing memory ICs, one of the options is the memory size/configurations. I understand the size part, but what does the "16Kx9" mean? It seems the same memory ...
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284 views

Organization of large memory using memory blocks

I found the following question in a test. I am not looking for an answer to the question per se, but I am having difficulty understanding the part in bold, as explained below. A main memory unit ...
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2answers
815 views

How to implement memory mapped IO

I am describing a system in VHDL. This system already contains a processor, a DDR SDRAM controller and a VGA controller. VGA reads pixels from SDRAM (already validated and proven in FPGA). Although ...
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2answers
395 views

SDRAM initialization

I've been trying to study how the ARM bootloader works, but initialization of SDRAM is still somewhat a mystery to me. For example AT91 Bootstrap uses following function for initialization. I think I ...
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4answers
991 views

SDRAM problem with LPC1788

This is my PCB layout: My problem is: When i tried to Access SDRam with my example code (Memory test Code) everything seems ok. All the SDRam Data changes what i need. But when i tried to Access ...
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3answers
3k views

Choosing a SDRAM pcb layout

I'm working on a project with the quite new STM32F429 in LQFP208 package. I need to solder the first couple of prototype by myself for low budget reason. I choose this package so I could check myself ...
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1answer
105 views

SDRAM Edge Rates

I've found older SDRAM sources with lower speed grades (133Mhz) are getting more difficult to find, while the higher speed grades (166Mhz+) are more readily available. Not being a memory expert, I'm ...
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100 views

SDRAM timing requirements

I am interfacing a Micron MT48H16M32LFCM-75 SDRAM with an Atmel AT91SAM9G20 and I need to verify on paper (as far as possible), that the timing specifications between those two devices are compatible. ...
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2answers
633 views

How does SDRAM refresh interact with ECC

I'm trying to understand how SDRAM hardware works if it also has ECC capability. If a memory system has ECC capability it will be able to correct a single bit error in a block of memory and detect, ...
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2answers
767 views

How DDR2 SDRAM works?

I have the Xilinx Spartan-3AN Starter Kit and I need to use the on board DDR2 SDRAM (MT47H32M16CC-XX). Until now I only used Static RAM and this type of memory is new for me. Can someone explain me ...
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1answer
123 views

Do I have to equate clock and Data Bus propagation delay for Transmission Lines?

My question is about SDRAM timings for clock and DataBUS. Som designer advice that clock pin has to be the shortest one. Data Bus may be longer than these because of the some problems. But clock trace ...
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7answers
4k views

How can 8-bit processor support more than 256 bytes of RAM?

If a 32 bit processor can handle 4GB of RAM(aproximately), why do my arduino mega 2560 has 8kB of SRAM, if being a 8-bit processor allows it to handle just 256 bytes?, or am i reading this next page ...
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3answers
3k views

Interfacing with RAM from a PC, e.g. SDRAM / DDR, to a microcontroller

I'm looking into interfacing standard PC form-factor SDRAM or DDR sticks to a microcontroller, but I can't find any definitive details on how they work in terms of how the bus works. I guess it's ...
7
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1answer
223 views

What is lead-in termination?

This term is mentioned in the Micron Application Note: Hardware Tips for Point-to-Point System Design on page 10 (...For signals with lead-in termination...), however I've been struggling to find out ...
7
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2answers
2k views

Why not SRAM for FPGA in image processing?

I'm beginning with VHDL coding and I've done some basic image processing on my development board. I've noticed that most FPGA development boards often use DRAM (SDRAM, DDRAM) as RAM. For example, I'm ...
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1answer
205 views

SDRAM on opposite side of board with respect to uC

Just a quick question. Is it advised against to place a high speed memory device on the opposite side of the PCB with respect to the microcontroller? And if it is ill advised, how is it possible to ...
3
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1answer
156 views

Memory interface for video output

I am designing a system where a DSP (like the TMS320VC5501) processes some video data and outputs it to a PSP screen (the ones sold on sparkfun). The issue I'm having here is designing the video ...
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1answer
193 views

How do they integrate logic into a DRAM process while manufacturing SDRAM?

When SDRAM is manufactured, how do they integrate logic into the IC while they are using a DRAM process for fabrication? Because SDRAM requires logic to decode its inputs, do the burst ordering, etc. ...
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2answers
192 views

SDRAM chip selection

I need to buffer 1.5Gb/s of video data through SDRAM, which works out to be 3Gb/s total in and out combined. This is my thinking so far: Write/read burst length is set to max (16 clock cycles), and ...
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2answers
120 views

Can a disconnected pin on DDR3 SDRAM go undetected?

I was testing some DDR3 SODIMM modules using Memtest86+ on a Lenovo Thinkpad T520. I re-tested a module that I previously marked faulty and it came out fine. So I wonder if it's possible that the ...
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1answer
447 views

SDRAM initialization issue (Freescale iMX31)

I'm trying to modify an existing init sequence (low level init of SDRAM) to accommodate a change in hardware configuration: an existing SDRAM on my iMX31 was replaced with a different size, otherwise ...