Questions regarding how to properly ensure Signal Integrity, protection from noise, shielding, proper pcb layout.

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14
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1answer
207 views

PCIe, diagnosing and improving an eye diagram

I have implemented a design that uses PCIe. It is somewhat different in that the PCIe interface is used as a chip-to-chip communication lane on a single PCB (e.g. no PCIe connector). The root ...
0
votes
1answer
35 views

How do I determine if the clock signal suffers from high speed effects

I need to determine if the clock signal inside a multichip module shall suffer from high speed effects i.e reflection and ringing. I have: (1) IBIS models of the components inside the multi-chip ...
1
vote
2answers
62 views

Where do all the PDN capacitors sit?

I have my voltage rails coming off board and I have quite a number of ICs. Each has their own decoupling and for the really demanding ICs I have a bulk capacitor. If I have some target impedance and ...
1
vote
1answer
48 views

Trace Dimensions limitation for JTAG signals

I have a JTAG bus that I need to go over PCB (or could make cable) for about 12 inches. I am trying to figure out the signal integrity specs for the JTAG bus ... what trace width vs. trace length I ...
2
votes
2answers
173 views

Is it possible to physically measure the input and output impedance of a component?

Input and output impedance is an important property of complex electronic components. Is it possible to physically measure them like we measure resistance? Is it possible to measure it for BJT based ...
0
votes
0answers
26 views

What skin depth percentage will require the use of a via to connect top and bottom side of a plane?

This question arose from the comments of the the following question : Physically, what is and how to, make an anti pad? If we have a plane with adjacent signal layers to the plane (similar to the ...
1
vote
2answers
210 views

Physically, what is and how to, make an anti pad?

Consider the following later stack (it's only the top 3 layers of an 8 layer board) Top Signal Layer Plane Signal Layer I have a high frequency trace that is being routed on the top layer and I ...
0
votes
0answers
21 views

Noise and raise in heat causes lose/no signal strength of my wireless internet USB

I'm 15-20Kms away from tower which is source of my signals. I have a Booster couple of months ago it was good enough to provide Strong Signals, As Summer comes the problem of raise in atmospheric ...
0
votes
1answer
49 views

How subtle or dramatic are the effects of a impedance mismatch by a certain percentage?

If a trace is designed to be 50 ohms, how much of an effect would 10% or 20% mismatch between line impedance and termination values ? For instance, a 50 ohm line with 45 ohm or 55 ohm series ...
5
votes
1answer
120 views

SPI Bus Termination Issue

I've been working on a project where an OMAP Linux SPI master interacts with 6 SPI slaves peripherals (5x A/D converters and single magnetometer). I can set the SPI clock frequency and have ...
3
votes
4answers
566 views

Return path on a PCB

I've spent the weekend absorbing video lectures from Eric Bogatin and reading his book "Signal and Power Integrity - Simplified" He states that the the return path for the PCB may be any DC plane ...
0
votes
1answer
105 views

5V TTL signals over 4m or so?

Adding input and output capacitors either side of my 5V DC-DC converter doesn't seem to help much, and I'm wondering if some kind of signal interference might be my problem. I'm running signal from a ...
0
votes
2answers
104 views

Trace termination length limits

Are there any length limits to series termination ? If I have a trace that's 12 in or a trace that is 100 in, can the same series termination resistor be used (assuming that Zo = 50 ohm) ?
1
vote
3answers
133 views

Height of the substrate in online PCB impedance calculators

Is the height of the substrate just the non conductive portion between copper layers ? Using this calculator as an example In a 4L board, if the top and bottom traces are of the same thickness and ...
0
votes
2answers
114 views

Understanding capacitive load conditions for a microcontroller

This is from a PIC24E microcontroller datasheet. My question is understand what does "load conditions for device timing" mean ? Does it mean in order to maintain timing (say for a high speed PWM ...
1
vote
3answers
103 views

How to select source termination resistors by looking at signal?

If I have two devices that some distance apart on a fairly large PCB (could be 1 in, or it could be 20 in). If I arbitrary select a value for R1, lets say 33 ohms in this example and if my digital ...
1
vote
1answer
45 views

How to setup PCB to correct for signal integrity issues after boards are made?

I have a board layed like the in the image below. I have a microcontroller that generated clk1, which feeds into U1. After 8 clock cycles, the clock passes through to U2 and does this 30 times. It's a ...
0
votes
0answers
60 views

Inverter noise picked up on USB data lines breaks USB communication - signal integrity

I have an equipment where the CPU is a 16-bit dsPIC. There is an inverter board switching 300V across a 4 MOSFETS H-bridge at 20kHz and delivering 180W. This equipment communicates with a computer ...
0
votes
2answers
90 views

PCB via, increase annular ring or increase hole size?

I have to use via to route small analog signals. If I want to minimize the effect of via on the signal, should I increase the annular ring size or hole size. Lets say the total via diameter is same in ...
0
votes
1answer
54 views

Is TMDS really differential?

TMDS (Transition Minimised Differential Signalling) is a nominally differential signalling specification used, for example, in DVI & HDMI. Today though I was reading Brooks' Signal Integrity ...
-1
votes
4answers
552 views

What are the main causes of Overshoot and undershoot of a signal?

I'm not an EE major, but I was curious what causes overshoot and undershoot. Where can i find a detailed explanation of the process? I heard it has to do with the parasitic capacitance, but there ...
3
votes
2answers
90 views

How can you auto-calibrate a conductance sensor?

Sensors need to be calibrated every so often, so that the voltage/current change due to the change in the conductance is always the same, and the signal conditioning of that voltage/current is always ...
1
vote
1answer
51 views

I have read that a design which fails signal integrity shall have EMC issues

I have read that if a design has EMC issues and is emitting a lot of radiation, then there is a relationship with some signal paths not being properly terminated and/or there being signal integrity ...
1
vote
2answers
56 views

transmission loss with microsd extender

Would a 20-30cm microSD extension cord suffer any kind of noticeable transmission loss? This is a passive extender - literally, a microsd card with wires coming off of it, and a card slot at the other ...
0
votes
1answer
93 views

Do we ever use the pin capacitance of a digital circuit component (e.g ASIC, FPGA) in doing timing or data integrity analysis

As far as I understand, the pin capacitance on say an ASIC or FPGA effects the rise and fall time of the signal on it. It is also possible that the impedance offered by this capacitance to a very high ...
4
votes
1answer
169 views

How can I determine a maximum run length for CANbus?

I'm using CANbus to communicate between two circuit boards. 120 ohm termination resistors on either end. Transceivers are MCP2561 and ISO1050. Bit rate is in the hundreds of kilobits/second. Medium is ...
0
votes
2answers
86 views

Why is the data rate a function of the length of the transmission line?

The length of a transmission line is limiting the highest possible data rate on that line. Why are faster signals more likely to become corrupted on long transmission lines than on shorter ones, with ...
0
votes
1answer
108 views

SPI Bus Clock Slew Rate

I am interfacing LPC1768 SPI bus and SST25VF016B SPI Serial Flash. Flash is 50Mhz, and these are the values I copied from SPI Flash Datasheet. page 24. FCLK (Serial Clock Frequency) 50 MHz TSCKH ...
2
votes
1answer
489 views

RMII MAC side routing and signal integrity

I have some signal integrity and EMC questions. In my board LPC1768 RMII interface is connected to LAN8720. Because of pin locations some RMII signals must go through bottom layer. This is a four ...
1
vote
1answer
56 views

Suggest FEC technique

I am a novice in signal processing so there may be a fundamental gap in my understanding of the concept. I am working on a link which has an error of 1 in 1000 bits which I have to improve to 1 in ...
4
votes
5answers
456 views

Why does differential signaling send complementary signals instead of just pairing the input and ground voltage?

I'm very new to EE, so please excuse me if this question is bad or has an obvious answer. After reading an overview of differential signalling, it left me wondering: Why does differential signalling ...
5
votes
1answer
354 views

DDR bus design review

In our last build we had issues with DDR stability in our prototype, simply because of lack of experience with this type of high speed memory connections. We managed to get it working with halving the ...
0
votes
3answers
120 views

Analog signal over long cable

I would like to use 50mV FSD signal to sense DC current at a distance of ~70 feet with a twisted pair cable and then perform signal condition there. Does anyone have any experience with this? " ...
2
votes
2answers
331 views

Problem with Ethernet PHY

One of my clients is experiencing problems with a SMSC LAN8710A PHY that is connected to a Xilinx FPGA. The Ethernet link works perfectly when the board is connected to my MacBook or to my office ...
5
votes
3answers
685 views

How do I invert a signal without deforming it, and without using a logic gate?

I have an IC which outputs pulses over an open collector pin. I need both these pulses and their inverses in my circuit. I want to do the inversion by using as few as possible transistors and without ...
3
votes
3answers
531 views

Electrical issue with USB ? Hi-speed device not working on own design

Disclaimer, I'm a SW guy, so please don't take anything for granted, and I would appreciate explanations in layman's terms :) We have a custom design based on ...
1
vote
2answers
170 views

Avoiding crosstalk between makeshift wires

My setup is as follows. I have 6 foot long 22-gauge wires connecting pin headers of an audio codec eval board and an FPGA daughterboard. I am sending an 8KHz and 128KHz clock signals and a data signal ...
1
vote
1answer
146 views

Will software-based DSSS work?

We are implementing a 2.4 GHz RF link using a TI CC2541 chip (http://www.ti.com/product/cc2541) and we are new to RF design. We want a robust, low-bandwidth, low-latency link. We were thinking of ...
3
votes
3answers
391 views

Returning Current on power planes? (High frequencies)

For a 4-Layered design (Signal-Ground-Power-Signal): I wonder that, I need both bottom signal layer and top signal layer for high frequency signals. I will use both of them for my high frequency ...
2
votes
3answers
805 views

SDRAM problem with LPC1788

This is my PCB layout: My problem is: When i tried to Access SDRam with my example code (Memory test Code) everything seems ok. All the SDRam Data changes what i need. But when i tried to Access ...
3
votes
1answer
170 views

Return Paths of Signals on Flat Flex Cable

I have a 4 layer PCB with a typical stackup (signal-gnd-vcc-signal) and on the top layer there's a CMOS sensor connected with a flat flex cable... I was wondering, since there's no reference plane ...
3
votes
1answer
564 views

How does the DDR clock compensation capacitor improve signal quality?

I saw in some DDR3 designs that there is a capacitor between differential clock lines, for example the image below: In the document this image comes from it says: On the DDR3 SDRAM DIMM, there ...
2
votes
1answer
204 views

RS-485 / CAN signal levels

From what I know, CAN at the physical layer in the "recessive" state just lets pull-up/pull-down do the work. Does that mean the rise time is theoretical slower than a RS-485 transceiver? And about ...
2
votes
5answers
212 views

Pulse counting affected by oscilloscope probe

As shown in the block diagram below. I generate a 128KHz clock and a stream of known number of pulses in 10msec (the 10msec timer is implemented in the pulse counter by dividing the 128KHz by 1280) ...
7
votes
3answers
927 views

What is the effect of supply voltage asymmetry in opamp amplifier topologies?

What is the effect of a \$\Delta V\$ voltage shift in one of the supply voltage inputs of an opamp on its functional behavior (\$\Delta V\$ can be positive or negative)? Suppose that, I'm designing a ...
3
votes
1answer
115 views

How to ground pins on a multilayer board with a ground plane?

Let's say I have a multilayer board with a single dedicated ground plane. Should I place all the grounds directly to the plane with a via as close as possible to the pin/pad or should I be looking ...
3
votes
2answers
471 views

SPI multiple slave termination

I've been reading about signal integrity and went through this site reading about it as well as other references. Alot of the topics deal with a single slave, but not so much multiple slaves. I'll be ...
11
votes
1answer
966 views

Why does reflection off a PCB via look like this?

My question is related to http://mobius-semiconductor.com/whitepapers/ISSCC_2003_SerialBackplaneTXVRs.pdf. On the page 18 there are a few figures of "TDR off Diferent Types off Vias". I am confused ...
5
votes
1answer
602 views

On referencing power planes and return current paths

I recently worked on a 16-layer board design that contained only 2 ground planes, at the outer layers of the board, and several power planes (+1V1, +1V8, +3V0, +5V0) in the middle: Since there are ...
2
votes
1answer
507 views

Benefits of top and bottom ground pour in multilayer boards with proper ground plane layers and stackup

I'm trying to get some analytical feeling for the use of ground pours on bottom and top layer in multilayer boards with proper stackups such as (for example). Top Gnd Sig1 Power Power Sig2 Gnd ...