Tagged Questions

Questions regarding how to properly ensure Signal Integrity, protection from noise, shielding, proper pcb layout.

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1
vote
2answers
34 views

transmission loss with microsd extender

Would a 20-30cm microSD extension cord suffer any kind of noticeable transmission loss? This is a passive extender - literally, a microsd card with wires coming off of it, and a card slot at the other ...
0
votes
1answer
56 views

Do we ever use the pin capacitance of a digital circuit component (e.g ASIC, FPGA) in doing timing or data integrity analysis

As far as I understand, the pin capacitance on say an ASIC or FPGA effects the rise and fall time of the signal on it. It is also possible that the impedance offered by this capacitance to a very high ...
4
votes
1answer
64 views

How can I determine a maximum run length for CANbus?

I'm using CANbus to communicate between two circuit boards. 120 ohm termination resistors on either end. Transceivers are MCP2561 and ISO1050. Bit rate is in the hundreds of kilobits/second. Medium is ...
0
votes
2answers
66 views

Why is the data rate a function of the length of the transmission line?

The length of a transmission line is limiting the highest possible data rate on that line. Why are faster signals more likely to become corrupted on long transmission lines than on shorter ones, with ...
0
votes
1answer
41 views

SPI Bus Clock Slew Rate

I am interfacing LPC1768 SPI bus and SST25VF016B SPI Serial Flash. Flash is 50Mhz, and these are the values I copied from SPI Flash Datasheet. page 24. FCLK (Serial Clock Frequency) 50 MHz TSCKH ...
2
votes
1answer
101 views

RMII MAC side routing and signal integrity

I have some signal integrity and EMC questions. In my board LPC1768 RMII interface is connected to LAN8720. Because of pin locations some RMII signals must go through bottom layer. This is a four ...
1
vote
1answer
48 views

Suggest FEC technique

I am a novice in signal processing so there may be a fundamental gap in my understanding of the concept. I am working on a link which has an error of 1 in 1000 bits which I have to improve to 1 in ...
2
votes
5answers
231 views

Why does differential signaling send complementary signals instead of just pairing the input and ground voltage?

I'm very new to EE, so please excuse me if this question is bad or has an obvious answer. After reading an overview of differential signalling, it left me wondering: Why does differential signalling ...
5
votes
1answer
202 views

DDR bus design review

In our last build we had issues with DDR stability in our prototype, simply because of lack of experience with this type of high speed memory connections. We managed to get it working with halving the ...
0
votes
3answers
76 views

Analog signal over long cable

I would like to use 50mV FSD signal to sense DC current at a distance of ~70 feet with a twisted pair cable and then perform signal condition there. Does anyone have any experience with this? " ...
2
votes
2answers
167 views

Problem with Ethernet PHY

One of my clients is experiencing problems with a SMSC LAN8710A PHY that is connected to a Xilinx FPGA. The Ethernet link works perfectly when the board is connected to my MacBook or to my office ...
5
votes
3answers
568 views

How do I invert a signal without deforming it, and without using a logic gate?

I have an IC which outputs pulses over an open collector pin. I need both these pulses and their inverses in my circuit. I want to do the inversion by using as few as possible transistors and without ...
0
votes
0answers
46 views

Choosing Connector for High Speed Signals

What parameters make connectors for high speed signals different from ordinary berg sticks/box connectors? I want to connect MIPI-CSI2 signals from my Processor board to an Add-On board through ...
3
votes
3answers
252 views

Electrical issue with USB ? Hi-speed device not working on own design

Disclaimer, I'm a SW guy, so please don't take anything for granted, and I would appreciate explanations in layman's terms :) We have a custom design based on ...
1
vote
2answers
122 views

Avoiding crosstalk between makeshift wires

My setup is as follows. I have 6 foot long 22-gauge wires connecting pin headers of an audio codec eval board and an FPGA daughterboard. I am sending an 8KHz and 128KHz clock signals and a data signal ...
0
votes
0answers
49 views

Close Vias cause a Signal problem on high speeds?

I have designed a 4-layer board (signal + GND + PWR + signal). Have an SDRAM (using it about 80MHz). My stack up is: ...
1
vote
1answer
82 views

Will software-based DSSS work?

We are implementing a 2.4 GHz RF link using a TI CC2541 chip (http://www.ti.com/product/cc2541) and we are new to RF design. We want a robust, low-bandwidth, low-latency link. We were thinking of ...
3
votes
3answers
162 views

Returning Current on power planes? (High frequencies)

For a 4-Layered design (Signal-Ground-Power-Signal): I wonder that, I need both bottom signal layer and top signal layer for high frequency signals. I will use both of them for my high frequency ...
2
votes
3answers
505 views

SDRAM problem with LPC1788

This is my PCB layout: My problem is: When i tried to Access SDRam with my example code (Memory test Code) everything seems ok. All the SDRam Data changes what i need. But when i tried to Access ...
3
votes
1answer
137 views

Return Paths of Signals on Flat Flex Cable

I have a 4 layer PCB with a typical stackup (signal-gnd-vcc-signal) and on the top layer there's a CMOS sensor connected with a flat flex cable... I was wondering, since there's no reference plane ...
3
votes
1answer
334 views

How does the DDR clock compensation capacitor improve signal quality?

I saw in some DDR3 designs that there is a capacitor between differential clock lines, for example the image below: In the document this image comes from it says: On the DDR3 SDRAM DIMM, there ...
1
vote
1answer
143 views

RS-485 / CAN signal levels

From what I know, CAN at the physical layer in the "recessive" state just lets pull-up/pull-down do the work. Does that mean the rise time is theoretical slower than a RS-485 transceiver? And about ...
2
votes
5answers
184 views

Pulse counting affected by oscilloscope probe

As shown in the block diagram below. I generate a 128KHz clock and a stream of known number of pulses in 10msec (the 10msec timer is implemented in the pulse counter by dividing the 128KHz by 1280) ...
4
votes
2answers
459 views

What is the effect of supply voltage asymmetry in opamp amplifier topologies?

What is the effect of a \$\Delta V\$ voltage shift in one of the supply voltage inputs of an opamp on its functional behavior (\$\Delta V\$ can be positive or negative)? Suppose that, I'm designing a ...
3
votes
1answer
101 views

How to ground pins on a multilayer board with a ground plane?

Let's say I have a multilayer board with a single dedicated ground plane. Should I place all the grounds directly to the plane with a via as close as possible to the pin/pad or should I be looking ...
3
votes
2answers
328 views

SPI multiple slave termination

I've been reading about signal integrity and went through this site reading about it as well as other references. Alot of the topics deal with a single slave, but not so much multiple slaves. I'll be ...
10
votes
1answer
580 views

Why does reflection off a PCB via look like this?

My question is related to http://mobius-semiconductor.com/whitepapers/ISSCC_2003_SerialBackplaneTXVRs.pdf. On the page 18 there are a few figures of "TDR off Diferent Types off Vias". I am confused ...
5
votes
1answer
345 views

On referencing power planes and return current paths

I recently worked on a 16-layer board design that contained only 2 ground planes, at the outer layers of the board, and several power planes (+1V1, +1V8, +3V0, +5V0) in the middle: Since there are ...
2
votes
1answer
339 views

Benefits of top and bottom ground pour in multilayer boards with proper ground plane layers and stackup

I'm trying to get some analytical feeling for the use of ground pours on bottom and top layer in multilayer boards with proper stackups such as (for example). Top Gnd Sig1 Power Power Sig2 Gnd ...
3
votes
4answers
1k views

PCB Signal Bus design

I have a pcb with a SPI bus with several sensors that have to be connected to this bus. Since 90 degree traces are not recommended in a proper PCB design I ask myself how to connect so many sensors ...
2
votes
2answers
378 views

How should I check USB signal integrity?

I'm using 2 USB hubs chained together to hook up my phone to the computer to do some testing stuff. How can I check if the USB signal is being good or not? I tried scoping the USB pins with the USB ...
3
votes
3answers
179 views

understanding transmission line signal integrity through simulations

I need to simulate how signals are reflected based on the source, load and line impedances and how the signal integrity is effected by the spacing between different traces on a board, traces on the ...
8
votes
1answer
523 views

What separates a “good” eye diagram from a “bad” one?

I'm running some USB verification testing at work, and the Agilent oscilloscope I'm working with returns a nice summary of pass/fail statistics along with a pretty eye diagram. Since the pass/fail is ...
2
votes
1answer
392 views

Detect logic signal in a long distance. What type of interface to use?

My daughter board uses a comparator(LM339) to output logic 1 or 0 under a 3v3 supply. The cable connecting daughter board and main board is at least 1.5m. Luckily, the frequency is not fast but the ...
1
vote
2answers
132 views

Resistance between data/Addr pins and GND ranges from 1k to 1M, is this normal?

After soldering a 132-pin surface mount DSP, I checked if there are short circuits or not using "GreenLee DM-110" multimeter. I found that the resistance between data or address pins and GND ranges ...
1
vote
0answers
95 views

Analysing Signal quality through pogo pins using Hyperlynx

I have successfully modeled Linesim and boardsim schematics for quite a few designs in the past and we have been able to do the required SI simulations. I had one question though: On one of our ...
1
vote
1answer
92 views

Do I have to worry about backwards crosstalk with a 1 way bus?

I'm working on a DDR memory circuit, and I'm not sure how big an issue crosstalk is on the command/address bus. I've designed for crosstalk with the DQ/DQS and CLK lines because they are high ...
3
votes
1answer
286 views

SPI routing question…Maximum length SPI can be routed

Basically my question is regarding maximum length of SPI routing, and route efficiently in my scenario and any timing issues(Setup and Hold). I am just explaining my scenario. Please bear with me, it ...
0
votes
1answer
100 views

Do I have to equate clock and Data Bus propagation delay for Transmission Lines?

My question is about SDRAM timings for clock and DataBUS. Som designer advice that clock pin has to be the shortest one. Data Bus may be longer than these because of the some problems. But clock trace ...
3
votes
2answers
435 views

Ground vias on high speed PCBs

I know that if I use vias on high speed traces that I need to reduce the inductance effect of the via. So I will put ground vias next to these vias to help returning current. I have seen a picture ...
6
votes
2answers
302 views

Returning Currents for two side boards and returning current questions

I have some questions these are I am not sure: I have designed a board that has classical 2 side PCB design. Frequency is not a big issue for me but with ESD my CPU resets itself. (CPU clock 20 Mhz, ...
5
votes
2answers
164 views

Can I slow a CMOS output through an RC filter?

Is it good practice to slow down the slew rate of a CMOS output by putting an RC filter on it? What happens with impedance matching after I do this? Or can I just set the RC filter with such a low ...
4
votes
1answer
410 views

When scoping the CLK and DATA lines of a PS/2 keyboard it looks… rather odd

Normally if I look at a digital signal I see a nice, relatively sharp pulse train on the screen, but when scoping the outputs of a PS/2 keyboard things get a little weird and I'm not sure what it ...
2
votes
1answer
768 views

Does transmitting break over FTDI chipset yield a binary 0 received on the receiving end?

I send breaks (using Tx) over FTDI FT232R chipset using two ways: ...
6
votes
2answers
1k views

False Positives on Arduino Input

I've used analog and digital input for a multitude of applications with the Arduino Uno board. It has continuously given extremely non reliable readings, where the analog input is always fluctuating, ...
3
votes
2answers
293 views

Packet loss in CAN

How susceptible is a CAN bus to packet loss, and what are the sources of packet loss in CAN? I realize the answer may depend heavily on the application, so here are some details: bus length: about ...
12
votes
3answers
2k views

What problems could occur when chaining 40 shift registers?

I'm planning on chaining together 40 x 74HC595 shift registers. The whole chain of 74HC595s will be controlled by a 5 V microcontroller, which will generate the ...
2
votes
3answers
773 views

The resistance between the 1.2V rail and GND is 40 Ohms, is it safe?

I have a power supply board that supplies a DSP, FPGA, CPLD and other components of a system. When I measure the resistance between power rails and GND using a multimeter I get the following readings: ...
2
votes
2answers
225 views

Determining parity or FEC (Forward Error Correction) requirements from percent error

I am very new to signal processing and my background is in physics. I would like to know if it is possible to determine the number of parity bits needs to theoretically get 100% transmission from a ...
9
votes
4answers
545 views

Why do some of my signals 'shiver' (have jitter)?

I have a 2 MHz SPI bus but one thing I've noticed that is that some of my signals often 'shiver'. Yes my trigger is setup properly so I don't think the issue lies there. You can see what I mean here: ...