Questions regarding how to properly ensure Signal Integrity, protection from noise, shielding, proper pcb layout.

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0answers
27 views

How to calculate wiring tolerance when dealing with high frequency signals

guys. I am designing a DA board that treats digital signals up to 300Mhz. What I learn from book is that I have to concern signal integrity problem when the signal is quicker than 100Mhz. So I plan to ...
1
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2answers
69 views

Avoiding crosstalk between makeshift wires

My setup is as follows. I have 6 foot long 22-gauge wires connecting pin headers of an audio codec eval board and an FPGA daughterboard. I am sending an 8KHz and 128KHz clock signals and a data signal ...
0
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0answers
39 views

Close Vias cause a Signal problem on high speeds?

I have designed a 4-layer board (signal + GND + PWR + signal). Have an SDRAM (using it about 80MHz). My stack up is: ...
1
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1answer
58 views

Will software-based DSSS work?

We are implementing a 2.4 GHz RF link using a TI CC2541 chip (http://www.ti.com/product/cc2541) and we are new to RF design. We want a robust, low-bandwidth, low-latency link. We were thinking of ...
3
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3answers
84 views

Returning Current on power planes? (High frequencies)

For a 4-Layered design (Signal-Ground-Power-Signal): I wonder that, I need both bottom signal layer and top signal layer for high frequency signals. I will use both of them for my high frequency ...
2
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2answers
205 views

SDRAM problem with LPC1788

This is my PCB layout: My problem is: When i tried to Access SDRam with my example code (Memory test Code) everything seems ok. All the SDRam Data changes what i need. But when i tried to Access ...
3
votes
1answer
100 views

Return Paths of Signals on Flat Flex Cable

I have a 4 layer PCB with a typical stackup (signal-gnd-vcc-signal) and on the top layer there's a CMOS sensor connected with a flat flex cable... I was wondering, since there's no reference plane ...
3
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1answer
194 views

How does the DDR clock compensation capacitor improve signal quality?

I saw in some DDR3 designs that there is a capacitor between differential clock lines, for example the image below: In the document this image comes from it says: On the DDR3 SDRAM DIMM, there ...
1
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1answer
102 views

RS-485 / CAN signal levels

From what I know, CAN at the physical layer in the "recessive" state just lets pull-up/pull-down do the work. Does that mean the rise time is theoretical slower than a RS-485 transceiver? And about ...
2
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5answers
160 views

Pulse counting affected by oscilloscope probe

As shown in the block diagram below. I generate a 128KHz clock and a stream of known number of pulses in 10msec (the 10msec timer is implemented in the pulse counter by dividing the 128KHz by 1280) ...
2
votes
1answer
89 views

How to ground pins on a multilayer board with a ground plane?

Let's say I have a multilayer board with a single dedicated ground plane. Should I place all the grounds directly to the plane with a via as close as possible to the pin/pad or should I be looking ...
3
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2answers
216 views

SPI multiple slave termination

I've been reading about signal integrity and went through this site reading about it as well as other references. Alot of the topics deal with a single slave, but not so much multiple slaves. I'll be ...
10
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1answer
421 views

Why does reflection off a PCB via look like this?

My question is related to http://mobius-semiconductor.com/whitepapers/ISSCC_2003_SerialBackplaneTXVRs.pdf. On the page 18 there are a few figures of "TDR off Diferent Types off Vias". I am confused ...
5
votes
1answer
239 views

On referencing power planes and return current paths

I recently worked on a 16-layer board design that contained only 2 ground planes, at the outer layers of the board, and several power planes (+1V1, +1V8, +3V0, +5V0) in the middle: Since there are ...
2
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1answer
188 views

Benefits of top and bottom ground pour in multilayer boards with proper ground plane layers and stackup

I'm trying to get some analytical feeling for the use of ground pours on bottom and top layer in multilayer boards with proper stackups such as (for example). Top Gnd Sig1 Power Power Sig2 Gnd ...
3
votes
4answers
769 views

PCB Signal Bus design

I have a pcb with a SPI bus with several sensors that have to be connected to this bus. Since 90 degree traces are not recommended in a proper PCB design I ask myself how to connect so many sensors ...
2
votes
2answers
170 views

How should I check USB signal integrity?

I'm using 2 USB hubs chained together to hook up my phone to the computer to do some testing stuff. How can I check if the USB signal is being good or not? I tried scoping the USB pins with the USB ...
3
votes
3answers
137 views

understanding transmission line signal integrity through simulations

I need to simulate how signals are reflected based on the source, load and line impedances and how the signal integrity is effected by the spacing between different traces on a board, traces on the ...
8
votes
1answer
400 views

What separates a “good” eye diagram from a “bad” one?

I'm running some USB verification testing at work, and the Agilent oscilloscope I'm working with returns a nice summary of pass/fail statistics along with a pretty eye diagram. Since the pass/fail is ...
2
votes
1answer
249 views

Detect logic signal in a long distance. What type of interface to use?

My daughter board uses a comparator(LM339) to output logic 1 or 0 under a 3v3 supply. The cable connecting daughter board and main board is at least 1.5m. Luckily, the frequency is not fast but the ...
1
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2answers
106 views

Resistance between data/Addr pins and GND ranges from 1k to 1M, is this normal?

After soldering a 132-pin surface mount DSP, I checked if there are short circuits or not using "GreenLee DM-110" multimeter. I found that the resistance between data or address pins and GND ranges ...
1
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0answers
76 views

Analysing Signal quality through pogo pins using Hyperlynx

I have successfully modeled Linesim and boardsim schematics for quite a few designs in the past and we have been able to do the required SI simulations. I had one question though: On one of our ...
1
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1answer
82 views

Do I have to worry about backwards crosstalk with a 1 way bus?

I'm working on a DDR memory circuit, and I'm not sure how big an issue crosstalk is on the command/address bus. I've designed for crosstalk with the DQ/DQS and CLK lines because they are high ...
3
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1answer
239 views

SPI routing question…Maximum length SPI can be routed

Basically my question is regarding maximum length of SPI routing, and route efficiently in my scenario and any timing issues(Setup and Hold). I am just explaining my scenario. Please bear with me, it ...
0
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1answer
82 views

Do I have to equate clock and Data Bus propagation delay for Transmission Lines?

My question is about SDRAM timings for clock and DataBUS. Som designer advice that clock pin has to be the shortest one. Data Bus may be longer than these because of the some problems. But clock trace ...
3
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2answers
222 views

Ground vias on high speed PCBs

I know that if I use vias on high speed traces that I need to reduce the inductance effect of the via. So I will put ground vias next to these vias to help returning current. I have seen a picture ...
6
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2answers
229 views

Returning Currents for two side boards and returning current questions

I have some questions these are I am not sure: I have designed a board that has classical 2 side PCB design. Frequency is not a big issue for me but with ESD my CPU resets itself. (CPU clock 20 Mhz, ...
5
votes
2answers
143 views

Can I slow a CMOS output through an RC filter?

Is it good practice to slow down the slew rate of a CMOS output by putting an RC filter on it? What happens with impedance matching after I do this? Or can I just set the RC filter with such a low ...
4
votes
1answer
344 views

When scoping the CLK and DATA lines of a PS/2 keyboard it looks… rather odd

Normally if I look at a digital signal I see a nice, relatively sharp pulse train on the screen, but when scoping the outputs of a PS/2 keyboard things get a little weird and I'm not sure what it ...
2
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1answer
555 views

Does transmitting break over FTDI chipset yield a binary 0 received on the receiving end?

I send breaks (using Tx) over FTDI FT232R chipset using two ways: ...
5
votes
2answers
839 views

False Positives on Arduino Input

I've used analog and digital input for a multitude of applications with the Arduino Uno board. It has continuously given extremely non reliable readings, where the analog input is always fluctuating, ...
3
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2answers
212 views

Packet loss in CAN

How susceptible is a CAN bus to packet loss, and what are the sources of packet loss in CAN? I realize the answer may depend heavily on the application, so here are some details: bus length: about ...
12
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3answers
1k views

What problems could occur when chaining 40 shift registers?

I'm planning on chaining together 40 x 74HC595 shift registers. The whole chain of 74HC595s will be controlled by a 5 V microcontroller, which will generate the ...
2
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3answers
568 views

The resistance between the 1.2V rail and GND is 40 Ohms, is it safe?

I have a power supply board that supplies a DSP, FPGA, CPLD and other components of a system. When I measure the resistance between power rails and GND using a multimeter I get the following readings: ...
2
votes
2answers
184 views

Determining parity or FEC (Forward Error Correction) requirements from percent error

I am very new to signal processing and my background is in physics. I would like to know if it is possible to determine the number of parity bits needs to theoretically get 100% transmission from a ...
9
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4answers
445 views

Why do some of my signals 'shiver' (have jitter)?

I have a 2 MHz SPI bus but one thing I've noticed that is that some of my signals often 'shiver'. Yes my trigger is setup properly so I don't think the issue lies there. You can see what I mean here: ...
10
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2answers
2k views

Why are vias placed this way on a PCB?

I used to check complex commercial PCBs specially those of graphics cards to see how professional PCB designers do their layout and learn from their techniques. When I checked the card shown below I ...
2
votes
2answers
445 views

Signal integrity at 40 MHz with parallel signals

I have to design a board with an 8 bit parallel port that carries 40 MHz signals. It is not possible to wire them very short and in parallel (I am sure the wires will be about 7 cm long), so I have to ...
4
votes
2answers
357 views

Routing considerations of analog signals on twisted pairs

I'm designing a part of a system that will receive 4 analog signals carried on 4 twisted pair cables which are input to an ADC. These signals are low speed (probably in KHz) bipolar ranging from -10V ...
0
votes
1answer
293 views

How to reduce voltage from a high speed buffer?

I am using this buffer to connect signal between 2.5 V and 5.5 V to a 3.3 V microcontroller. The problem is I will get a 5 V output and my microcontroller doesn't have 5 V tolerant inputs so I have ...
2
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2answers
408 views

How can I meet these PCB design conductivity/isolation requirements?

The specifications required are as follows: The resistance between ground pins on a connector and the case (chassis) ground should be less than 3 Ohms. The resistance between any other signal on the ...
18
votes
4answers
2k views

Short Distance Board to Board Communication

My MCU runs a SPI bus with about 4 devices. I'd like to extend this bus to be off board as well i.e. have some PCBs connect to the "main" board and extend the functionality. The "pad to pad" distance ...
10
votes
3answers
826 views

SDRAM Prototype vs Production Woes

I have a design using an LPC1788 together with a SDRAM module from ISSI (IS42S32800D). This is a 32bit interface. I have routed this design out and had a prototype made with a PCB manufacturer that ...
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vote
4answers
184 views

Sinusoidal Waveform Induced on Long (~15m) Wire

I have about 72 of the following circuits on my board. The MOSFET and R2 comprise of the output stage and the pull up resistor is my input stage. The long length of wire in-between is the wire under ...
5
votes
3answers
600 views

Increasing Fall/Rise Times for Signal Integrity

I have a board that tests a wiring harness' continuity by outputting a set of test vectors onto the harness and reading it back. The wires in the harness can be as little as 1 m and as large as 10 m. ...
0
votes
2answers
874 views

Highly asymmetrical rise and fall times

I'm using a MOSFET to buffer my signals from a CPLD. The signals travel external to the PCB using long (from 1m to 10m) wires and then come back to the same PCB - the wires are actually the component ...
1
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2answers
364 views

System Clock Ringing

I have a 8 MHz oscillator that I run to two CPLDs on my board. The trace lengths are less than 1.5 inches. The traces do you have vias in them, so they do change their impedance. But I was hoping that ...
3
votes
2answers
493 views

Why the measured voltage increases when I change ground reference?

The following image shows my connections: The grounds of all devices are connected to a common PCB. When I measure the 1.2V referenced to the ground on my PCB, it reads 1.201V which is great. But ...
2
votes
4answers
588 views

What's the Actual Speed in GHz of RapidIO or RocketIO serial interfaces?

When reading about high speed serial interfaces like RapidIO or RocketIO, I find data rates of 3.125 Gigabits/second and more. My question is: 3.125 Gb/s = ?? GHz What's the relation between Data ...
14
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2answers
794 views

How to transmit high current (2.6A) with low voltage (1.2V) for a long distance?

I want to supply a DSP with 1.2V. This DSP needs 2.6 Amps of current at full load. The minimum supply based on the electrical specs of this DSP is 1.16V, which means that the maximum voltage drop ...