Questions regarding how to properly ensure Signal Integrity, protection from noise, shielding, proper pcb layout.

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1answer
84 views

Separating Two High Speed Digital ICs

Previously, I've designed a PCB incorporating this ADC chip. It has a digital bus of 10 signals some of which are 40MHz. Right now we have a four layer PCB and the ADC is connected directly to a ...
5
votes
1answer
80 views

Disadvantages of Schmitt Trigger Inputs

I'm familiar with the utilization of Schmitt Triggers when interfacing with low slew rate signals / sinusoidal waveforms. In a recent design, I've been scrubbing our FPGA I/O configurations and ...
0
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1answer
47 views

SD Card Trace Inductance and Capacitance

Most (if not all) SD card datasheets contain the following requirements, which I gather are copied from the standard: 16nH max trace inductance for f < 20 MHz 40pF max line capacitance Two ...
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4answers
397 views

Dealing with signal noise over 50 foot communication link

Situation: Connecting a motor controller to an MCU. Motor controller is about 50 feet away from MCU. Connected via a single conduit (buried), containing the following cables: (There is no other ...
0
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1answer
58 views

What is causing this distortion on a 20MHz control signal?

I'm having an issue with a PCB on which I have a microcontroller and an external SRAM. I don't want to fully describe the problem as I already posted a question regarding that. Link Since that I ...
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vote
2answers
139 views

Signal and power integrity - 4 layer board

Let's assume that we need to design Mixed signal PCB with 2 fast integrated circuits(tr_min = 1ns) operating at different voltage levels(3.3V and 4V). There are however other voltage levels on the ...
5
votes
2answers
497 views

Do I need a via or stitching cap when I transition between physical reference planes of the same potential?

I have the following layer stack up Signal Ground Signal Power Ground Signal Ground Signal Layer 1-2-3 are tightly coupled Layer 4-5 are tightly coupled Layer 6-7-8 are tightly coupled Total ...
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vote
1answer
45 views

Why is the input pin to my multiplexer considered a capacitive load?

I am currently using CD74HC4067 multiplexer in my design. I had trouble with my input signal and therefore conducted an experiment by measuring the input resistance of my multiplexer as the frequency ...
2
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4answers
93 views

purpose of termination resistor

My question is not about a particular bus or line and the termination I should put on it. I know some busses need termination resistor like CAN or adress/data for memories. If I understood well these ...
2
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1answer
60 views

No driver IC on net in Hyperlynx problem

I am getting the 'no driver IC on net' problem in Hyperlynx signal integrity software. Does anyone have any idea bout it? This is my PCB: It has an SMD connector and an AD9767 DAC. I have added the ...
3
votes
1answer
95 views

High-Speed PCB Design - Routing on Power Plane Layer?

I am working on designing my first high-speed PCB with 4 layers (in order): Top Layer: Single-ended/TTL signals Internal Layer 1: Power Plane (3.3V) Internal Layer 2: Ground Plane Bottom Layer: ...
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1answer
33 views

Predicting bit error rates for RF communications [closed]

I am trying to estimate what the approximate bit error rate for a given antenna configuration would be. Specifically, suppose I have two parabolic dish antennas pointed at each other. If they are ...
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0answers
63 views

How to reduce SPI bit errors between a Bus Pirate and a BIOS chip?

I need to eliminate bit errors when reading a BIOS chip using a Bus Pirate v3.6. The BIOS chip is still soldered onto the motherboard. I'm using a Bus Pirate probe set to connect the Bus Pirate to a ...
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votes
2answers
71 views

Should we try to match the differential impedance of a CML pair, and if so, why?

Differential signalling 'traditionally' involves two conductors carrying equal and opposite signals, the data being signalled by the polarity. In this arrangement the majority of the current returns ...
7
votes
3answers
886 views

Does this layout ever make sense to do?

Let's say I've got an power output and I want to power a chips Vin's with it. But, let's say it's a couple of different digital Vcc's on the chip that I want to power, like a rail for an LO, a rail ...
3
votes
1answer
203 views

how to split audio with buffers?

I am split an audio signal coming from an op amp to both a line driver buffer and a VU meter buffer, as shown in the schematic. My trouble is in determining the correct placement and value of ...
1
vote
1answer
44 views

Find Power Spectral Density of given signal

I am given a question with very brief notes to study from. The question is this: Now I was wondering, are the following part of the notes relevant at all: Is this the appropriate method to solve ...
5
votes
3answers
1k views

Why does the capacitance on a line disappear when properly terminated?

Came across an Adafruit interview with the one and only Paul Horowitz and he said something interesting. Part of interview thats related to this question He said in more or less words that the ...
2
votes
2answers
70 views

Issue with circuit design 10x probe

I designed a board to mux 16 inputs into a 4 channel scope using relays. I also included circuitry to replicate a 10x probe on the board. That is, I placed a 9M ohm resistor in parallel with a 1.4pF ...
2
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3answers
108 views

How to terminate switching transistor for level change?

For a typical driver, I would add a series termination resistor to terminate the line. But what would be the correct way to terminate when a transistor is used to level shift a 3.3V/5V signal to some ...
1
vote
1answer
102 views

Why does cable length matter so much when source is high impedance?

My beginner’s electronics book has now started to teach me about microphones, specifically Electret microphones. While searching the web for more info, I stumbled upon an article where the author ...
15
votes
1answer
379 views

PCIe, diagnosing and improving an eye diagram

I have implemented a design that uses PCIe. It is somewhat different in that the PCIe interface is used as a chip-to-chip communication lane on a single PCB (e.g. no PCIe connector). The root ...
0
votes
1answer
57 views

How do I determine if the clock signal suffers from high speed effects

I need to determine if the clock signal inside a multichip module shall suffer from high speed effects i.e reflection and ringing. I have: (1) IBIS models of the components inside the multi-chip ...
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2answers
75 views

Where do all the PDN capacitors sit?

I have my voltage rails coming off board and I have quite a number of ICs. Each has their own decoupling and for the really demanding ICs I have a bulk capacitor. If I have some target impedance and ...
1
vote
1answer
141 views

Trace Dimensions limitation for JTAG signals

I have a JTAG bus that I need to go over PCB (or could make cable) for about 12 inches. I am trying to figure out the signal integrity specs for the JTAG bus ... what trace width vs. trace length I ...
2
votes
2answers
209 views

Is it possible to physically measure the input and output impedance of a component?

Input and output impedance is an important property of complex electronic components. Is it possible to physically measure them like we measure resistance? Is it possible to measure it for BJT based ...
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2answers
1k views

Physically, what is and how to, make an anti pad?

Consider the following later stack (it's only the top 3 layers of an 8 layer board) Top Signal Layer Plane Signal Layer I have a high frequency trace that is being routed on the top layer and I ...
0
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1answer
62 views

How subtle or dramatic are the effects of a impedance mismatch by a certain percentage?

If a trace is designed to be 50 ohms, how much of an effect would 10% or 20% mismatch between line impedance and termination values ? For instance, a 50 ohm line with 45 ohm or 55 ohm series ...
5
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1answer
196 views

SPI Bus Termination Issue

I've been working on a project where an OMAP Linux SPI master interacts with 6 SPI slaves peripherals (5x A/D converters and single magnetometer). I can set the SPI clock frequency and have ...
3
votes
4answers
1k views

Return path on a PCB

I've spent the weekend absorbing video lectures from Eric Bogatin and reading his book "Signal and Power Integrity - Simplified" He states that the the return path for the PCB may be any DC plane ...
0
votes
1answer
159 views

5V TTL signals over 4m or so?

Adding input and output capacitors either side of my 5V DC-DC converter doesn't seem to help much, and I'm wondering if some kind of signal interference might be my problem. I'm running signal from a ...
0
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2answers
189 views

Trace termination length limits

Are there any length limits to series termination ? If I have a trace that's 12 in or a trace that is 100 in, can the same series termination resistor be used (assuming that Zo = 50 ohm) ?
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3answers
247 views

Height of the substrate in online PCB impedance calculators

Is the height of the substrate just the non conductive portion between copper layers ? Using this calculator as an example In a 4L board, if the top and bottom traces are of the same thickness and ...
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2answers
205 views

Understanding capacitive load conditions for a microcontroller

This is from a PIC24E microcontroller datasheet. My question is understand what does "load conditions for device timing" mean ? Does it mean in order to maintain timing (say for a high speed PWM ...
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3answers
199 views

How to select source termination resistors by looking at signal?

If I have two devices that some distance apart on a fairly large PCB (could be 1 in, or it could be 20 in). If I arbitrary select a value for R1, lets say 33 ohms in this example and if my digital ...
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1answer
55 views

How to setup PCB to correct for signal integrity issues after boards are made?

I have a board layed like the in the image below. I have a microcontroller that generated clk1, which feeds into U1. After 8 clock cycles, the clock passes through to U2 and does this 30 times. It's a ...
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2answers
135 views

PCB via, increase annular ring or increase hole size?

I have to use via to route small analog signals. If I want to minimize the effect of via on the signal, should I increase the annular ring size or hole size. Lets say the total via diameter is same in ...
0
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1answer
86 views

Is TMDS really differential?

TMDS (Transition Minimised Differential Signalling) is a nominally differential signalling specification used, for example, in DVI & HDMI. Today though I was reading Brooks' Signal Integrity ...
0
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4answers
2k views

What are the main causes of Overshoot and undershoot of a signal?

I'm not an EE major, but I was curious what causes overshoot and undershoot. Where can i find a detailed explanation of the process? I heard it has to do with the parasitic capacitance, but there ...
3
votes
2answers
117 views

How can you auto-calibrate a conductance sensor?

Sensors need to be calibrated every so often, so that the voltage/current change due to the change in the conductance is always the same, and the signal conditioning of that voltage/current is always ...
1
vote
1answer
58 views

I have read that a design which fails signal integrity shall have EMC issues

I have read that if a design has EMC issues and is emitting a lot of radiation, then there is a relationship with some signal paths not being properly terminated and/or there being signal integrity ...
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2answers
65 views

transmission loss with microsd extender

Would a 20-30cm microSD extension cord suffer any kind of noticeable transmission loss? This is a passive extender - literally, a microsd card with wires coming off of it, and a card slot at the other ...
0
votes
1answer
112 views

Do we ever use the pin capacitance of a digital circuit component (e.g ASIC, FPGA) in doing timing or data integrity analysis

As far as I understand, the pin capacitance on say an ASIC or FPGA effects the rise and fall time of the signal on it. It is also possible that the impedance offered by this capacitance to a very high ...
4
votes
1answer
500 views

How can I determine a maximum run length for CANbus?

I'm using CANbus to communicate between two circuit boards. 120 ohm termination resistors on either end. Transceivers are MCP2561 and ISO1050. Bit rate is in the hundreds of kilobits/second. Medium is ...
0
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2answers
106 views

Why is the data rate a function of the length of the transmission line?

The length of a transmission line is limiting the highest possible data rate on that line. Why are faster signals more likely to become corrupted on long transmission lines than on shorter ones, with ...
0
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1answer
166 views

SPI Bus Clock Slew Rate

I am interfacing LPC1768 SPI bus and SST25VF016B SPI Serial Flash. Flash is 50Mhz, and these are the values I copied from SPI Flash Datasheet. page 24. FCLK (Serial Clock Frequency) 50 MHz TSCKH ...
3
votes
1answer
815 views

RMII MAC side routing and signal integrity

I have some signal integrity and EMC questions. In my board LPC1768 RMII interface is connected to LAN8720. Because of pin locations some RMII signals must go through bottom layer. This is a four ...
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1answer
60 views

Suggest FEC technique

I am a novice in signal processing so there may be a fundamental gap in my understanding of the concept. I am working on a link which has an error of 1 in 1000 bits which I have to improve to 1 in ...
4
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5answers
653 views

Why does differential signaling send complementary signals instead of just pairing the input and ground voltage?

I'm very new to EE, so please excuse me if this question is bad or has an obvious answer. After reading an overview of differential signalling, it left me wondering: Why does differential signalling ...
5
votes
1answer
465 views

DDR bus design review

In our last build we had issues with DDR stability in our prototype, simply because of lack of experience with this type of high speed memory connections. We managed to get it working with halving the ...