About tools to simulate circuits. Specify the tool used.

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40 views

Representing an equation with a simulation of Operation amplifier adder

I am trying to represent an equation (Vf=-3V1+7V2+2) using operation amplifiers. The schematic that I did is: simulate this circuit – Schematic created using CircuitLab but I have ...
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31 views

Circuit simulation software with good animation capabilities? [on hold]

I am an electrical engineer working in the Railway industry. I teach electrical wiring diagrams and circuits of various train subsystems to technicians and engineers. I need a circuit simulation ...
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17 views

How to Simulate 10w LED packages in Circuit Lab

I've been messing around buying random electrical components from China and I came across these 10w LEDs and, after seeing how bright just one was when supplied with 12v at 900mA, now I'm looking for ...
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32 views

Looking for “Model” of the L200, ideas? [on hold]

Since i want to build a power supply based of the L200 i want to simulate it first using multisim. The problem is that multisim doesn't have the L200 in their database. So I'll have to make one ...
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16 views

How to infer equivalent PID controller coefficients from an existing black box ccontroller?

I have a 2 input, 2 output system that I have recorded in response to 1. steps (actually quasi-steps, with 50 ms rise time + some overshoot), and 2. sine waves from 0.5 to 50 Hz, in both open and ...
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12 views

CMOS Transient Simulation in Silvaco [on hold]

I'm trying to get the current vs. transient time for a Bulk CMOS ( inverter ) using Silvaco simulation. So what I did is that after I fabricated the CMOS device, I added a load capacitance to the ...
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39 views

Model Sim Software with VHDL, What is Wrong?

I wrote the following VHDL Code: ...
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1answer
35 views

Audio Amplifier Design (CE Amplifier - Class AB Power Amplifier)

I am trying to design a Audio Amplifier which provides a gain of 20db (10V/V). I have managed to design the following circuit but the output voltage gets clipped and clamped. Please find the schematic ...
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2answers
33 views

CE Amplifier Design for Audio Amplifier

I am trying to design an audio amplifier which provides a maximum gain of 20dB (or) 10V/V . For the circuit I designed the lower half of the amplified signal is being clipped. I am also attaching the ...
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1answer
52 views

Why Can't I get a Smooth Sine Curve in PSPICE

I am trying to simulate a Volume Control Circuit in PSPice Student Edition. I am unable to see a smooth sine curve at the output. Could you check my circuit. Find the Schematic below Thanks
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34 views

Open source PID simulator

I have been searching for a open source PID simulator (kind a advanced PID simulator).Are there any free open source PID simulators available on internet?
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1answer
50 views

Why this concept in VHDL doesn't work?

I want to make a simple processing element for calculating the absolute difference between two 8-bit words. However, this element may be used as part of an array in order to speed up the AD ...
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1answer
32 views

Showing negative numbers in Verilog

I am writing a program for a 16-bit ripple carry adder and stumbling a little at the end. When I run my code (which includes negative numbers), it's doing the math right, but giving me all positive ...
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19 views

circuit/multisim troubleshooting

I can't seem to get an output wave to appear. Can anyone see anything wrong? Or are my values off, like the capacitors?
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1answer
33 views

How to simulate a n-p-n bjt using Cadence Virtuoso?

I had been simulating CMOS transistors using Virtuoso, in which I had used ami06n as model and NCSUanalogParts as library. But for a BJT, when i tried simulating through ADE-L using this config, it ...
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1answer
45 views

Simulating a Constant Temperature Anemometer

I am trying to simulate the results I see when using a constant temperature anemometer circuit to sense air flow. An excellent discussion can be found: arduino thermal anemometer. Here is my ...
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1answer
11 views

Disambiguation of AC Analysis and Small Signal Analysis

I am trying to understand Small Signal Analysis (SSA) for Diodes and BJT transistors through different textbooks but I have some issues. Is AC Analysis the same as SSA? I have seen hints that imply ...
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1answer
28 views

How is MOSFET modelled in DC analysis?

I am wondering how simulator (LTspice, Cadence,...) compute DC operating point of MOSFET in DC analysis. I know that in DC analysis, capacitors are open and inductors are short. With MOSFET how is it ...
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27 views

Error in 'Multisim' when connecting two op amps in cascade

I've connected the circuit below (wien bridge oscillator) and simulated it using Multisim: The results were expected: a sinusoidal wave of 1.2 Vp-p. I wanted to amplify this resulting signal, so I ...
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59 views
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27 views

Half Wave Voltage Doubler Simulation stuck

I'm trying to simulate the following circuit on LTSpice simulate this circuit – Schematic created using CircuitLab The capacitors have 10Meg Parallel ...
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42 views

LTspice IV ir2110 H-bridge simulation wierd behaviour

I want to simulate H-bridge using LTspice. At some point Ho stops working correctly. I am using ir2110 typical connection as schematic. This si up to the point where is it working ( but schematic not ...
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18 views

display the output of a MATLAB simulation model for an induction machine in space phasor illustration

Hello, do any one know, if is it possible to display the output of a simulation model in MATLAB with the space phasor illustration? (in german: Raumzeigerdarstellung) as the picture shows: I have ...
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27 views

Is it possible to simulate complex systems on desktop? [duplicate]

Disclaimer: I'm an experienced software dev, but I am just dipping my toes into embedded, I'm definitely out of my depth, so please be gentle :) I'm working with a team creating a simple IoT device. ...
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3answers
80 views

Input/output impedance of microcontroller

how to calculate the input and out put impedance for a micro controller , for the purpose of modeling in LT spice , for example RX610 family from Renesas For example the lumped characteristics can ...
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1answer
119 views

AD620 in Proteus: timestep too small

I've made this circuit in Proteus, as a part of a practice report: In real life it works, as I built and tested it. But in Proteus, when I want to run the simulation, I get these errors: ...
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1answer
45 views

simulating a electrical transformer

My goal is to program a FDM simulation of a transformer. So, we have the coupled inductor model to start with ... However, if L1 = 1, L2 = 9, and coupling is perfect then M = sqrt(1*9) = 3 and L1 - ...
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20 views

Event Debug Mode error when performing mixed Verilog/VHDL simulation in VCS

I am getting the following error: ...
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0answers
85 views

Two different ways of writing the same thing but generating different behaviours in Verilog

I have a part of Verilog code that is basically trying to synthesize a flip-flop. I have been experimenting and it seems that I can come up with two ways of writing it. The first way being : ...
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1answer
24 views

Adafruit Anemometer

Recently I bought an anemometer from Adafruit. I was wondering is there is any way or approach which I can simulate the sensor for measuring the wind speed. If there is any software able to simulate ...
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36 views

Orcad Capture add component via Breakout library

I want to link an IGBT .mod file to the model provided by the breakout.lib (ZbreakN) of Orcad Capture. I added the component of the breakout library, right-clicked, 'Edit Pspice model' and then pasted ...
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2answers
72 views

How to debug FPGA designs

This is supposed to be a followup to my previous question how to get a FPGA design that will definitely work on actual hardware. I have made a lot of progress since I asked the above question (thanks ...
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109 views

Proteus 8 stop showhing Simulation errors tab

When running a simulation then ending it, the "Simulation errors" tab appear automatically, and that's a bit bothering because it takes all the window, and I have to close it everytime. Is there ...
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41 views

Read file in hex vhdl

I'm designing an ALU that does several logic operations. I created a testbench and all the function works fine. Now I want to make the testbench read from a text file and write the value in a ...
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1answer
91 views

What are common EE computer tasks? [closed]

I am an electrical engineering student looking to build a desktop computer. That being said, I would like to configure it to run common EE tasks as efficiently as possible. Therefore, I am trying to ...
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1answer
38 views

Find cutoff frequency of a common emmitter amplifier

simulate this circuit – Schematic created using CircuitLab I need to find the cutoff frequency of this common emmitter amplifier. Is it possible to simulate a bode plot?
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13 views

Spice mosfet, user selectable parameters ires, cox, pox, vtn from a 3rd party model

I have a spice model for the part ald1103 from advanced linear devices that contains parameters to be filled in by the user, presumably to support custom ASICs using transistors from this ...
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1answer
67 views

NGspice 26 returns result that is 6 orders of magnitude too small for simple depletion MOS test jig

So, I'm trying to diagnose a simulation issue with the IXTT20N50D in CircuitLab, and created a very simple transfer characteristic test jig to do so: ...
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47 views

Plotting more than one voltage in LTSpice

I have a Spice netlist as follows. In this netlist, I want to plot V(3) and V(2) at the same time to the same plot pane. Writing only .plot v(3) or .plot v(2) can plot the corresponding voltages ...
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60 views

simulating coils with FEMM

To understand (and optimize) a circuit for wireless charging a bit better, I tried to simulate the tx/rx coils. There is a ferrite below/above the tx/rx coil. The peak-peak current is ca. 5A ...
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1answer
36 views

Simulation of BPSK in fading channels

I'm trying to simulate BPSK in a channel with Rayleigh fading and AWGN, then obtain the Bit Error Probability (BEP). My program is written in C. I compared my BEP vs \$\frac{E_b}{N_0}\$ (SNR per bit) ...
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1answer
79 views

How to simulate VHDL program without FPGA

I want to learn VHDL, and I wonder if I can find any tool that allow me simulate a VHDL program without having an FPGA. I do some search in internet, and I found this list of HDL simulators, but I ...
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1answer
93 views

Distributed Transmission Line, Characteristic Impedance in AWR Microwave Office

I am trying to design a distributed amplifier in which the parasitic capacitances of a small-signal FET model are linked to inductors to form a distributed line across the drains and gates and I'm ...
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3answers
64 views

Diode destroys square wave?

I was developing a footwell controller for my car, using RGB LEDs for the lights, an Arduino Nano for RGB controlling and an auxiliary PWM generator (pure white lights) when the Arduino is off. The ...
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26 views

How to use BSIM packages

I'm not quite sure what to do with the BSIM packages: http://www-device.eecs.berkeley.edu/bsim/ The package has basically benchmarks and source code. As for the source code part, if I just want to ...
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1answer
74 views

Verilog SPI module functioning in unpredicted ways

I am currently trying to implement a simple SPI Master module in Verilog using Quartus Prime Lite V15.1.0 Build 185 for compilation and Simulation Waveform Editor as my simulation tool. The module has ...
2
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1answer
72 views

Unexpected LTSPICE Output - Voltage Mode Buck Convertor

I'm trying to simulate in LTSPICE a simple buck convertor taking 34V -> 20V @ 2.5A and I'm not seeing what I expect. Here is my circuit and some waveforms: The top half of the circuit is the ...
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1answer
41 views

Keysight's Advanced Design System users, what's wrong with this simulation - II [duplicate]

As requested, I am forking a question as continuity to my previous inquiry from: Keysight's Advanced Design System users, what's wrong with this simulation? As such, this is not a duplicate. ...
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54 views

Keysight's Advanced Design System users, what's wrong with this simulation?

For those of you that uses Advanced Design System (ADS), from this circuit: Fundamental Frequency for transient simulation tool is set to 1GHz. Yet, I'm getting this output: Main question: Since ...