About tools to simulate circuits. Specify the tool used.

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1answer
40 views

Tips on linking SW and HW simulation.

I am total layman about this topic and I would appreciate experienced users to give me some useful tips and hints. I develop some code for arm cortex m0 which I want to simulate in ...
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1answer
35 views

Pspice simulation problem

What is a convergence problem? My circuit code is below and when I simulate it is saying that the NMOS transistors MPDA and MPDB are not converging. See the following screenshot: Here's the ...
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1answer
24 views

How can module TB trap $fatal from module A

I have an RTL simulation where module TB is the testbench for module A. Module A generates $fatal when it meets some condition it doesnt like. Module TB generates/collects transactions to/from A. Is ...
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0answers
25 views

how to solve this problem using powerworld simulator

∙ This 10 Bus Test Case is taken from the text book of Glover et al. . It is given as a design project to the students. ∙ This test case consists of 10 buses, 7 generators, 5 transformers and 6 ...
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1answer
26 views

Is it possible to have Altium ignore one schematic in a project?

I would like to start using Altium to simulate parts of my schematic, but I would much rather have a separate "simulation schematic" inside the project which should be annotated and compiled ...
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1answer
44 views

Why does iSim give a different result than hardware

I am working on a MIPS CPU for an FPGA - this is mostly a personal project to understand FPGA's. I have a 5 stage pipeline CPU implementation working correctly when run on iSim, however when I run it ...
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1answer
58 views

Input Characteristics of MOSFET in triode region?

When a MOSFET is operating in saturation region, i.e. \$V_{GS} > V_{th}\$ and \$V_{DS} ≥ ( V_{GS} – V_{th} )\$, the drain current equation clearly indicates the parabolic relation between the drain ...
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1answer
47 views

VHDL - Does signal ever get assigned in the same clk cycle?

This is my simulation I'm assigning different values to btnin my testbench ...
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2answers
51 views

Proteus ISIS Fast simulation

I want to display my output on 3 seven segment displays, I am doing that by serially switching them on and off. I have taken some help from here : ...
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0answers
20 views

How to carry out signal integrity simulation with IBIS models

I need to determine if there will be high speed effects on the clock signal. I have not done such a simulation before. I have the IBIS models of the circuit components involved. I think I still need ...
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1answer
51 views

Simulation error and output voltage drop of DC voltage doubler circuit in Multisim

I have simulated the circuit provided in this link:http://www.circuitdiagram.org/dc-voltage-doubler-multiplier-circuit.html. But, when I simulate the circuit, the output voltage is dropped and I get a ...
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1answer
30 views

Help in plugging equation in arbritrary current source LTSpice

I cannot plug in the following equation and parameters in arbitrary current source. Any help would very appreciated. ltspice cannot read my parameters..
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1answer
17 views

How to view voltage graph in simulink

I am trying to simulate Synchronous Buck DC DC converter I have created the circuit now i want to test it to check whether it is giving me the correct output or not , I have tried the same circuit in ...
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3answers
70 views

How to simulate an 8x4 memory using VHDL?

Why does this code: ...
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0answers
13 views

Simulate two-port networks in spice

I've been trying to simulate a circuit that includes a two-port network. While I was able to solve my problem using the T-model, I'm curious, how could I simulate a non reciprocal two-port network? I ...
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2answers
90 views

Can we simulate FPGA board?

As a part of my curriculum, I am required to implement a project on FPGA. However, even the cheapest available boards are out of my reach (blame currency conversion !) and besides, even if I buy one, ...
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2answers
54 views

How does a negative feedback amplifier reach steady state?

I tried to simulate a negative feedback non-inverting op-amp, and got incorrect results. I ran the following time-stepping code in python: ...
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0answers
58 views

How to simulate and initialise Block Memory ROM created using Xilinix CORE generator?

I created the ROM correctly using the CORE generator and the correct .coe file. There is supposed to be instruction words inside the memory (32*256). But the data bus out of the memory is always set ...
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0answers
15 views

EMC simulation using FEKO

I am trying to simulate a lens antenna using feko by illuminating it with a Yagi-Uda antenna radiation pattern. The problem is that the simulation can't be completed because radiation pattern (in ...
4
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2answers
75 views

Creating an Integrated Circuit Component in Altium

I am new to PCB designing and I am new to Altium. I want to make a schematic, PCB design and simulate a RF circuit involving a GPS receiver front end IC MAX2769. Altium library does not have this IC. ...
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8 views

Falstad circuit simulator not displaying text

I've been trying to run the falstad circuit simulator on firefox on elementary os luna, however I can't seem to view any of the texts, such as for selecting components and such. I can right-click to ...
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1answer
63 views

Can anyone explain why I get these results in OrCAD?

I am new user of OrCAD , and I have a problem in understanding the voltage shown in the red circle. By logic, the voltage of this point should be: $$3.3 \mathrm V \times \frac{5 \Omega}{5 \Omega + ...
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1answer
69 views

How to measure input/output impedance of amplifiers in a simulation?

What is the most effective way of measuring the input/output impedance of an amplifier in a simulation? When I know the impedance I want to measure is purely resistive, I usually set up an input ...
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2answers
96 views

Thyristor voltage regulator with different fireing angle for each period with simulink

First of all I'm really low with EE so please, go easy on me. As home assigment we have to design Thyristor voltage regulator in simulink. It should run for 5 periods with different thyristor fireing ...
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0answers
25 views

ltspice with large transistor array takes long time to solve

I have been working on a project to create several of the same T Flip-Flops with different components in LTSpice. The first uses the built in dflop object from LTSpice and the xor. I then moved to ...
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37 views

Complex system circuit design and simulation

I'm building a solar powered GPS tracking device using an Ieik Mini Nano V3.0 Atmega328p microcontroller board (based on Arduino Nano), Adafruit Fona GSM module, Ublox NEO-6M GPS module. The GPS ...
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0answers
23 views

PSpice Question (Wrong VAC IDC settings? iPRINT direction? or AC Sweep setting?)

I'm trying to use PSpice simulating this circuit: My drawing and setting are: But I think my result is wrong, which is: Looking at the answer of this question and using Matlab I get: I think ...
3
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1answer
52 views

Phasor simulation versus power flow

I have a basic question about the utility of a power-flow study versus a phasor simulation of a network. Here is a description of phasor simulation from the Matlab Simpowersystems manual "If, in a ...
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0answers
23 views

HSPICE subcircuit design problem

I want to design below circuit in HSPICE , Technique used is GDI . The Code is given below. ...
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3answers
83 views

Frequency response of a complex circuit

I am interested in finding the impedance as a function of frequency of the \$n^{th}\$ circuit in this series: simulate this circuit – Schematic created using CircuitLab (By request: this ...
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0answers
23 views

naming/wording of an introduced sub circuit ->interpose model

I have a question in context of of a naming convention. Imagine a schematic of electrical components (a netlist), where I want to change the behavior of one part by cutting the wiring and adding a ...
0
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1answer
78 views

Attiny10 not triggering timer overflow interrupt while simulation (Atmel Studio 6)

I have problems simulating the timer overflow in Atmel Studio 6. The code is for an Attiny10 and looks like below. As far as I know I set all the neccessary bits to enable the counter (which works in ...
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2answers
49 views

Is it possible to simulate hardware of MIPS architecture computer defined using Verilog/VHDL?

I am reading Digital Design and Computer Architecture book and if I will be persistent then I will have MIPS architecture computer at the end, implemented from scratch by me . I wonder is it ...
0
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1answer
21 views

How to achieve a block of Z^(-0.5) in Simulink?

I'm doing simulation in Simulink of Matlab, but don't know how to get a Z^(-0.5) cell like this:
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51 views

How to get change in position and rotation from gyroscope and accelerometer?

i have a 6-axis accelerometer and gyroscope MPU6050 . i'm using simulink with arduino to read to raw data from the mpu . I intend to measure something that only moves in the X and Z axis. I've heard ...
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19 views

Extract dynamic power Xilinx XPower

As i see in text books, Power trace of a design can be extracted using Xilinx Design Suit which show dynamic power vs. time. However trying to use Xilinx XPower and Power Estimator, it only shows ...
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2answers
53 views

How Verilog decides upon simultaneous events

Say we have a function, simple as f(x) = x. Say we have a clock that ticks every 20 nanoseconds, and say we change x as we wish. ...
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1answer
26 views

Post Map simulation reliability

I'm designing a module in VHDL for an FPGA. My module is added to already existing design. It has a Wishbone slave interface. The IDE (Lattice Semiconductor Diamond 3.2 ) allows to do post map ...
0
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1answer
27 views

ADG608 multiplexer acting really strange in Multisim

I am trying to use the circuit below to switch between multiple resistors using a multiplexer. Initially I had different values of resistors attached to every channel, but since I was getting very ...
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0answers
31 views

how to solve mosfet size match error in tanner 14.1 for 0.18um process

I have refer your answer for spice simulation. but it is not going with 14.1 version. please help me with respect to 14.1 version.
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0answers
71 views

simple inverter simulation in simulink

I am facing a weird problem simulating a rather simple inverter circuit in simulink. The schematic I'm working on is shown below. The oscillograms refer to PWM (a,b,c,d) and output which is 0! ...
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0answers
231 views

Incremental Conductance MPPT algorithm in MATLAB Simulink

I am simulating an application of the incremental conductance MPPT algorithm with a boost converter in MATLAB Simulink. The PV cell and boost converter have been modeled. I am facing problems while ...
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1answer
59 views

Edge detector issue

I've a stupid problem and I don' figure out how I can solve it. In my design I'm using a rising edge detector. The problem is that ActiveHDL doesn't simulate it in the way that I expect. The VHDL code ...
1
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1answer
26 views

3D device simulation of diode (static)

I am looking for a simple 3d software solving the drift and diffusion model for a diode in equilibrium. (Very simple abrupt p/n-junction - even without contacts. Purpose: teaching). I know Silvaco ...
0
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1answer
58 views

Vivaldi Antenna: size & max input power & software simulation

First, I've to say I'm a beginner in this field so please forgive me if my questions were not smart. I was reading about Vivaldi antenna and I decided to do an experiment; I'm going to use a flat ...
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0answers
61 views

Convergence problem in pspice but not in ltspice

I am trying to simulate a circuit in LTSPICE and it simulates without any convergence problems. However when I copy the netlist into pspice and try it simulate it I get strange results. It keeps ...
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1answer
59 views

Clipping circuit simulation producing unexpected result

I am playing around with a clipping circuit to protect a adc on my microcontroller. I beleive the following will work, but when I simulated the circuit I saw something funky. Any ideas on why adding ...
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0answers
20 views

how to make parameters as input port in Matlab?

I want to calculate BER in a communication system in Matlab simulink. I have used from "error rate calculation block", which accepts the transmitted and received signals as inputs and the output is ...
0
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1answer
33 views

Microstrip lenght problem

I'm simulating a single microstrip half-wave resonator (1.8 GHz) in Sonnet and using ADS LineCalc tool for calculating the microstrip length but I'm getting a wrong number. Substrate parameters ...
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2answers
111 views

Using iSim to simulate 16-bit CLA schematic on Xilinx, all inputs and outputs on the waveform are 'X'. How can I debug?

I'm building a sixteen bit Carry Lookahead Adder for my EE class. I'm definitely a noob to all this so bear with me, however I've been googling for a WHILE and haven't found any answers. Here is the ...