Newest 'spartan' Questions - Electrical Engineering Stack Exchange

2

votes

1answer

64 views

How do I buffer a high Frequency clock on a Spartan 6?

I am trying to create a high speed clock on my Spartan 6 Atlys Board. The onboard clonck is 100MHz. I am trying to use an on chip PLL to get a faster clock. I am using a the clocking wizard IP to ...

asked May 12 at 18:39

Lord Loh.
311112

4

votes

3answers

239 views

Minimizing Logic in a Spartan-6 for a Game of Life Cell

While trying to learn FPGA programming, I've decided to implement a massively parallel game of life. Here's my first attempt: ...

fpga vhdl spartan

asked May 3 at 0:45

Hugo S Ferreira
1376

1

vote

2answers

77 views

How to get MicroBlaze running on Papilio Pro

I am new to the FPGA world, and there seems to be gazzilions of boards and FPGA vendors. I just bought the Papilio Pro, which is based on the Spartan 6 LX9, and although I can already bitstream basic ...

fpga spartan microblaze

asked Apr 20 at 18:49

Hugo S Ferreira
1376

1

vote

1answer

68 views

Interfacing SJA1000 to Spartan6 FPGA

As the title says, I would like to interface an SJA1000 CAN controller to a Xilinx Spartan6 FPGA. The SJA1000 has a shared 8-bit address&data bus with an address latch signal and either separate ...

fpga vhdl memory xilinx spartan

asked Apr 3 at 2:34

Miral
1362

0

votes

2answers

105 views

How to implement Serial port RS-232 from 2.5V IO signal?

I am playing with a Xilinx Spartan-3A development (XC3S50A-TQ144C) and then I tried to implement RS-232 serial port by following the guide here: http://www.fpga4fun.com/SerialInterface.html I bought ...

voltage fpga rs232 spartan

asked Mar 30 at 12:47

wonghang
11

-3

votes

1answer

121 views

FPGA Image Processing [closed]

I'm looking into making an FPGA based image processing unit to do very basic function, like change brightness or something. Is there an easy, or well documented way, to interface a camera (something ...

fpga spartan imageprocessing

asked Mar 5 at 16:59

user1000229
1154

1

vote

1answer

137 views

What is state of port B when port A of FT2232H is in sync. FT245 mode?

I am designing Spartan 6 dev board with FT2232H interface, and I would like to use FT2232H to program AT45 flash with bitstream and then switch FTDI to FT245 mode and use 60MHz clock of 2232H as main ...

ftdi spartan

asked Jan 28 at 21:05

Bruno Kremel
1036

1

vote

1answer

385 views

Fixed Point Division in verilog for Spartan 6

I am developing a core on Spartan 6 which needs to do divisions like 1/6,2/4 etc... so the values are always between 0 and 1. As I dont need the precision of floating point I am want to use a fixed ...

fpga verilog xilinx spartan

asked Jan 19 at 17:11

ChinniKrishna Kothapalli
384

1

vote

1answer

93 views

What is the minimum current I need to supply to a Spartan-6 pin in order to register a high signal?

Digging around in the spartan-6 DC and switching characteristics guide, I can't find what I'm looking for. Also no absolute max sync/source current ratings for the user IO pins. Looking at the dev ...

fpga xilinx spartan

asked Jan 2 at 6:56

Stacey Anne
1,7661318

4

votes

1answer

179 views

inout port in VHDL RS232 Module from Digilent

I'm looking at the Digilent RS232 reference component available from http://www.digilentinc.com/Products/Detail.cfm?Prod=S3EBOARD for the Spartan 3E Starter Kit. I began putting together a testbench, ...

verilog vhdl xilinx spartan

asked Jan 1 at 19:47

trayres
1518

6

votes

4answers

525 views

How fast does a 64-bit multiply or divide execute on an FPGA?

When using a regular FPGA such as Xilinx Spartan 3 or Virtex 5, how many cycles does a double-precision floating-point 64-bit multiplication or division take to execute? As far as I understand, the ...

fpga xilinx math spartan floating-point

asked Dec 21 '12 at 11:44

Geotarget
27416

2

votes

1answer

106 views

Design doesnot work properly when clock net delay is slightly higher in spartan3a fpga

I am running my design on spartan3a 3s700afg484 at 50 mhz. There is no set up and hold time violations. There is only one global clock net. My clock report for two runs are RUN 1: Info: [707]: | ...

fpga verilog xilinx spartan

asked Dec 13 '12 at 13:19

quartz
1134

-7

votes

1answer

112 views

extracting images from camera using fpga and trasfering to pc [closed]

am be student,ece. In our college we have spartan 6-150Tx series fpga kit , the software used for this is Xilinx ise... this kit has a camera too, we need to connect this camera to fpga kit and ...

fpga spartan

asked Dec 2 '12 at 15:53

lavanya
1

4

votes

2answers

306 views

3.2 Gb/s high speed interface over 50m: copper, fiber, other ideas?

I need to run a 3.2 Gb/s interface over 50m. My client is keen on Cat6e. The lower the price, the better. These are my findings so far: I'm looking at using a Spartan 6 GTP Tranceiver with copper ...

xilinx spartan high-speed

asked Nov 12 '12 at 6:15

Stacey Anne
1,7661318

8

votes

3answers

259 views

Compare implementing a simple automation design on a MCU vs an FPGA/CPLD

I have been working with MCU's since the 90's, and I've recently ventured into the FPGA scene with the Spartan6 series chips from Xilinx. Assuming a simple factory automation design with sensors and ...

microcontroller fpga xilinx development spartan

asked Oct 25 '12 at 6:26

Kevin Boyd
541823

4

votes

1answer

297 views

Discrepancy between post-Place-and-Route static timing analysis and ISIM simulation results

Overview I'm implementing a simple Harvard-style CPU using Xilinx ISE version 14.1. I'm using settings compatible with a Digilent Nexys3 board, but for the time being the entire project is performed ...

fpga simulation timing spartan constraints

asked Jul 19 '12 at 17:26

drxzcl
1,569920

1

vote

2answers

329 views

constant memory on the Spartan 3 Starter Kit

I'm in dire need of compile-time generated constant memory of ~512K x 16Bit on the Spartan 3 Starter Kit Board. I'm configuring the board over the JTAG port, and wondered if a) there is a way to ...

fpga xilinx spartan rom

asked Jul 6 '12 at 12:48

Andreas Grapentin
1083

1

vote

1answer

107 views

Excessive latency in inter-FPGA communication

I have 4 Spartan 6 FPGAs connected through 64-bit lanes, forming a line. (That is, FPGA1 is connected to FPGA2, FPGA2 is connected to FPGA3, and FPGA3 is connected to FPGA4.) I have split each 64-bit ...

fpga spartan

asked Jul 4 '12 at 22:06

Randomblue
2,762438

2

votes

1answer

84 views

SelectMap accepts FPGA image but does not enter the startup sequence

I am loading the image of my Spartan 6 and it seems that it cannot go to the final step of the process: the "Startup Sequence". After I load the image byte by byte, and add a lot of extra clock cycles ...

fpga spartan

asked Jul 2 '12 at 10:18

Randomblue
2,762438

2

votes

1answer

213 views

SelectMap: Should HSWAPEN be high?

I'm in the process of debugging microprocessor loading of a Spartan 6 image through SelectMap. The HSWAPEN pin has caught my eye. In my design it is pulled low via a 10K resistor. However, when ...

fpga spartan selectmap

asked Jul 2 '12 at 9:41

Randomblue
2,762438

2

votes

2answers

115 views

SelectMap: Who drives the pins: FPGA or Microprocessor

I'm reading this application note regarding SelectMap image loading for my Spartan6. On page 2 I read: The device has properly powered up, but the internal configuration memory needs to be ...

fpga spartan selectmap

asked Jun 29 '12 at 10:06

Randomblue
2,762438

6

votes

1answer

195 views

Preventing Verilog module from being optimised away

I have tried to put lots of inverters to stress test my Spartan 6 power supply as recommended here. Here is the basic module: ...

verilog spartan ise

asked Jun 27 '12 at 13:51

Randomblue
2,762438

9

votes

2answers

676 views

Programming multiple FPGAs using JTAG

I have a JTAG chain connecting 4 Spartan 6 FPGAs that I program using ISE iMPACT. The software can program any strict subset of the 4 FPGAs in a row successfully, and in any order. However, when I ...

fpga jtag spartan

asked Jun 27 '12 at 9:00

Randomblue
2,762438

2

votes

2answers

245 views

Loading an FPGA image with SelectMap

As of now, I have been programming my Xilinx Spartan 6 using JTAG. I now want to load the FPGA image using SelectMap with my STM32 processor. (See this document (pages 33ff) for more information about ...

fpga spartan selectmap

asked Jun 25 '12 at 16:17

Randomblue
2,762438

0

votes

1answer

164 views

Verilog: Pass a vector as a port to a module

I have two modules counter: Output is a vector called error_count. lcd: Module to display the code on an LCD. Input includes clock and error_count. Following snippet of the code is most relevant ...

fpga lcd verilog xilinx spartan

asked May 20 '12 at 11:18

Neel Mehta
31619

0

votes

1answer

417 views

Working with Spartan-6 LX9 clock

I am a novice in digital design and are learning things using "Advanced Digital Design with the Verilog HDL" along with a Spartan-6 LX9 board by Xilinx. So far I have managed to blink few leds on the ...

fpga verilog xilinx clock spartan

asked Apr 8 '12 at 1:20

Vlad Lazarenko
673213

1

vote

2answers

764 views

Transferring a 1MB bitstream to a FPGA and reading it out

I am using Spartan 3E Starter Kit and I need to store a sequence of bits around 1MB long. It is a constant bitstream and will be known to me at the time of programming the board. I need to be able to ...

fpga memory flash spartan

asked Apr 7 '12 at 9:23

Neel Mehta
31619

0

votes

0answers

262 views

HDMI ports and IP ports (spartan-6-atlys / or what???)

I'm trying to develop an HDMI to IP converter, what should I use? I'm considering using the Digilent Atlys with an Xilinx Spartan-6 FPGA, 2 HDMI inputs, and a 10/100/1000 Ethernet PHY, but is there ...

ethernet spartan hdmi

asked Mar 11 '12 at 18:48

jossef
11

1

vote

4answers

840 views

Clock generation using FPGA

I am trying to use Spartan 3E kit to generate 50 MHz clock. The kit comes along with a 50 MHz crystal which I am trying to use. So, I wrote a simple code to output the clock from the FPGA to the SMA ...

fpga xilinx clock high-frequency spartan

asked Feb 26 '12 at 15:34

Neel Mehta
31619

0

votes

1answer

421 views

How to output signal though SMA connector in Spartan 3E Starter Kit

I want to output a signal through the SMA connector available on the Spartan 3E starter kit board. Can someone guide me as to how to do it?

fpga xilinx high-frequency spartan

asked Feb 19 '12 at 15:47

Neel Mehta
31619

0

votes

2answers

1k views

Video & image processing in Spartan-6 FPGA

I'm very new to FPGA. I got a Spartan-6 from Digilent. As my final year project I want to do image processing through it. How can MATLAB & Simulink be used for this? How should the camera be ...

fpga matlab spartan

asked Apr 6 '11 at 15:01

user3749

5

votes

3answers

1k views

Can I use ghdl or some other VHDL compiler/simulator than WebPack with a Spartan 3E?

I'm struggling with WebPack's bloat and random broken pieces when running in Linux. So, I'm thinking it may just be easier to use a different compiler/simulator. Is it possible to use something ...

fpga xilinx vhdl spartan

asked Apr 1 '11 at 22:58

Earlz
1,107836

1

vote

1answer

2k views

Using the AC97 Codec on an Atlys Spartan 6 Board

I'm a beginner to FPGA programming. I just started programming an Atlys Spartan 6 board and so far have written one program to blink LEDs in a counter pattern. Now I'm trying to send the clock signal ...

audio fpga verilog spartan

asked Apr 1 '11 at 0:46

Icarus
84

-1

votes

2answers

312 views

Rf modules for FPGA board

Are there any good data rate(~Mbps) RF modules available in market that can be interfaced with Digilent Atlys Spartan®-6 FPGA Development Kit ? Thanks in advance.

fpga rf xilinx spartan

asked Mar 2 '11 at 2:06

nav
263

10

votes

3answers

1k views

FPGA, first steps

Well this is a continuation of my question on FPGA over here. I finally selected a Digilent Atlys with a Spartan 6 FPGA, I don't have any prior experience of FPGA's although I have done some amount ...

fpga xilinx spartan

asked Jan 3 '11 at 9:35

Kevin Boyd
541823

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