Static random-access memory (SRAM) if a form of memory that uses latches to store information. It is volatile and loses information when power is removed but unlike dynamic does not require refreshing to retain information. This comes at the cost of higher complexity and less density than DRAM, but ...

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244 views

DMA between GPIO and SRAM on STM32

Here I am trying to move the data at the SRAM location 0x20000010 into the ODR register of ...
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2answers
137 views

What's the difference between a SRAM cell and a D-Latch?

They both seem identical - they both have an "enable" and a single input. When enable is high, the value stored in the element is set to the input. Are they functionally different in any way? (I know ...
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3answers
189 views

AVR SRAM limitation

I'm just an enthusiast looking for some advice. I'd like to use a microcontroller to read frames from a camera and write those frames to a small LCD screen. The camera and screen are on the same SPI ...
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1answer
87 views

Selecting external RAM for an ARM static memory controller

So I'm going through the datasheet for a device by Atmel (AT91SAM) and it shows the followings: This SMC is capable of handling several types of external memory and peripheral devices, such as ...
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1answer
55 views

Use of READY line on 8086 - is it mandatory?

Alright folks, I've recently begun working through the design of an 8086 single-board in my free time to play with (for lack of a better word, I need to experience the rush of being close to ...
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1answer
44 views

Multi-processor memory controller chips

I am trying to find a controller chip for either SRAM or S/DRAM which can properly manage access of the memory from one or more devices (i.e. microprocessors). I have been up and down Google and all I ...
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2answers
147 views

FPGA RAM / SRAM in VHDL

Today I ran out of gates on my Xylinx Spartan 3 (Basys2 by Digilent) FPGA. This was not a surprise to me as I had implemented an 8 bit x 2048 array for use as an FIFO buffer. Code: ...
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1answer
64 views

Microchip 23LC1024 driver for Atmel XMega

Is there driver or any example code available for 23LC1024 SRAM memory implemented with Atmel XMega or mega-series microcontroller?
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1answer
149 views

Current Mirror Sense Amplifier

I am unable to understand the working of the below circuit and how it act as amplifier. Enable the SAEN signal i.e. turning it high. Let us assume that we get DL as 1 and DLB as 0. Actually it will ...
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1answer
231 views

Precharging circuits in SRAM

I got to know 4 circuits used for Precharging in SRAM. I have few questions regarding circuits explanation: Diagram (a): Q1: It mentions it as diode-connected NMOS pair. Why? Q2: This burns more ...
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1answer
368 views

Sense Amplifiers in SRAM

The basic 6T structure used for storing data is same as one used in "Positive Feedback Differential Voltage Sense Amplifier", then how come while the data is stored in SRAM memory cell it doesn't get ...
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1answer
76 views

What would cause SRAM to have no errors when 5 of the bits are high?

We have a SRAM (8bit by 512k chip, 19bit address) connected to a XMOS micro-controller using a ribbon cable soldered on both sides. The xmos micro controller is a startKit and the sram chip is a ...
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2answers
398 views

What do memory configurations like “256Kx18” mean?

This is a beginner question here. When choosing memory ICs, one of the options is the memory size/configurations. I understand the size part, but what does the "16Kx9" mean? It seems the same memory ...
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2answers
535 views

Using BRAM instead of SRAM in Virtex-5 FPGA

I am working on a project where we are capturing signals from an ADC using a Virtex-5 FPGA and the samples are being stored on a 128K x 256 SRAM from where the data samples are acquired by a PC. I ...
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1answer
127 views

Does MCU RAM size affect quality of WAV read from SD?

I'm planning to build a cheap and compact WAV audio player that reads audio from a Petit-FatFs microSD card. The Petit-FatFs filesystem is designed for use with devices with less than 512B RAM. My ...
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3answers
83 views

Frame memory (SRAM) size for an image

I am now reviewing a paper about hardware implementation and it says by cropping the 128*96-pixels from 160*120-pixels, the size of the frame memory (SRAM) can be reduced to 1/10. I don't get it. ...
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213 views

STM32-E407 - FSMC

Have anyone any experience of the FSMC of a STM32 E407 chip ? Write speeds, DMA, etc ? I have an application that needs upto (worst case) 20 MB (thats bytes) / Sec sustained transfer rate from the ...
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2answers
123 views

Why aren't SRAM modules laid out in a matrix?

I'm currently reading about RAM modules. Bigger DRAM module are laid out in a matrix. When retrieving data you first retrieve the row and then the column. One of the benefits of the matrix lay-out is ...
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0answers
332 views

Read VGA pixel value from SRAM in VHDL

I'm using a SRAM in order to store a frame that I have to display on screen with the VGA interface. I need to read the pixel value from the SRAM and then send it to the VGA monitor. I have created a ...
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2answers
594 views

VHDL SRAM Controller interface

I'm designing a VGA controller in VHDL and for video memory I decided to use SRAM memory. In order to manage the RAM I created a controller that must be interfaced with the VGA Controller. So far I ...
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1answer
514 views

Which SPI mode to use?

I'm interfacing a 23LC1024 SPI Serial SRAM with a PIC18, using the C18 compiler and the built-in functions from <spi.h> as described in the Compiler ...
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2answers
246 views

Creating SRAM array digitally using Verilog

As a part of my Cadence based project, I chose the topic 'Optimising power, area and timing for a 32x8 SRAM unit'. Though this is possible using NC-Verilog or by manually constructing the schematic ...
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2answers
189 views

Accessing an SRAM Array?

As im learning about Computer Architecture im trying to understand it from the ground up (Transistors in CMOS in particular) I came across the simple 6T schematic for SRAM (2 inverters) Mostly ...
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3answers
1k views

What's the catch with FRAM?

After recently acquiring an MSP430 Launchpad I've been playing with various microcontroller projects. Unfortunately, the MSP430G2553 only has 512 bytes of RAM, so doing anything complex requires ...
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2answers
247 views

Data bus between uC and SRAM: what happens when both are writing concurrently?

My understanding of interfacing a standard SRAM chip is the following: When the host wants to write, the OutputEnable# is driven high to bring the SRAM data bus to High-Z and the host is driving the ...
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1answer
136 views

Without double-clocking, how to perform 2 write and 2 read each clock using Dual Port RAM?

In a project I'm working currently, the quad-port RAM ,which can perform 2 write and 2 read each clock by double-clocking technique, is required to achieve some specific goals. But now it seems too ...
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1answer
147 views

DS3232M Skips seconds when writing to SRAM

I'm using a DS3232M that works great for keeping track of the time until I try to write to the SRAM on the chip. When I use the SRAM it slows the updates of the seconds register or stops them all ...
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1answer
2k views

Using CCM (Core Coupled Memory) in STM32F4xx

STM32F4xx microcontrollers have 128KB of SRAM + 64KB of CCM SRAM. CMM SRAM is hardwired to data bus so it is impossible to use it with DMA. What is the reason to add additional SRAM as CCM? Does it ...
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2answers
1k views

Why not SRAM for FPGA in image processing?

I'm beginning with VHDL coding and I've done some basic image processing on my development board. I've noticed that most FPGA development boards often use DRAM (SDRAM, DDRAM) as RAM. For example, I'm ...
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1answer
2k views

Speed difference between SRAM (Static RAM) and DDR3 RAM

This is more of a computing question, but only electronics geeks would know such things. Today's computers use multiple layers of memory in order to work with data quickly. Currently CPU speeds are ...
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3answers
224 views

Physical address vs virtual address

Physical address is hardware address of physical memory and virtual address is the one the processor will be seeing, it has it has a tag and offset. I understand this. Can any one describe it with an ...
4
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1answer
3k views

Running executable from external SRAM

I have an STM32 dev board with some external SRAM. I would like to execute my code from that external SRAM, but my processor only supports booting from the Flash, internal SRAM or System memory (a ...
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2answers
374 views

Does pin order matter at all for this RAM?

I am trying to route a pic32 chip to a 128kB SRAM chip and having a bit of a hard time getting all 17 address lines and all 8 data lines connected. I am trying to tie the first 16 address pins to ...
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4answers
4k views

SRAM and Flip-Flops

Still learning, but this question is bugging me. I finally sort of understand how Flip-Flops work, and how that is used to maintain Shift Registers and such. From the wiki page: "Each bit in an SRAM ...
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2answers
218 views

Reading and writing SRAM

I am setting up a audio delay circuit and i want to store the data on SRAM chip. I am doing it with a 64khz clock and ideally i would like to write a word in every other pulse and read a word every ...
0
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1answer
68 views

Attaching two identical PSRAMs to the same set of signals

I have an ARM microprocessor connected to an FPGA through one 47 pin memory bus. Also, two identical PSRAMs (datasheet available here) are connected to the FPGA through 65 pins (47 for first PSRAM + ...
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1answer
121 views

Undefined behaviour in a PSRAM read memory transaction

I am reading the datasheet of a PSRAM (available here). Looking at the timing diagram for burst reads (page 10, figure 8), there is a "undefined behaviour" for a half-cycle on the ...
3
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1answer
120 views

Why doesn't page mode write operations exist?

I'm learning about the different memory access modes for SRAM. (Specific datasheet available here.) As I understand, there is "asynchronous mode", "page mode" and "burst mode". Page mode is an ...
3
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1answer
808 views

Microprocessor controlling SRAM through an FPGA

I have an ARM Cortex 3M (reference manual here) connected through the FSMC (Flexible Static Memory Controller) to a Spartan 6 FPGA. In turn, the Spartan 6 is connected to some external SRAM. I need ...
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1answer
479 views

Testing the integrity of SRAM

I am testing a board that has external SRAM. Apparently the SRAM is relatively sensitive to the soldering heat from the manufacturing process, and so careful testing must be done to check integrity of ...
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1answer
663 views

Using SDRAM with a MC68000

I'm currently working on developing myself a computer based on the Motorola 68000 CPU and am currently working on the RAM interface. Since I want a basic multitasking OS, I want to use 1 MB of RAM. ...
1
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3answers
1k views

SRAM memory cell - what kind of flip-flop

There is a classic 6T SRAM cell (image from wikipedia): It looks like (two inverters in opposite directions and interconnected in and out) and works like some flip-flop. But what kind of flipflop ...
2
votes
3answers
1k views

I know why DRAM is slower to write than to read, but why is the L1 & L2 cache RAM slower to write?

DRAM is slower to write than read because it takes time to either charge or discharge a DRAM memory cell. But what about the SRAM in my processor's L1 and L2 caches? It's slower to write as well but ...
1
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4answers
1k views

How to implement SRAM sense amplifier?

I am designing a simple programmable LED screen system as an exercise, and I need a non-standard type of SRAM (16x5) so I am designing the memory circuits. I have looked everywhere (Digikey, TI, ...
4
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2answers
158 views

Advice on suitable SRAM

I'm kind of new to all this and the choices out there is kind of overwhelming when it comes to selecting a SRAM package and Flash eprom to go with a 10 Mhz Z80180. I'm looking for a 128 KB SRAM and a ...