Static random-access memory (SRAM) if a form of memory that uses latches to store information. It is volatile and loses information when power is removed but unlike dynamic does not require refreshing to retain information. This comes at the cost of higher complexity and less density than DRAM, but ...
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Problem running C++ function from STM32's SRAM in Keil microVision
I'm using Keil uVision 4.6 to write a C++ program for SMT32F103RE.
I need to run one of my program functions directly from SRAM, so I devided my SRAM into two separate regions:
...
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1answer
108 views
VHDL SRAM Controller interface
I'm designing a VGA controller in VHDL and for video memory I decided to use SRAM memory. In order to manage the RAM I created a controller that must be interfaced with the VGA Controller. So far I ...
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1answer
96 views
Which SPI mode to use?
I'm interfacing a 23LC1024 SPI Serial SRAM with a PIC18, using the C18 compiler and the built-in functions from <spi.h> as described in the Compiler ...
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2answers
74 views
Creating SRAM array digitally using Verilog
As a part of my Cadence based project, I chose the topic 'Optimising power, area and timing for a 32x8 SRAM unit'. Though this is possible using NC-Verilog or by manually constructing the schematic ...
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2answers
73 views
Accessing an SRAM Array?
As im learning about Computer Architecture im trying to understand it from the ground up (Transistors in CMOS in particular)
I came across the simple 6T schematic for SRAM (2 inverters)
Mostly ...
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3answers
425 views
What's the catch with FRAM?
After recently acquiring an MSP430 Launchpad I've been playing with various microcontroller projects. Unfortunately, the MSP430G2553 only has 512 bytes of RAM, so doing anything complex requires ...
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2answers
190 views
Data bus between uC and SRAM: what happens when both are writing concurrently?
My understanding of interfacing a standard SRAM chip is the following: When the host wants to write, the OutputEnable# is driven high to bring the SRAM data bus to High-Z and the host is driving the ...
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1answer
81 views
Without double-clocking, how to perform 2 write and 2 read each clock using Dual Port RAM?
In a project I'm working currently, the quad-port RAM ,which can perform 2 write and 2 read each clock by double-clocking technique, is required to achieve some specific goals. But now it seems too ...
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1answer
71 views
DS3232M Skips seconds when writing to SRAM
I'm using a DS3232M that works great for keeping track of the time until I try to write to the SRAM on the chip. When I use the SRAM it slows the updates of the seconds register or stops them all ...
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1answer
274 views
Using CCM (Core Coupled Memory) in STM32F4xx
STM32F4xx microcontrollers have 128KB of SRAM + 64KB of CCM SRAM. CMM SRAM is hardwired to data bus so it is impossible to use it with DMA.
What is the reason to add additional SRAM as CCM?
Does it ...
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2answers
402 views
Why not SRAM for FPGA in image processing?
I'm beginning with VHDL coding and I've done some basic image processing on my development board.
I've noticed that most FPGA development boards often use DRAM (SDRAM, DDRAM) as RAM.
For example, I'm ...
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1answer
384 views
Speed difference between SRAM (Static RAM) and DDR3 RAM
This is more of a computing question, but only electronics geeks would know such things. Today's computers use multiple layers of memory in order to work with data quickly. Currently CPU speeds are ...
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3answers
148 views
Physical address vs virtual address
Physical address is hardware address of physical memory and virtual address is the one the processor will be seeing, it has it has a tag and offset. I understand this. Can any one describe it with an ...
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1answer
1k views
Running executable from external SRAM
I have an STM32 dev board with some external SRAM. I would like to execute my code from that external SRAM, but my processor only supports booting from the Flash, internal SRAM or System memory (a ...
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2answers
312 views
Does pin order matter at all for this RAM?
I am trying to route a pic32 chip to a 128kB SRAM chip and having a bit of a hard time getting all 17 address lines and all 8 data lines connected. I am trying to tie the first 16 address pins to ...
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4answers
821 views
SRAM and Flip-Flops
Still learning, but this question is bugging me.
I finally sort of understand how Flip-Flops work, and how that is used to maintain Shift Registers and such.
From the wiki page:
"Each bit in an SRAM ...
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2answers
131 views
Reading and writing SRAM
I am setting up a audio delay circuit and i want to store the data on SRAM chip.
I am doing it with a 64khz clock and ideally i would like to write a word in every other pulse and read a word every ...
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1answer
53 views
Attaching two identical PSRAMs to the same set of signals
I have an ARM microprocessor connected to an FPGA through one 47 pin memory bus. Also, two identical PSRAMs (datasheet available here) are connected to the FPGA through 65 pins (47 for first PSRAM + ...
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1answer
76 views
Undefined behaviour in a PSRAM read memory transaction
I am reading the datasheet of a PSRAM (available here). Looking at the timing diagram for burst reads (page 10, figure 8), there is a "undefined behaviour" for a half-cycle on the ...
3
votes
1answer
100 views
Why doesn't page mode write operations exist?
I'm learning about the different memory access modes for SRAM. (Specific datasheet available here.) As I understand, there is "asynchronous mode", "page mode" and "burst mode".
Page mode is an ...
2
votes
1answer
492 views
Microprocessor controlling SRAM through an FPGA
I have an ARM Cortex 3M (reference manual here) connected through the FSMC (Flexible Static Memory Controller) to a Spartan 6 FPGA. In turn, the Spartan 6 is connected to some external SRAM.
I need ...
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1answer
215 views
Testing the integrity of SRAM
I am testing a board that has external SRAM. Apparently the SRAM is relatively sensitive to the soldering heat from the manufacturing process, and so careful testing must be done to check integrity of ...
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1answer
394 views
Using SDRAM with a MC68000
I'm currently working on developing myself a computer based on the Motorola 68000 CPU and am currently working on the RAM interface. Since I want a basic multitasking OS, I want to use 1 MB of RAM. ...
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3answers
512 views
SRAM memory cell - what kind of flip-flop
There is a classic 6T SRAM cell (image from wikipedia):
It looks like (two inverters in opposite directions and interconnected in and out) and works like some flip-flop.
But what kind of flipflop ...
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votes
3answers
680 views
I know why DRAM is slower to write than to read, but why is the L1 & L2 cache RAM slower to write?
DRAM is slower to write than read because it takes time to either charge or discharge a DRAM memory cell. But what about the SRAM in my processor's L1 and L2 caches? It's slower to write as well but ...
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4answers
870 views
How to implement SRAM sense amplifier?
I am designing a simple programmable LED screen system as an exercise, and I need a non-standard type of SRAM (16x5) so I am designing the memory circuits. I have looked everywhere (Digikey, TI, ...
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1answer
108 views
Advice on suitable SRAM
I'm kind of new to all this and the choices out there is kind of overwhelming when it comes to selecting a SRAM package and Flash eprom to go with a 10 Mhz Z80180.
I'm looking for a 128 KB SRAM and a ...
