Static random-access memory (SRAM) if a form of memory that uses latches to store information. It is volatile and loses information when power is removed but unlike dynamic does not require refreshing to retain information. This comes at the cost of higher complexity and less density than DRAM, but ...

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Why are two LEDs on? is 7489 broken?

This is a follow up question to this question. I have attempted to draw a schematics of my setup for the 7489 below. Without the switch closed, the LED D1 is on. Then the switch is closed, then also ...
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69 views

Schematics for using IC 7489 memory

I bought two SN7489 because I wanted to learn how the memory chip works. I followed the datasheet. I don't seem to be able to get it to work. After playing around for some time with the IC, it got ...
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1answer
61 views

M48Z02 SRAM unexpected data loss

I'm using a M48Z02, a 5 V 16 Kbit ZEROPOWER SRAM. In absence of power, according to datasheet information, this device can hold data for years: A [...] package houses the M48Z02 silicon with a ...
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1answer
44 views

What is precharge in terms of Static Ram?

In many six transistor static ram cell diagrams, it mentions a so called "precharge" that holds both bit lines at positive voltage. What is the use of this? wouldn't this constant voltage just screw ...
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48 views

Paralell SRAM with separate I/O ports

In Logisim I created a circuit containing RAM module with separate input and output lines I want to build this circuit from real items. However I could not find any SRAM chips that have separate I/O ...
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44 views

What are the differences between line tree decoder and matrix decoder?

Here's the reference material which has me confused. After reviewing these 2 images I am confused about the differences between the 2 as the 6 to 64 decoder looks remarkably like a matrix decoder ...
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1answer
26 views

M48Z02 (16Kbit ZEROPOWER SRAM) is TTL compatible?

I've some problem using together TLL and CMOS integrated. I'm developing a project and only now I discovered that the two standards can create troubles together. So I decided to use only TTL chips. ...
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1answer
68 views

Fast write/read on NVRAM with Windows

I am trying to find a solution to create a 4MBit NVRAM module (FRAM or SRAM, doesn't matter) with a standard PC with Windows. I want to store up to 1MB of data in less than 1 second with 50-100 write ...
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4answers
197 views

Is program code copied to SRAM from flash on microcontroller?

On PC, program executable is read from hard disk, and loaded into RAM to execute it. On microcontroller, program is stored on flash. Is it loaded into SRAM when microcontroller starts up? If yes, ...
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207 views

Unstable/sensitive ARM- External SRAM connection

I designed a board for a specific purpose. There are different active components on the board, including: ATMEL SAM4S16C Controller (runs on 120MHz) W5100 ethernet controller (connected to the SAM ...
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3answers
148 views

Interfacing 62256 SRAM to low pin-count AVR via latches

I need to add over 20 kBytes of RAM to the small device built around ATMega8. Moreover I'm interested to research whether I can substitute it with ATtiny2313. The goal is roughly speaking to store ...
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1answer
71 views

What is the purpose of SRAM in the DS1307 RTC chip and the onboard AT24C32N EEPROM chip??

I am going to interface a RTC to PIC18F and before doing so, I'd like to clear some doubts regarding the module and its connections. I am using the "Tiny RTC" as shown in this link!. The following ...
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1answer
67 views

FPGA + SRAM - floating inputs of SRAM during configuration of FPGA

I'm connecting SRAM to FPGA (Spartan 6). During configuration and during periods when FPGA will be down (for example I would like to turn off FPGA when external flash will be programmed by uC) address ...
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1answer
141 views

Modern replacements for old DRAM memory chips

I have an old video card for a computer from the 1980s era, but unfortunately the memory chips on it have gone bad. As it's quite a rare device today, I would like to repair it. Unfortunately I ...
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0answers
24 views

SRAM latency reduction methods used in practice

I've read a paper* by a [then] Sun engineer (and some academic collaborators) that describes a way to improve SRAM latency (over a batch of chips) by adding a combination of row redundancy and ECC so ...
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1answer
70 views

How does a flip-flop circuit keep it state?

When reading about the difference between SDRAM and SRAM (electronically), I understand that SDRAM requires the dynamically charging of the capacitors to maintain their states. I do not get how SRAM ...
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2answers
92 views

Why fram instead of eeprom

Why do all the gameboy cartridge mods for nonvolatile save use a type of ram like fram? Why isn't a sufficiently fast eeprom or flash ic used? EDIT: We all know this is about parallel interface ICs, ...
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1answer
141 views

How does this SRAM work?

I have to simulate a SRAM and I already replicated the circuit in Proteus. Still, I'm unsure where to start. I haven't found any table to see how to assign data and then how to read it. Could anyone ...
2
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1answer
99 views

Size of DRAM logic designs

I am a beginner with FPGAs and EE in general, so please bear with me! It is my understanding that many modern FPGAs are SRAM-based, and for good reason: SRAM can handle higher clock speeds and has ...
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1answer
365 views

What type of memory allows for most parallel read/write operations per clock cycle in an FPGA?

If you imagine basic motion detection where you have two frames stored in memory: a previous 640x480 frame and the current 640x480 frame, what type of memory (SRAM, DRAM, SDRAM, DDR SDRAM, etc) would ...
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25 views
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250 views

How do the access transistors in an SRAM cell work?

For example, in the picture above, how do M5 and M6 really work? how can they be turned on by simply asserting WL? wouldn't the transistors turn on or off based on the gate-source voltage? I don't ...
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4answers
680 views

SRAM swapped address / data bits

Consider the following wiring from a microcontroller to a sram chip: ...
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1answer
67 views

Arduino Uno SRAM

After countless hours trying to debug my 'was working fine with MEGA' code, i have diagnosed the issue to my SRAM. I except that my code (a combination of NTPClient, EthernetClient & various ...
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3answers
61 views

How can I replace this 5565 SRAM with a dual port SRAM?

I have an existing device (an arcade CPU board) that stores some data in a 5565 64-Kbit SRAM. I want to replace it with a dual-port RAM so I can read the data with a microcontroller. I don't need to ...
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2answers
218 views

Schematic for run of the mill SRAM?

So lets take your run of the mill SRAM, such as 23K256 from Microchip: http://ww1.microchip.com/downloads/en/DeviceDoc/22100D.pdf Do they mostly just use a generic 6T cell setup such as: ...
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1answer
3k views

DMA between GPIO and SRAM on STM32

Here I am trying to move the data at the SRAM location 0x20000010 into the ODR register of ...
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2answers
673 views

What's the difference between a SRAM cell and a D-Latch?

They both seem identical - they both have an "enable" and a single input. When enable is high, the value stored in the element is set to the input. Are they functionally different in any way? (I know ...
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3answers
412 views

AVR SRAM limitation

I'm just an enthusiast looking for some advice. I'd like to use a microcontroller to read frames from a camera and write those frames to a small LCD screen. The camera and screen are on the same SPI ...
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1answer
197 views

Selecting external RAM for an ARM static memory controller

So I'm going through the datasheet for a device by Atmel (AT91SAM) and it shows the followings: This SMC is capable of handling several types of external memory and peripheral devices, such as ...
2
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1answer
99 views

Use of READY line on 8086 - is it mandatory?

Alright folks, I've recently begun working through the design of an 8086 single-board in my free time to play with (for lack of a better word, I need to experience the rush of being close to ...
0
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1answer
73 views

Multi-processor memory controller chips

I am trying to find a controller chip for either SRAM or S/DRAM which can properly manage access of the memory from one or more devices (i.e. microprocessors). I have been up and down Google and all I ...
3
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2answers
679 views

FPGA RAM / SRAM in VHDL

Today I ran out of gates on my Xylinx Spartan 3 (Basys2 by Digilent) FPGA. This was not a surprise to me as I had implemented an 8 bit x 2048 array for use as an FIFO buffer. Code: ...
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1answer
159 views

Microchip 23LC1024 driver for Atmel XMega

Is there driver or any example code available for 23LC1024 SRAM memory implemented with Atmel XMega or mega-series microcontroller?
2
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1answer
519 views

Current Mirror Sense Amplifier

I am unable to understand the working of the below circuit and how it act as amplifier. Enable the SAEN signal i.e. turning it high. Let us assume that we get DL as 1 and DLB as 0. Actually it will ...
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1answer
1k views

Precharging circuits in SRAM

I got to know 4 circuits used for Precharging in SRAM. I have few questions regarding circuits explanation: Diagram (a): Q1: It mentions it as diode-connected NMOS pair. Why? Q2: This burns more ...
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1answer
3k views

Sense Amplifiers in SRAM

The basic 6T structure used for storing data is same as one used in "Positive Feedback Differential Voltage Sense Amplifier", then how come while the data is stored in SRAM memory cell it doesn't get ...
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1answer
87 views

What would cause SRAM to have no errors when 5 of the bits are high?

We have a SRAM (8bit by 512k chip, 19bit address) connected to a XMOS micro-controller using a ribbon cable soldered on both sides. The xmos micro controller is a startKit and the sram chip is a ...
4
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2answers
800 views

What do memory configurations like “256Kx18” mean?

This is a beginner question here. When choosing memory ICs, one of the options is the memory size/configurations. I understand the size part, but what does the "16Kx9" mean? It seems the same memory ...
2
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2answers
2k views

Using BRAM instead of SRAM in Virtex-5 FPGA

I am working on a project where we are capturing signals from an ADC using a Virtex-5 FPGA and the samples are being stored on a 128K x 256 SRAM from where the data samples are acquired by a PC. I ...
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1answer
170 views

Does MCU RAM size affect quality of WAV read from SD?

I'm planning to build a cheap and compact WAV audio player that reads audio from a microSD card using Petit-FatFs. The Petit-FatFs driver is designed for use with devices with less than 512B RAM. My ...
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3answers
104 views

Frame memory (SRAM) size for an image

I am now reviewing a paper about hardware implementation and it says by cropping the 128*96-pixels from 160*120-pixels, the size of the frame memory (SRAM) can be reduced to 1/10. I don't get it. ...
4
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2answers
149 views

Why aren't SRAM modules laid out in a matrix?

I'm currently reading about RAM modules. Bigger DRAM module are laid out in a matrix. When retrieving data you first retrieve the row and then the column. One of the benefits of the matrix lay-out is ...
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1answer
691 views

Read VGA pixel value from SRAM in VHDL

I'm using a SRAM in order to store a frame that I have to display on screen with the VGA interface. I need to read the pixel value from the SRAM and then send it to the VGA monitor. I have created a ...
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2answers
1k views

VHDL SRAM Controller interface

I'm designing a VGA controller in VHDL and for video memory I decided to use SRAM memory. In order to manage the RAM I created a controller that must be interfaced with the VGA Controller. So far I ...
6
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1answer
899 views

Which SPI mode to use?

I'm interfacing a 23LC1024 SPI Serial SRAM with a PIC18, using the C18 compiler and the built-in functions from <spi.h> as described in the Compiler ...
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2answers
474 views

Creating SRAM array digitally using Verilog

As a part of my Cadence based project, I chose the topic 'Optimising power, area and timing for a 32x8 SRAM unit'. Though this is possible using NC-Verilog or by manually constructing the schematic ...
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2answers
310 views

Accessing an SRAM Array?

As im learning about Computer Architecture im trying to understand it from the ground up (Transistors in CMOS in particular) I came across the simple 6T schematic for SRAM (2 inverters) Mostly ...
24
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3answers
4k views

What's the catch with FRAM?

After recently acquiring an MSP430 Launchpad I've been playing with various microcontroller projects. Unfortunately, the MSP430G2553 only has 512 bytes of RAM, so doing anything complex requires ...
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2answers
278 views

Data bus between uC and SRAM: what happens when both are writing concurrently?

My understanding of interfacing a standard SRAM chip is the following: When the host wants to write, the OutputEnable# is driven high to bring the SRAM data bus to High-Z and the host is driving the ...