In theory at least, SOIC is half the pin pitch of DIP and SSOP is half again. Thus SSOP is 0.1/4 = 0.025" or 0.635mm. Except I see many parts, from TI and Linear especially, which are SSOP (or TSSOP) ...
Will there be a problem if I stay almost in the border in trace spacing when dealing with line voltages?
The IPC-2221 standard shows that 1.25mm will be enough at less than 3050m at 250V (220V is the line voltage here in Turkey), even if the coating gets damaged. However, people generally recommend 5mm ...