State machine is a very generic term for any process (electronic or otherwise) whose output is not simply a function of its current inputs, but also depends on its past history. In other words, it has "memory", or internal state information.

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634 views

Interrupt handling in microcontrollers and FSM example

Initial question I have a general question about the handling of interrupts in microcontrollers. I am using the MSP430, but I think the question may be extended to other uCs. I would like to know ...
0
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1answer
83 views

State diagram for 2-bit parity generator

So the question I need help with is: Design a minimal moore state machine for a 2-bit parity generator that outputs ‘1’ if the number of 1s in a 2-bit sequence is odd, and outputs ‘0’ otherwise. ...
0
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1answer
112 views

Keypad Scanner Verilog code problem with state machine and column input

I am developing a Keypad both in hardware and Verilog using a DE2 Cyclone II board. I made a keypad using buttons (switches) that follows this schematic: The scanner works by setting the Column ...
0
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0answers
24 views

Digilent EPP handshaking problem

I intend to use my Spartan-6 board as an interface between my mic (which produces I2S data) and PC for live recording. Since UART is too slow, i planned on using Digilent's parallel interface with ...
2
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1answer
90 views

sequence detector in verilog

I have the task of building a sequence detector Here's the code : ...
0
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0answers
56 views

Help me understand Mealy machine with D flip flops vs JK flip flops

So, the task is to implement a synchronous sequential circuit which detects the input sequence "1101" using D flip flops and standard logic gates (represent with Mealy machine with finite number of ...
0
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3answers
84 views

This state machine does not go into an initial state on start

This is my state machine code: ...
0
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3answers
109 views

Finite-State-Machine-based digital design

How do I implement a specific digital design using mealy model and then implement the same design again using Moore model ? Can anyone provide detailed steps ? Thanks. Update: In the digital logic ...
0
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2answers
83 views

You need at least four states to exploit the advantages of a Mealy machine over a Moore machine

What's meant by this question? "You need at least four states to exploit the advantages of a Mealy machine over a Moore machine." I'm trying to wrap my head around this but I'm not sure "what" ...
3
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1answer
98 views

VHDL code and unintended latches

I am working on coding a Regsiter a1 with input signals b1,rst and wra1 the register ...
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0answers
169 views

Binary/Polynomial division on FPGA implementation

I am beginning the implementation of the polynomial binary division algorithm now as I understood i will be checking the MSB bit if 1 to XOR and shift the sum if 0 I will only shift. What I am not ...
0
votes
1answer
161 views

The difference between algorithmic state machine (ASM) and state transition graph

I have a very basic question. In what ways an algorithmic state machine (ASM) is different from a state transition graph (STG). Can someone take a very basic example (such as a binary counter) to ...
0
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0answers
29 views

Implement a finite state machine Mealy [paper + wishboard]

I have a problem with a project, I need to implement a Mealy machine on a Wishboard, but I can't figure it out how to finish it. Some of the post I found here helped me to understand better how this ...
0
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1answer
169 views

How do I analytically list the correct sequence for the given digital circuit?

Suppose given the digital circuit below, which contains 3 JK flip-flops: Assume that the sequence starts at ABC = 000. How can I analytically list the resulting sequence after every clock cycle?
5
votes
2answers
133 views

Unable to get the correct k-map for this finite state machine (Crosswalk System)

I am trying to create a Crosswalk System using a finite state machine. Although I understand how to do it, apparently I am continuously arriving at the wrong equations for my D inputs since my K-maps ...
0
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2answers
93 views

What are “consecutive input pulses”?

I am stuck on a homework problem that I have difficult time understanding: Draw the state diagram of the circuit described below, with detailed explanations: A detection circuit has two ...
0
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0answers
147 views

Design a Mealy FSM that functions as a sequence detector, generating two outputs y, z in the following way:

Initially both inputs are set to 0. Output y is set to 1 when the sequence "10" has been applied to the input x; output y should then be reset to 0 and y should continue detecting next occurrence of ...
0
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2answers
81 views

Building a first State Machine circuit - Technical Help

I just learned how to synthesize a diagram of a finite state machine into a diagram of a logical circuit composed of D flip flops, a clock and logical gates. However, I don't really have much ...
0
votes
3answers
188 views

How to detect a change in resistance?

I would like to have a circuit that can be controlled by two variable resistors, and it should use the value of the "most-recently-changed" resistor. How can I find out when one of the variable ...
2
votes
3answers
119 views

State Machine w/ Decoder

I'm trying to design a State Machine that acts as a synchronous lock. There is only 1 input (X) and one output (Lock= 0, Unlock = 5v). The machine will only unlock if the following order is put in: 0* ...
2
votes
2answers
621 views

How to design a LIFT simulator using FSM(Finite State Machine)

I want to design a LIFT with the help of Finite state machine. There are four floors. So I took them as 0, 1,2,3 and correspondingly the states. The 0,1,2,3 buttons are present inside the lift. If ...
0
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0answers
42 views

Reading an irregularly shaped matrix and doing action when a key is pressed in a modular way

Before I get into the details, I'd like to apologize if this is the wrong SE site for this. I could see it going on here, Stackoverflow, Arduino, or maybe even code review. I am using a Teensy 2 as a ...
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votes
2answers
635 views

Generate State Diagram from VHDL Code?

Is there a tool which generates State Diagrams from VHDL code? Also is there an easy way to indent VHDL code like in Visual Studio if I press ctrl + i it indents.
0
votes
1answer
150 views

Key press/Key release

I'm designing a keypad in VHDL and for protection purposes I disable pressing a second or more keys while one key is being pressed. Example while I'm pressing "7" a press of "2","3","5","4","1","0" ...
7
votes
3answers
275 views

Pressing same key rows at the same time

I am designing a keypad in VHDL. Everything works fine when only a single key is pressed. I'm scanning each column for a key press in a state machine and when no key is pressed, which is the condition ...
0
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2answers
255 views

Software to draw state diagrams and asm charts? [closed]

I would like to draw state diagrams and asm charts like these: Any recommendations? Are these done with Microsoft Visio?
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3answers
128 views

Return from idle state

I have 5 states : idle, state1, state2, state3, state4. I sometimes need to go to idle according to my design, and when I return from idle, I don't want to start from beginning, I want to start from ...
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3answers
167 views

Set a constant high signal to low

I have a keypad circuit, when I press and hold a key, the signal "key_pressed" is always high, as long as I keep the key pressed, which is normal, when I leave it, it gets low again. But I don't want ...
0
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1answer
148 views

State switches in FSM

I have a simple board with 6 buttons, consisting of 3 columns and 2 rows I would like to detect the pressed button. My code below works with this fsm: ...
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2answers
118 views

Usage of Next state and Clock Divider?

I have a clock divider and state machine like this: ...
0
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0answers
38 views

Create State machine and implement on CPLD [duplicate]

I have this conditions for traffic controller. I excuted this on table. Now I want to implement this to state machine. Then after I will use this state machine to create VHDL and implement it in CPLD. ...
0
votes
1answer
153 views

Enable clock for a state machine?

I have 100Mhz system clock and I would like to have a 200Hz Enable signal for enabling the state machine. I need a clock divider for this process and thought about this : ...
0
votes
1answer
691 views

Implication chart method for state reduction

I'm not understanding implication charts to reduce states for Mealy and Moore machines. I'm looking at an example from berkley I was able to construct the table and then also eliminate the ones based ...
4
votes
2answers
589 views

ISR - to flag or not to flag?

From what I read on the internet we should respond to interrupts as quickly as possible, when programming microcontrollers; and that flags should be avoided because they tend to compound over time. ...
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votes
1answer
217 views

Creating a Sorting Machine (Finite State Machine) [closed]

So here is my task: Design a sorting machine. The idea!is to design a two-port read two-port write register file with k registers. The data are stored in registers using some input switches (address ...
0
votes
1answer
169 views

Finite State Machine to find Greatest Common Divisor

Ok so here is the problem we are given: Consider the following datapath. Assume the width of the datapath n is 4. The ALU has a 1-bit operation code OP. If OP=0, the ALU performs A-B. If OP=1, the ...
0
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0answers
143 views

Project to Print School ID on a 7 Segment Display - All Segment Outputs are High When Simulated

I am working on a project that uses a BCD up-counter block, a BCD to school ID block, and a BCD to 7-segment display, in order to print out my school ID on the 7-segment display of an FPGA. Here is ...
0
votes
1answer
222 views

How are state machines used in electronics?

It seems to me the use of state machines is just in logic circuits, is that correct? If not do they have other uses, such as say in microcontroller programming? I'm quite new to the subject and wonder ...
2
votes
1answer
265 views

Finding the logic expressions of a finite state machine that has three possible inputs

I'm familiar with finite state machines when there are two possible states for input, which I will call w. That is, w = 1 or ...
0
votes
1answer
287 views

Finite state machine FSM model of FIR filter in VHDL for FPGA

I want to make a FSM model of FIR, for that I need to write FIR calculation code line in FSM implementation. Here is the actual and correct code for FIR ...
0
votes
1answer
36 views

Structure function solving

I have following block diagram, I am having trouble constructing structure function marks for this block diagram. What concerns me is that OR state from State 5 to State 2 and State 6. I thought ...
1
vote
1answer
263 views

Output table equivalent to state diagram?

I have the following state diagram to which I am supposed to construct an output table for. I have the answer, but I do not understand how they derived this output table? If someone could explain one ...
1
vote
3answers
164 views

SCPI message exchange control implementation

This is more of a software question but I figured more would be known about SCPI (IEEE 488.2) here. I am implementing a full serial (using IEEE 1174) SCPI parser on an IC device but am wondering ...
0
votes
1answer
618 views

How can I determine whether circuit is Moore or Mealy machine

I've designed a modulo 5 counter (0,1,2,3,4,0,1....) with additional features like BCD to 7-segment-display decoder, the reset switch and the special switch to omit number "3" in the counter. But the ...
1
vote
2answers
1k views

Best practice to keep main() in embedded systems

I would like to know one thing about keeping the main() in embedded coding practice. I have a stand-alone system that have n ...
1
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2answers
109 views

How to determine what the states should be in this state diagram

I'm trying to make a simple state diagram to understand a concept in class. There is one input and one output \$ \left(X \ \text{and}\ Y\ \text{lets say} \right)\$. The output is \$1\$ if an input is ...
0
votes
3answers
278 views

How to choose flip flop type for implementation?

How to choose flip flop type for implementation in moore or mealy state diagram? I can't understand this thing. Could someone help me? There are t-type, d-type, s-r type, j-k type. How to choose one ...
4
votes
1answer
169 views

Simple state machine with latching inputs is confusing me

Okay so this is a question for school, I am not expecting someone to give me the full thought out answer, I just need someone to point me in the right direction as I am confused and my tutor is off on ...
0
votes
0answers
105 views

Finding state diagram of circuit with two T flip flops

I want to find the state diagram of this circuit, there is no input and output. I need to use Excitation table? I would like to get some suggestions. Thanks!
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votes
2answers
316 views

Finite State Machine

My task is to design a FSM whose output goes high for a single cycle whenever the pattern 10110 is detected on its input. I am assuming I will need five state bubbles.