State machine is a very generic term for any process (electronic or otherwise) whose output is not simply a function of its current inputs, but also depends on its past history. In other words, it has "memory", or internal state information.

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State Machine w/ Decoder

I'm trying to design a State Machine that acts as a synchronous lock. There is only 1 input (X) and one output (Lock= 0, Unlock = 5v). The machine will only unlock if the following order is put in: 0* ...
2
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2answers
87 views

How to design a LIFT simulator using FSM(Finite State Machine)

I want to design a LIFT with the help of Finite state machine. There are four floors. So I took them as 0, 1,2,3 and correspondingly the states. The 0,1,2,3 buttons are present inside the lift. If ...
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0answers
31 views

Reading an irregularly shaped matrix and doing action when a key is pressed in a modular way

Before I get into the details, I'd like to apologize if this is the wrong SE site for this. I could see it going on here, Stackoverflow, Arduino, or maybe even code review. I am using a Teensy 2 as a ...
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2answers
125 views

Generate State Diagram from VHDL Code?

Is there a tool which generates State Diagrams from VHDL code? Also is there an easy way to indent VHDL code like in Visual Studio if I press ctrl + i it indents.
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1answer
73 views

Key press/Key release

I'm designing a keypad in VHDL and for protection purposes I disable pressing a second or more keys while one key is being pressed. Example while I'm pressing "7" a press of "2","3","5","4","1","0" ...
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3answers
187 views

Pressing same key rows at the same time

I am designing a keypad in VHDL. Everything works fine when only a single key is pressed. I'm scanning each column for a key press in a state machine and when no key is pressed, which is the condition ...
0
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2answers
71 views

Software to draw state diagrams and asm charts? [closed]

I would like to draw state diagrams and asm charts like these: Any recommendations? Are these done with Microsoft Visio?
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3answers
76 views

Return from idle state

I have 5 states : idle, state1, state2, state3, state4. I sometimes need to go to idle according to my design, and when I return from idle, I don't want to start from beginning, I want to start from ...
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3answers
137 views

Set a constant high signal to low

I have a keypad circuit, when I press and hold a key, the signal "key_pressed" is always high, as long as I keep the key pressed, which is normal, when I leave it, it gets low again. But I don't want ...
0
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1answer
110 views

State switches in FSM

I have a simple board with 6 buttons, consisting of 3 columns and 2 rows I would like to detect the pressed button. My code below works with this fsm: ...
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2answers
65 views

Usage of Next state and Clock Divider?

I have a clock divider and state machine like this: ...
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0answers
35 views

Create State machine and implement on CPLD [duplicate]

I have this conditions for traffic controller. I excuted this on table. Now I want to implement this to state machine. Then after I will use this state machine to create VHDL and implement it in CPLD. ...
0
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1answer
99 views

Enable clock for a state machine?

I have 100Mhz system clock and I would like to have a 200Hz Enable signal for enabling the state machine. I need a clock divider for this process and thought about this : ...
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0answers
75 views

Implication chart method for state reduction

I'm not understanding implication charts to reduce states for Mealy and Moore machines. I'm looking at an example from berkley I was able to construct the table and then also eliminate the ones based ...
4
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2answers
537 views

ISR - to flag or not to flag?

From what I read on the internet we should respond to interrupts as quickly as possible, when programming microcontrollers; and that flags should be avoided because they tend to compound over time. ...
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1answer
85 views

Creating a Sorting Machine (Finite State Machine) [closed]

So here is my task: Design a sorting machine. The idea!is to design a two-port read two-port write register file with k registers. The data are stored in registers using some input switches (address ...
0
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1answer
65 views

Finite State Machine to find Greatest Common Divisor

Ok so here is the problem we are given: Consider the following datapath. Assume the width of the datapath n is 4. The ALU has a 1-bit operation code OP. If OP=0, the ALU performs A-B. If OP=1, the ...
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0answers
92 views

Project to Print School ID on a 7 Segment Display - All Segment Outputs are High When Simulated

I am working on a project that uses a BCD up-counter block, a BCD to school ID block, and a BCD to 7-segment display, in order to print out my school ID on the 7-segment display of an FPGA. Here is ...
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0answers
27 views

Register file to handle binary numbers to then be sorted (circuit diagram)? [duplicate]

--The inputs to the muxes are just the output Q of the D flip flop. They go in descending order instead of across the register. There are two sets of four 4-to-1 muxes, each posses the same inputs ...
0
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1answer
187 views

How are state machines used in electronics?

It seems to me the use of state machines is just in logic circuits, is that correct? If not do they have other uses, such as say in microcontroller programming? I'm quite new to the subject and wonder ...
2
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1answer
145 views

Finding the logic expressions of a finite state machine that has three possible inputs

I'm familiar with finite state machines when there are two possible states for input, which I will call w. That is, w = 1 or ...
0
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1answer
155 views

Finite state machine FSM model of FIR filter in VHDL for FPGA

I want to make a FSM model of FIR, for that I need to write FIR calculation code line in FSM implementation. Here is the actual and correct code for FIR ...
0
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1answer
32 views

Structure function solving

I have following block diagram, I am having trouble constructing structure function marks for this block diagram. What concerns me is that OR state from State 5 to State 2 and State 6. I thought ...
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1answer
112 views

Output table equivalent to state diagram?

I have the following state diagram to which I am supposed to construct an output table for. I have the answer, but I do not understand how they derived this output table? If someone could explain one ...
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3answers
98 views

SCPI message exchange control implementation

This is more of a software question but I figured more would be known about SCPI (IEEE 488.2) here. I am implementing a full serial (using IEEE 1174) SCPI parser on an IC device but am wondering ...
0
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1answer
141 views

How can I determine whether circuit is Moore or Mealy machine

I've designed a modulo 5 counter (0,1,2,3,4,0,1....) with additional features like BCD to 7-segment-display decoder, the reset switch and the special switch to omit number "3" in the counter. But the ...
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2answers
846 views

Best practice to keep main() in embedded systems

I would like to know one thing about keeping the main() in embedded coding practice. I have a stand-alone system that have n ...
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2answers
76 views

How to determine what the states should be in this state diagram

I'm trying to make a simple state diagram to understand a concept in class. There is one input and one output \$ \left(X \ \text{and}\ Y\ \text{lets say} \right)\$. The output is \$1\$ if an input is ...
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3answers
184 views

How to choose flip flop type for implementation?

How to choose flip flop type for implementation in moore or mealy state diagram? I can't understand this thing. Could someone help me? There are t-type, d-type, s-r type, j-k type. How to choose one ...
4
votes
1answer
142 views

Simple state machine with latching inputs is confusing me

Okay so this is a question for school, I am not expecting someone to give me the full thought out answer, I just need someone to point me in the right direction as I am confused and my tutor is off on ...
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0answers
80 views

Finding state diagram of circuit with two T flip flops

I want to find the state diagram of this circuit, there is no input and output. I need to use Excitation table? I would like to get some suggestions. Thanks!
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2answers
196 views

Finite State Machine

My task is to design a FSM whose output goes high for a single cycle whenever the pattern 10110 is detected on its input. I am assuming I will need five state bubbles.
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2answers
230 views

Design Finite State Machine

I need to design a finite state machine that detects any invalid button sequences for a set of instructions. The scenario is a factory where the person must press POWER, WELD, and than POWER and that ...
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1answer
156 views

Finite State Machine for Synchronous Circuit

Using the diagram below I have to fill out the state table for Q1+, Q0+, G, and F. Assuming Q0+ and Q1+ are the inputs to the left and right flip-flops, respectively, fill out the following state ...
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1answer
132 views

Curious state transitions in state machine RTL simulation

I have a simple state machine as part of my Verilog module: ...
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1answer
110 views

What are the methods to encode Finite State Machines?

I'm a bit confused about these topics. I already studied combinational systems, and went for Karnaugh Maps and Quine McCluskey methods, so now I studied sequential systems and I'm supposed to study ...
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1answer
122 views

I get a warning that a latch is generated - why

When I compile my VHDL code I get following warning: ...
5
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2answers
2k views

How to choose between Mealy and Moore state machine

I know the basic differences between Mealy and Moore FSM (Finite state machine). What I want to understand is the following: Pros and cons of using Mealy over Moore and vice versa In which situation ...
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3answers
89 views

State Diagram Issue - Equivalent Situations

How do I know according to the following diagram if I have a equivalent situations, how do I recognize it? for example we will examine S2 and S3. I would like to get an advice how to do it. Thanks! ...
1
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1answer
152 views

Call a Finite State Machine in VHDL

I need to read data from a SRAM in one step (something like READ_RAM(addr) that returns the value stored in the SRAM at the "addr" address). Is it possible create a function/procedure that integrates ...
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3answers
340 views

Can someone help me complete this Verilog code for this sequential circuit?

I'm still pretty new to Verilog and all and could use some help completing/fixing my code for this problem. I have made the state diagram, state table/assignment, minimized the equation, and even have ...
0
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0answers
218 views

A step motor fsm design

A step motor (or stepper motor) is a brushless DC (direct current) electric motor that divides a full rotation into a number of equal steps.The step motor has permenant magnet rotor and electromagnets ...
2
votes
2answers
428 views

Designing a Moore Machine

For a class project, I am required to design a Moore Machine based on a problem that we were given. I have already done this with a Mealy Machine, but I am encountering errors with the Moore Machine. ...
0
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1answer
176 views

Drawing State Diagrams

So I'm going through my textbook and I'm stuck on this problem: Design a circuit that has two inputs, \$clk\$ and \$X\$, and produces one output \$O\$. \$X\$ may change every clock cycle, and the ...
0
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1answer
81 views

Next-State Tables

Could someone give me some tips on how to approach state tables? I'm working through my textbook for an upcoming exam and I'm stuck at this problem: 17) Design a circuit that has an input clk, ...
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4answers
183 views

9-Bit State Machine

I am working on a state machine that will drive a state bus for a personal project. The state machine will have an output pattern like the following: ...
3
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2answers
241 views

Finite State Machines

I want to design a finite state machine that is similar to a 3 bit counter. There are 3 bits of state (i.e. a 3 bit unsigned number) and the counter must count by 3's. More specifically, the sequence ...
0
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2answers
173 views

Statemachine as a separate module in VHDL?

I would like to create a state machine as a separate unit with multiple inputs and one output. The output will be the state. The states are defined by a syntax similar to ...
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2answers
598 views

calculating FSM's maximum clock frequency

Let's assume we have the Truth Table for our Finite state machine. How can we determine the maximum clock frequency for the system, under the assumptions that the wire delay is 0.3 ns , flip-flop ...
2
votes
2answers
343 views

Desiging FSM using D flip flop

I want implement the state diagram using D flip flop without using K-map because of the complexity of 5 variable K-map.Is there any other method by which it can be implemented. The state diagram is ...