State machine is a very generic term for any process (electronic or otherwise) whose output is not simply a function of its current inputs, but also depends on its past history. In other words, it has "memory", or internal state information.

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how to design a pattern detector state machine in vhdl

How can I use vhdl to design a sequence detector to find a 32bit sequence with 15 zeros followed by 17 ones by using 2 counters to count ones and zeros that have enable and reset signals. Can anybody ...
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58 views

Modelling Circuit from FSM using Verilog

I am trying to understand the concept of modeling a circuit from a FSM in Verilog. I have tried to write down the procedure that I have used in the image below just to make sure that I did it right: ...
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39 views

designing a state machine to detect a certain bit

So, I need to create a state machine (mealy machine) to detect the bit 1010 and also I need to code it in verilog. Here is a picture of my state machine: So, I created the state machine and Now I ...
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41 views

Implementing clock divider VHDL

I have written a FSM using a clock divider with the source frequency being 5MHz and trying to take it down to 3 for simulation sake but the clocks come as U in the simulation like so : I am ...
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117 views

When to use State Machines - FPGA

I've read a lot about FSMs (Finite State Machines) when doing VHDL tutorials. They are easy and I've used them a lot but I still don't understand something and can't find the answer online: When ...
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Why is this a Moore and not a Mealy FSM?

Can someone please explain how I can tell which FSM type I have? In my textbook I read that output in a Mealy FSM is based on both the input and the present state, but in a Moore FSM it is based only ...
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1answer
40 views

Algorithmic State Machine using D flip Flops - how to deal with don't care conditions

I have the following state transition table: where, A, B - current states of two D flip flops A+, B+ - next states of the two D flip flops X1, X2, X3 - inputs to the current states There are ...
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62 views

Comparison of State Assignments without transition table

I came across a problem in which 3 state assignments are given for a sequential Mealy machine with 8 states. State assignments are as follows: $$ \begin{array}{c|c|c} & \text{Assignment1} & ...
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2answers
162 views

Modeling the elevator as a finite state machine

This is my first post here. Nice to meet you all! I've read a related question here and am still having issues. The task: There is a building consisting of 7 storeys (indexed 0-6). Design a system ...
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28 views

State Machine for I-type MIPS instructions

I need to design a multi-cycle CPU in Verilog for MIPS instructions, but I'm still trying to fully understand the datapath and control. I found a state machine design for a MIPS instruction ...
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1answer
102 views

4-bit Finite State Machine with 6 states and synchronous reset using D Flip-Flops

I have recently began studying Digital Electronics and have hit a wall trying to figure out how to design FSMs. At the moment, I am attempting to desing the FSM in the title which generates the ...
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1answer
63 views

Xilinx ISE Language Template for State Machines

In Xilinx ISE, if you check the state-machine examples given in "Language Template" (VHDL->Synthesis Constructs->Coding Examples->State Machines and Verilog->Synthesis Constructs->Coding ...
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61 views

Finite state machine (FSM) that controls a memory block

I have to Implement a finite state machine (FSM) that controls a block memory. The FSM receives two inputs, indicating ready when the memory is prepared, read / write (r_w) indicating whether you want ...
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59 views

Rotation Detector Sequential Circuit

o I have tried tackling this problem, but I cant seem to get anywhere. I dont know if I am making things too complex. I came up with this state diagram and state table. But I dont know if this is too ...
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1answer
94 views

How do I convert ldi R17, 129 to machine code

What I got was 1110 1000 0001 0001 when I converted it to machine language. Is that right? Also what are the CPU activity steps and where am I going to use the address 0xF000? Is this the right CPU ...
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26 views

Can state reduction lead to increased number of gates?

In digital logic circuits, can state reduction in sequential circuits lead to increased number of gates in our circuit at any instant? I know that it reduces the states and sometimes reduces the ...
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69 views

Mealy Machine and registered outputs and delay increase

I am implementing an absolute value block containing a bit-serial Subtractor, the output connected to an 8-bit shift register which in turn connects to a two's complement block at the output there is ...
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1answer
82 views

Draw state transition diagram for identifying a sequence of bits

A state transition diagram has to be drawn for the following scenario. (Later it has to be implemented using D flipflops) Scenario:- A sequential machine to resolve a 4-bit security code. The code ...
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1answer
75 views

State based vs State-less design (in verilog)

Recently, I have been carrying out some beginner to lower moderate level designs, from starting to all the way to HDL coding in verilog. I thought that FSM based design, either Mealy or Moore is the ...
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2answers
91 views

Single input for consecutive state transitions in an FSM: preventing fall-through

Consider the following state diagram where the inputs are c and v. The system is also receiving a high frequency clock ...
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70 views

State diagram for JK-flip-flop

I'm trying to create a simple state-diagram for a JK flip-flop, and this is what I've come up with. I've seen other variants of this diagram, but to me this seems like a correct one if you look at ...
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1answer
137 views

Implementing a FSM using JK flip flops in VHDL

This is yet another semester project I'm stuck on. I need to implement a state machine starting from the following diagram: What I've managed to do so far is write this state table, although I'm ...
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2answers
158 views

Designing a State Machine

Question: Design a state machine that would output the sequence 0 1 7 1 and then 1 7 1 1 7 1 and so on. A reset will make the machine go to the which outputs 0? What I've managed to do so far: Since ...
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64 views

how to Make Mealy machine output synchronous?

I have seen in slide below (and of course with some thought ) that the output of a Mealy machine is not synchronous . (you can find the whole slide in here). to make it synchronous the slide note ...
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1answer
117 views

Finite State Machine

I tried to write a Verilog code for the finite state machine whose diagram shown below. I see nothing as an output. What is the wrong part of my code? or Is my code completely absurd? My code: ...
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1answer
37 views

Designing state machine for Jk FF Counter

The counter is supposed to go from 1>3>4>7>6 and use JK flip flops. While filling out the state table I'm a bit confused about what to do with invalid states. Since I think this is 3 bits and should ...
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1answer
323 views

Sequential Traffic Light Controller

Just for clarification: I'm just looking to see if I'm on the right path for this project and to figure out what the best plan of attack might be. I'm trying to simulate a sequential traffic ...
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1k views

Interrupt handling in microcontrollers and FSM example

Initial question I have a general question about the handling of interrupts in microcontrollers. I am using the MSP430, but I think the question may be extended to other uCs. I would like to know ...
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1answer
428 views

State diagram for 2-bit parity generator

So the question I need help with is: Design a minimal moore state machine for a 2-bit parity generator that outputs ‘1’ if the number of 1s in a 2-bit sequence is odd, and outputs ‘0’ otherwise. ...
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1answer
1k views

Keypad Scanner Verilog code problem with state machine and column input

I am developing a Keypad both in hardware and Verilog using a DE2 Cyclone II board. I made a keypad using buttons (switches) that follows this schematic: The scanner works by setting the Column ...
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1answer
2k views

sequence detector in verilog

I have the task of building a sequence detector Here's the code : ...
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3answers
113 views

This state machine does not go into an initial state on start

This is my state machine code: ...
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3answers
225 views

Finite-State-Machine-based digital design

How do I implement a specific digital design using mealy model and then implement the same design again using Moore model ? Can anyone provide detailed steps ? Thanks. Update: In the digital logic ...
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2answers
108 views

You need at least four states to exploit the advantages of a Mealy machine over a Moore machine

What's meant by this question? "You need at least four states to exploit the advantages of a Mealy machine over a Moore machine." I'm trying to wrap my head around this but I'm not sure "what" ...
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1answer
156 views

VHDL code and unintended latches

I am working on coding a Regsiter a1 with input signals b1,rst and wra1 the register ...
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124 views

VHDL - Flip Flop inferring on a signal

I have to design a circuit to count up to a number and return to zero. It must have a carry signal (which I named a_o in my circuit) as flag to show that the ...
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1answer
715 views

The difference between algorithmic state machine (ASM) and state transition graph

I have a very basic question. In what ways an algorithmic state machine (ASM) is different from a state transition graph (STG). Can someone take a very basic example (such as a binary counter) to ...
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1answer
181 views

How do I analytically list the correct sequence for the given digital circuit?

Suppose given the digital circuit below, which contains 3 JK flip-flops: Assume that the sequence starts at ABC = 000. How can I analytically list the resulting sequence after every clock cycle?
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2answers
363 views

Unable to get the correct k-map for this finite state machine (Crosswalk System)

I am trying to create a Crosswalk System using a finite state machine. Although I understand how to do it, apparently I am continuously arriving at the wrong equations for my D inputs since my K-maps ...
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2answers
166 views

What are “consecutive input pulses”?

I am stuck on a homework problem that I have difficult time understanding: Draw the state diagram of the circuit described below, with detailed explanations: A detection circuit has two ...
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2answers
120 views

Building a first State Machine circuit - Technical Help

I just learned how to synthesize a diagram of a finite state machine into a diagram of a logical circuit composed of D flip flops, a clock and logical gates. However, I don't really have much ...
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3answers
280 views

How to detect a change in resistance?

I would like to have a circuit that can be controlled by two variable resistors, and it should use the value of the "most-recently-changed" resistor. How can I find out when one of the variable ...
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3answers
149 views

State Machine w/ Decoder

I'm trying to design a State Machine that acts as a synchronous lock. There is only 1 input (X) and one output (Lock= 0, Unlock = 5v). The machine will only unlock if the following order is put in: 0* ...
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2answers
2k views

How to design a LIFT simulator using FSM(Finite State Machine)

I want to design a LIFT with the help of Finite state machine. There are four floors. So I took them as 0, 1,2,3 and correspondingly the states. The 0,1,2,3 buttons are present inside the lift. If ...
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2answers
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Generate State Diagram from VHDL Code?

Is there a tool which generates State Diagrams from VHDL code? Also is there an easy way to indent VHDL code like in Visual Studio if I press ctrl + i it indents.
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1answer
347 views

Key press/Key release

I'm designing a keypad in VHDL and for protection purposes I disable pressing a second or more keys while one key is being pressed. Example while I'm pressing "7" a press of "2","3","5","4","1","0" ...
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3answers
510 views

Pressing same key rows at the same time

I am designing a keypad in VHDL. Everything works fine when only a single key is pressed. I'm scanning each column for a key press in a state machine and when no key is pressed, which is the condition ...
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3answers
246 views

Return from idle state

I have 5 states : idle, state1, state2, state3, state4. I sometimes need to go to idle according to my design, and when I return from idle, I don't want to start from beginning, I want to start from ...
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3answers
328 views

Set a constant high signal to low

I have a keypad circuit, when I press and hold a key, the signal "key_pressed" is always high, as long as I keep the key pressed, which is normal, when I leave it, it gets low again. But I don't want ...
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1answer
273 views

State switches in FSM

I have a simple board with 6 buttons, consisting of 3 columns and 2 rows I would like to detect the pressed button. My code below works with this fsm: ...