The state-machines tag has no wiki summary.
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Can someone help me complete this Verilog code for this sequential circuit?
I'm still pretty new to Verilog and all and could use some help completing/fixing my code for this problem. I have made the state diagram, state table/assignment, minimized the equation, and even have ...
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A step motor fsm design
A step motor (or stepper motor) is a brushless DC (direct current) electric motor that divides a full rotation into a number of equal steps.The step motor has permenant magnet rotor and electromagnets ...
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Designing a Moore Machine
For a class project, I am required to design a Moore Machine based on a problem that we were given. I have already done this with a Mealy Machine, but I am encountering errors with the Moore Machine. ...
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Drawing State Diagrams
So I'm going through my textbook and I'm stuck on this problem:
21) Design a circuit that has two inputs, clk and X, and produces one output O. X may change every clock cycle, and the change happens ...
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Next-State Tables
Could someone give me some tips on how to approach state tables? I'm working through my textbook for an upcoming exam and I'm stuck at this problem:
17) Design a circuit that has an input clk, ...
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4answers
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9-Bit State Machine
I am working on a state machine that will drive a state bus for a personal project. The state machine will have an output pattern like the following:
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Finite State Machines
I want to design a finite state machine that is similar to a 3 bit counter. There are 3 bits of state (i.e. a 3 bit unsigned number) and the counter must count by 3's. More specifically, the sequence ...
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Statemachine as a separate module in VHDL?
I would like to create a state machine as a separate unit with multiple inputs and one output. The output will be the state.
The states are defined by a syntax similar to ...
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calculating FSM's maximum clock frequency
Let's assume we have the Truth Table for our Finite state machine.
How can we determine the maximum clock frequency for the system, under the assumptions that the wire delay is 0.3 ns , flip-flop ...
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Desiging FSM using D flip flop
I want implement the state diagram using D flip flop without using K-map because of the complexity of 5 variable K-map.Is there any other method by which it can be implemented.
The state diagram is ...
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Desigining a synchronous FSM
I am trying to figure out how do I approach for a synchronous FSM as per the following information:
Two inputs A, B & single output Z
Two inputs A, B & single output Z
Z=1 if A had the ...
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Why is the output of stateful elements often named Q?
In logic circuit diagrams, I've seen various conventions for naming inputs and outputs of logic gates and combinatorial circuits. However, stateful elements like latches and flip-flops often have ...
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How do you compute a product machine from two finite state machine transition tables?
I have been asked to show 2 Finite State Machines are equivalent by computing the product machine of both. Below is an image of 2 transition tables corresponding to 2 Finite State Machines.
How do ...
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How do I implement a simple finite state machine with 2 T flip-flops?
The following Finite State Machine (FSM #1)
can be implemented with 2 T flip-flops like so:
This makes sense because you have 4 different states {00,01,10,11} and flip-flip TA handles the left ...
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2answers
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State Machine using Case getting unexpected result
I am trying to write a very simple state machine that implements a combinational lock.
The code is: Switch1 -> Switch2 -> Switch3 -> Switch4
I realize that it is Switch 7, 6, 5, 4 accordingly in ...
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Signal assignment type
What is the meaning of "combinational assignment" and "registered assignment" to signals? In particular what are the differences between these two types of assignments?
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FSM Using Excitation Equations and VHDL
I have been trying to create a FSM using the excitation equations I developed. I have not had much luck. The circuit has no output.
I DO NOT WANT TO USE 'TYPE' and custom state types. That is the ...
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3answers
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What happens when there's no specific input variable on a logic diagram using a JK flip flop?
I'm trying to do some homework involving this circuit diagram:
But I'm confused as to what the input would be for building a state table. Would I have to use the states of the flip flops as the ...
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conversion from Moore To Mealy
Can somebody please explain how can I convert from Moore FSM to Mealy FSM and vice versa?
Thanks in advance.
