State machine is a very generic term for any process (electronic or otherwise) whose output is not simply a function of its current inputs, but also depends on its past history. In other words, it has "memory", or internal state information.

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How are state machines used in electronics? [on hold]

It seems to me the use of state machines is just in logic circuits, is that correct? If not do they have other uses, such as say in microcontroller programming? I'm quite new to the subject and wonder ...
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70 views

Finding the logic expressions of a finite state machine that has three possible inputs

I'm familiar with finite state machines when there are two possible states for input, which I will call w. That is, w = 1 or ...
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53 views

Finite state machine FSM model of FIR filter in VHDL for FPGA

I want to make a FSM model of FIR, for that I need to write FIR calculation code line in FSM implementation. Here is the actual and correct code for FIR ...
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29 views

Structure function solving

I have following block diagram, I am having trouble constructing structure function marks for this block diagram. What concerns me is that OR state from State 5 to State 2 and State 6. I thought ...
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70 views

Output table equivalent to state diagram?

I have the following state diagram to which I am supposed to construct an output table for. I have the answer, but I do not understand how they derived this output table? If someone could explain one ...
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64 views

SCPI message exchange control implementation

This is more of a software question but I figured more would be known about SCPI (IEEE 488.2) here. I am implementing a full serial (using IEEE 1174) SCPI parser on an IC device but am wondering ...
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91 views

How can I determine whether circuit is Moore or Mealy machine

I've designed a modulo 5 counter (0,1,2,3,4,0,1....) with additional features like BCD to 7-segment-display decoder, the reset switch and the special switch to omit number "3" in the counter. But the ...
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611 views

Best practice to keep main() in embedded systems

I would like to know one thing about keeping the main() in embedded coding practice. I have a stand-alone system that have n ...
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65 views

How to determine what the states should be in this state diagram

I'm trying to make a simple state diagram to understand a concept in class. There is one input and one output \$ \left(X \ \text{and}\ Y\ \text{lets say} \right)\$. The output is \$1\$ if an input is ...
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139 views

How to choose flip flop type for implementation?

How to choose flip flop type for implementation in moore or mealy state diagram? I can't understand this thing. Could someone help me? There are t-type, d-type, s-r type, j-k type. How to choose one ...
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128 views

Simple state machine with latching inputs is confusing me

Okay so this is a question for school, I am not expecting someone to give me the full thought out answer, I just need someone to point me in the right direction as I am confused and my tutor is off on ...
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67 views

Finding state diagram of circuit with two T flip flops

I want to find the state diagram of this circuit, there is no input and output. I need to use Excitation table? I would like to get some suggestions. Thanks!
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165 views

Finite State Machine

My task is to design a FSM whose output goes high for a single cycle whenever the pattern 10110 is detected on its input. I am assuming I will need five state bubbles.
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Design Finite State Machine

I need to design a finite state machine that detects any invalid button sequences for a set of instructions. The scenario is a factory where the person must press POWER, WELD, and than POWER and that ...
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149 views

Finite State Machine for Synchronous Circuit

Using the diagram below I have to fill out the state table for Q1+, Q0+, G, and F. Assuming Q0+ and Q1+ are the inputs to the left and right flip-flops, respectively, fill out the following state ...
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109 views

Curious state transitions in state machine RTL simulation

I have a simple state machine as part of my Verilog module: ...
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1answer
104 views

What are the methods to encode Finite State Machines?

I'm a bit confused about these topics. I already studied combinational systems, and went for Karnaugh Maps and Quine McCluskey methods, so now I studied sequential systems and I'm supposed to study ...
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113 views

I get a warning that a latch is generated - why

When I compile my VHDL code I get following warning: ...
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731 views

How to choose between Mealy and Moore state machine

I know the basic differences between Mealy and Moore FSM (Finite state machine). What I want to understand is the following: Pros and cons of using Mealy over Moore and vice versa In which situation ...
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3answers
88 views

State Diagram Issue - Equivalent Situations

How do I know according to the following diagram if I have a equivalent situations, how do I recognize it? for example we will examine S2 and S3. I would like to get an advice how to do it. Thanks! ...
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132 views

Call a Finite State Machine in VHDL

I need to read data from a SRAM in one step (something like READ_RAM(addr) that returns the value stored in the SRAM at the "addr" address). Is it possible create a function/procedure that integrates ...
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264 views

Can someone help me complete this Verilog code for this sequential circuit?

I'm still pretty new to Verilog and all and could use some help completing/fixing my code for this problem. I have made the state diagram, state table/assignment, minimized the equation, and even have ...
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196 views

A step motor fsm design

A step motor (or stepper motor) is a brushless DC (direct current) electric motor that divides a full rotation into a number of equal steps.The step motor has permenant magnet rotor and electromagnets ...
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2answers
351 views

Designing a Moore Machine

For a class project, I am required to design a Moore Machine based on a problem that we were given. I have already done this with a Mealy Machine, but I am encountering errors with the Moore Machine. ...
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163 views

Drawing State Diagrams

So I'm going through my textbook and I'm stuck on this problem: Design a circuit that has two inputs, \$clk\$ and \$X\$, and produces one output \$O\$. \$X\$ may change every clock cycle, and the ...
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80 views

Next-State Tables

Could someone give me some tips on how to approach state tables? I'm working through my textbook for an upcoming exam and I'm stuck at this problem: 17) Design a circuit that has an input clk, ...
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169 views

9-Bit State Machine

I am working on a state machine that will drive a state bus for a personal project. The state machine will have an output pattern like the following: ...
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226 views

Finite State Machines

I want to design a finite state machine that is similar to a 3 bit counter. There are 3 bits of state (i.e. a 3 bit unsigned number) and the counter must count by 3's. More specifically, the sequence ...
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161 views

Statemachine as a separate module in VHDL?

I would like to create a state machine as a separate unit with multiple inputs and one output. The output will be the state. The states are defined by a syntax similar to ...
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467 views

calculating FSM's maximum clock frequency

Let's assume we have the Truth Table for our Finite state machine. How can we determine the maximum clock frequency for the system, under the assumptions that the wire delay is 0.3 ns , flip-flop ...
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2answers
319 views

Desiging FSM using D flip flop

I want implement the state diagram using D flip flop without using K-map because of the complexity of 5 variable K-map.Is there any other method by which it can be implemented. The state diagram is ...
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2answers
261 views

Desigining a synchronous FSM

I am trying to figure out how do I approach for a synchronous FSM as per the following information: Two inputs A, B & single output Z Two inputs A, B & single output Z Z=1 if A had the ...
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7answers
592 views

Why is the output of stateful elements often named Q?

In logic circuit diagrams, I've seen various conventions for naming inputs and outputs of logic gates and combinatorial circuits. However, stateful elements like latches and flip-flops often have ...
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1answer
301 views

How do you compute a product machine from two finite state machine transition tables?

I have been asked to show 2 Finite State Machines are equivalent by computing the product machine of both. Below is an image of 2 transition tables corresponding to 2 Finite State Machines. How do ...
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530 views

How do I implement a simple finite state machine with 2 T flip-flops?

The following Finite State Machine (FSM #1) can be implemented with 2 T flip-flops like so: This makes sense because you have 4 different states {00,01,10,11} and flip-flip TA handles the left ...
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196 views

State Machine using Case getting unexpected result

I am trying to write a very simple state machine that implements a combinational lock. The code is: Switch1 -> Switch2 -> Switch3 -> Switch4 I realize that it is Switch 7, 6, 5, 4 accordingly in ...
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136 views

Signal assignment type

What is the meaning of "combinational assignment" and "registered assignment" to signals? In particular what are the differences between these two types of assignments?
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262 views

FSM Using Excitation Equations and VHDL

I have been trying to create a FSM using the excitation equations I developed. I have not had much luck. The circuit has no output. I DO NOT WANT TO USE 'TYPE' and custom state types. That is the ...
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3answers
170 views

What happens when there's no specific input variable on a logic diagram using a JK flip flop?

I'm trying to do some homework involving this circuit diagram: But I'm confused as to what the input would be for building a state table. Would I have to use the states of the flip flops as the ...
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conversion from Moore To Mealy

Can somebody please explain how can I convert from Moore FSM to Mealy FSM and vice versa? Thanks in advance.