The synchronous tag has no wiki summary.
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Regarding voltage regulation of a synchronous generator
My textbook somewhat ambiguously defines the voltage regulation of a synchronous generator as the difference between the induced EMF and the full load terminal voltage, divided by the full load ...
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How electronic components keep synchronized?
So, voltage travels super fast right? Still, there has to be some lag between voltage traveling from one transistor into another. How is a circuit kept synchronized then?
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Why do displays with auto-synchronization function get out of sync? (pixels blur) [closed]
I'd like to know why LCD displays that have the "Auto" button need it in the first place. Are they losing sync with the signal because of some special feature or all LCD displays really suffer from ...
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176 views
Clock skew? Good or bad?
So, I've been reading up on clock skew. I came across the fact that clock skew can be incredibly useful, in the sense that positive skew can be used to speed up the circuit by increasing the clock's ...
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Design a 4-bit synchronous counter using D filp-flops and 16 x 4 ROM that can generated any arbitrary counting sequence
What are the restrictions on the counting sequence? Give the ROM contents for the following sequences: a) 12, 13, 14, 15, 5, 6, 7, 0, 1, 2, 3, 4, 11, 10, 9, 8, 12, 13, etc...
b)8, 9, 0, 1, 8, 9, ...
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Regulating a small clockwork synchronous AC motor
Is it possible to drive a small synchronous motor with permanent magnetized rotor to other speeds it is designed for?
I tried to drive a small clockwork AC motor which is symmetrically build but ...
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170 views
Sync video with data
When I have a datalogger and I want to sync a video-file to the recording, what would be an easy method? The logger and the camera both have an internal clock, but they may not be set exactly to the ...
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Synchronous motor mystery
Not too long ago I acquired an old ('70/'80) German flip clock. I found out that this clock is driven by a one-phase synchronous engine.
I can't get the motor to run. I (carefully!) connected the ...
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775 views
Syncing Signals with Global Clocks in FPGAs/CPLDs and Edge Detection
I am a newbie in digital logic design and I'm trying to get my head around syncing external signals to the global clock in an FPGA. For example, the SCK signal/clock fed to an FPGA by the SPI Master. ...
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489 views
How to implement a synchronization signal with AVR (attiny45)?
In pseudocode I want to do following:
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280 views
Timing inside a shift register
How I imagine synchronous digital networks work: data lines are sampled at rising clock edge, a set of transients occur, system settles, and data lines are sampled again on next rising edge. I would ...
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959 views
Ripple counters versus synchronous--pros, cons, and power consumption
Substantial edit--note that David Kessner's answer was written in response to the original posting; view the edit history to see what he was responding to
From what I've read of digital design, there ...
