Transform a high-level design description (e.g. VHDL or Verilog) into a low-level implementation to be loaded onto programmable logic.
0
votes
0answers
23 views
Verilog Netlist and verilog file not justifying each other
i generated a verilog netlist file with the help of a test case for 2-1 encoder .To test the netlist i draw the schematic diagram and try to find the output.I can't upload the pic of schematic which i ...
-1
votes
2answers
32 views
value of variable in Veriog not defined
I am analyzing a verilog file for always.
in this, what should be the value of "en" in case first and then in second?
...
0
votes
1answer
37 views
Understanding Verilog Netlist
This might be a out of stand question.I am trying to understand a verilog netlist for 1 bit adder and make schematic out of it.But as i am very new to Verilog, though can understand some basic ...
0
votes
1answer
88 views
Maximum and Minimum delay of combinational logic circuits
I am preparing for my exam and I am stuck with this past year question:
In the circuit shown below, the blocks A, B, C, and S are combination logic circuits. FF1 to FF3 are D flip-flops with same ...
1
vote
2answers
78 views
Post synthesis level simulation xilinx xst
I have written a verilog code and it is working fine at behavioral simulation level. After this I went for synthesizing the design using XST tool in Xilinx ISE 13.2. Running the post simulation level ...
2
votes
1answer
108 views
What does non-combinational area represent in synopsys design compiler
I have designed a ripple adder using full adders. In order to find delay incurred to perform this addition I included a clock in each full adder module. In my main code I instantiated these modules to ...
2
votes
3answers
156 views
Open Source verilog synthesizer
I'm looking for an open source verilog synthesizer. I am using Icarus Verilog as a verilog simulator. Originally I was going to use it for both simulation and synthesis, but found out the tool no ...
1
vote
1answer
186 views
How can I avoid “Minimum Pulse Width” slack violations in Quartus FPGA synthesis?
I am synthesizing a toy application on DE2, but I hit a timing problem (despite every inputs and outputs are clocked in my design). These violations are related to "minimum pulse width"...
How can I ...
-10
votes
1answer
159 views
Synthesis error for generated IP express single port RAM with shift register design
I have generated single port RAM (DP8KC primitive) from IP express using Lattice tool and then I am instantiating with 48 bit shift register, which is at input side. The output of shift register is ...
2
votes
2answers
137 views
How to generate wait until division is over in verilog?
I am using a division module which has two signals other than inputs
"go" to indicate start of division.
"done" to indicate stop of division.
It is taking approx 300 clock cycles for the division to ...
2
votes
2answers
124 views
Synthesize VHDL into discrete TTL integrated circuits
I've got a small project in VHDL (fully working in a Xilinx FPGA) and I would like to implement it using an old-school printed circuit board and discrete TTL integrated circuits, in the spirit of ...
0
votes
1answer
122 views
Search for a method to create a synthesizable Verilog file [closed]
I am studying Verilog, and I know what kind of Verilog file type can be synthesised. For instance, a signal can never be driven in two always blocks. But I can't do ...
0
votes
1answer
123 views
Why is ISE / XLS is mapping a signal to the global clock GCK0?
I've synthesized a design for a Coolrunner II CPLD. I intend to use the CPLD's internal clock. I have an input named CLK. I look at the fitter report and I see this:
...
1
vote
1answer
118 views
Can I create a verilog file to both simulate and synthesize?
Recently I was reading a Verilog study book. I finally realized that a Verilog file may not be synthesizable, because some Verilog statements are for simulation use only. But I'm too lazy to make one ...
3
votes
1answer
46 views
Synthesis using Synopsis
I'm using Synopsys to synthesize designs. I've noticed that when I synthesize exactly the same design several times, I get different synthesis reports.
When I launch the tool for the first time, ...
3
votes
1answer
195 views
How to embed a clock oscillator inside a digital block? Specifically, how is this defined for Synopsys DC?
I have to embed a clock oscillator inside my logic block for layout purposes. It's not an option to leave this block out and just bring the clock port in. Is there any way to define an internal net as ...
4
votes
1answer
226 views
Why does Synplify error out whereas Xilinx XST passes without problems?
I have a project with several inferred dual port RAM blocks. The code for this dual port RAM is as follows:
...
3
votes
1answer
427 views
Unsigned addition overflow and synthesis
Let's say we have the following code where a, b and c are 3-bit wide representing unsigned ...
3
votes
1answer
463 views
What is the difference between reg and wire after synthesizing?
Assuming i have these two codes:
module wire_example( a, b, y);
input a, b;
output y;
wire a, b, y;
assign y = a & b;
endmodule
and the second one ...
2
votes
2answers
206 views
Using Webpack from the command line, but without a project file?
I recently got Webpack to sorta work for me on my Linux system... but I tried using ISim for simulation of my designs and got hit by a problem. And from what I can tell, this problem isn't Xilinx's ...
3
votes
2answers
264 views
Why does design_vision compile my carry-lookahead adder into a ripple-carry adder?
At my school we have Synopsis "design_vision" in the computer labs. I don't know how to use any of the features so to me it's just a schematic-drawing tool.
Out of curiosity, I hand-coded in Verilog ...
5
votes
2answers
1k views
Generic free Verilog synthesis tools?
Are there any free or open source synthesis tools available that can convert Verilog RTL into a generic gate netlist? (composed of generic NAND, NOR, XOR, D-flops/registers, etc. Optimization not ...
2
votes
2answers
592 views
XST Verilog - Casting real to integer constants
When I try to synthesize the following Verilog code using Xilinx XST, I get the error, "Unsupported real constant". If I try wrapping that expression in an $rtoi function, XST gives a different ...
0
votes
2answers
255 views
about Synplify VHDL (code imported from Xilinx ISE)
Good day,
Need some help. Start to work with Synopsys Synplify. Import my Xilinx ISE project (fully work).
Try to run and receive - "No matching overload for to_integer" for this line
...
5
votes
3answers
168 views
What options do I have when synthesising control registers?
When your design includes control registers that are set/read on a dedicated clock domain (SPI or I2C etc), how do you usually deal with those?
For instance:
Do you keep them on their own clock ...
5
votes
3answers
367 views
Which synthesis tools support VHDL libraries?
On various places across the net, I read that (some) synthesis tools do not respect VHDL libraries. These tools just throw all entities and packages into a single namespace, so that you cannot have ...
7
votes
2answers
2k views
VHDL: integers for synthesis?
I'm a bit confused on if I should be using integers in VHDL for synthesis signals and ports, etc.
I use std_logic at top level ports, but internally I was using ranged integers all over the place. ...
