This tag is relevant to issues with timing of a protocol or a standard. This could contain UART/ IIC etc. timing as well as timing for driving a motor.

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31 views

What is the refresh rate of a Neurosky headset?

I'm working on a project which is based on a Neurosky Headset. I need to receive brain wave data from that and use them in my Arduino. The most important thing here is that I need the data in ...
0
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0answers
23 views

how to calculate the Rise delay of the inverter

how do I calculate the rise delay of the inverter using the "non linear delay model" cell library which has 0.3ns input fall transition time and 0.16pf output load. ? ...
2
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2answers
79 views

How to analyse timing report for Xilinx FPGA

I'm trying to learn FPGA programming, my test project is a 5 stage pipelined MIPS CPU, which works. Up until now I have been optimising for area utilisation, however this has caused a very slow clock ...
0
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2answers
59 views

Short “High” Output In Response to a “High” Input

I am new to electrical engineering. I would like to make a circuit that will go to low after a short given time (lets say 0.2s) of being High. Using graphics I would like to convert this: to this: ...
0
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2answers
198 views

Simple circuit to convert a toggle switch turning on into a short pulse

I need to convert a permanent high signal into a short high pulse. I've got a design problem where I have a toggle switch that connects to a variable +11V to +17V power source, providing a signal to ...
1
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2answers
67 views

How to multiply base system clock using .xdc constraints in Vivado

This question may be ridiculously rudimentary but I have been going through Xilinx's available guides and videos tearing my hair out... my problem is simply this: I want to use the base 100Mhz clock ...
0
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2answers
75 views

Timing circuit with op amps and capacitors

I understand how a basic comparator op amp works and how a capacitor charges individually, but I can't seem to put it all together to make this circuit. I think I might be messing up with the voltage ...
0
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3answers
64 views

How to get equal number of clock cycles before ISR on an AVR

While writing a time critical piece of code for an Attiny13, I figured I could use the rising edge of an input as a trigger to read in some self clocking data. However, the number of clock cycles ...
0
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1answer
54 views

Propagation delay from a graph

I'm in the edX class and failed on all my three attempts on one of the questions. Clearly my reasoning is wrong, but I can't figure out where exactly. I would really appreciate if somebody could help ...
0
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0answers
29 views

eth008 relay pulse setup on phone app

Is there a way to set up relay pulse times for the Android/iPhone "Devantech" app when using ETH008 board? I noticed that it is possible using the test program on PC, but not possible on the app OR: ...
1
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1answer
113 views

What's the dwell signals?

Today When I was seeing this page(Digital multimeters (DMM or DVOM) part) I saw this part: What does "automotive timing"? and What's the dwell signals? are these electronic concepts?
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0answers
44 views

P-Channel FET Switching Time

I have a question about the circuit shown below. Specifically, I am looking to calculate the time that it takes to fully enhance the PFET and activate 3V3_SW1 after the control signal transitions ...
0
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3answers
78 views

How does oscillator frequency stability affect timing? [duplicate]

If, for example, a crystal oscillator is specified as +/- 100ppm what does that mean? That the exact frequency is uncertain to that degree, or that the frequency varies by that degree over normal ...
0
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0answers
167 views

Altera TimeQuest SDC I/O constraint with SDRAM - does input delay include output hold time?

I am using a Altera Stratix IV with an ISSI 42x SDRAM device. I'm trying to understand the timing constraints for the data inputs of the FPGA (which is the data output from the SDRAM). According to ...
2
votes
1answer
150 views

Setup and Hold time VS temperature (and temperature inversion)

So I know that propagation delay and timing inside an ASIC are affected by temperature. In the old days things went faster when colder and slower when hotter. Now at 90nm and below there is ...
1
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2answers
310 views

SPI chip select --> data + clock delay tolerance

I know this likely depends on the specific chips and devices being used, but I'm just looking for estimate ballpark numbers. I'm considering using the spi protocol for a project, and I can't seem to ...
2
votes
1answer
75 views

How to simply introduce a short (2ns) delay on a line?

We found a race condition in one of our production circuits. A CPLD chip acting as address decoder plus a couple other functions, receives address and data signal over two buses. A peripheral device ...
2
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3answers
185 views

Reset the raspberry pi with a relay

I'm going to use my Rasp as a GPS tracking and it should be running even if the car is off; however, I don't want run out the car battery. To make it happens I added a battery controller ...
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1answer
1k views

Calculate the UART Baud Rate register for PIC devices

How do I calculate the UART configuration register values for a PIC 24F device, based on a desired Baud rate? Currently the UART module has 2 values that affect the Baud rate, BRG (16-bit register) ...
0
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1answer
135 views

Timing/buffering issue with Digilent's EPP on Basys2?

I have a Digilent Basys2 FPGA, and I'm implementing the EPP interface described in http://www.digilentinc.com/Data/Products/ADEPT/DpimRef%20programmers%20manual.pdf. This allows a program called ...
1
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1answer
104 views

FPGA simulates well and passes timing check but fails in PCB

So you have finished your FPGA design. You have simulated it with an extensive test bench created by a different engineer and it works, event at speed after it has been compiled, placed and routed. ...
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0answers
34 views

Timing with jittery pll

Ok this is sort of a follow up to my previous question where I have a 100Mhz input clock with 1ns Jitter, going into a pll that doubles that to 200Mhz. The 100Mhz clock is fed to logic block A, the ...
0
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1answer
166 views

VHDL delay mechanism

I have difficulty understanding how the delay (mainly inertial delay: AFTER) mechanism works in VHDL. I'll start with this: target <= waveform AFTER 3 NS; As ...
0
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1answer
80 views

AVR SPI slower than expected

I'm running an ATMega88A at 8MHz and have the SPI configured to run at Fosc/2 = 4MHz. In theory, shifting out 5000 bytes over SPI should take 1/4000000 * 8 * 5000 = 10ms. But according to the ...
1
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1answer
116 views

AVR SPI2X has no effect

I've got an ATMega88A configured to run on internal 8MHz clock: lfuse = 0xE2 hfuse = 0xDF efuse = 0x01 F_CPU defined as 8000000 This in confirmed in the 'real ...
0
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0answers
115 views

Interpolate DDR3 timing from DDR3-1600 to DDR3-1866?

This is an interesting math + electrical engineering problem. I have DDR3-2133 memory but it had presets for DDR3-1600 and DDR3-2133 but the fastest my motherboard supports is DDR3-1833. That means I ...
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2answers
232 views

ATtiny2313 vs ATtiny84 software compatibility

I make and sell a variant of the USBtiny AVR programmer. It uses an ATtiny2313 clocked at 12 MHz and does bit-banged USB using hand-tuned assembly language (that someone else wrote - it's an open ...
1
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1answer
212 views

driving LEDs via a PI a attiny and TLC5940 (validation) and possible powering issues

at the moment I am planning my first real (big) electronics project. I want to build a LED lamp, that can be controlled by a RaspberryPi (for e.g. programming a binary clock or changing the brightness ...
0
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2answers
359 views

Setup and hold time

Of the setup and hold timing constraints which are to be met to get a stable output, which one is critical in estimating the maximum clock frequency of a circuit?
1
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1answer
524 views

DDR4 routing / spacing guidelines

Where can I find the source of routing guidelines for DDR4. I'm talking about things like DQ to DQS timing, maximum length difference in ps for address and command and maybe maximum parallel run ...
3
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3answers
251 views

32-way Mux Produces Horrible Timing Problems

I'm coding a 32 way mux in verilog. The input is a counter which counts from 0 to 31, incrementing each clock cycle. Each counter value selects a different slice of a vector as an output. In my ...
2
votes
1answer
797 views

What actually happens in a RC circuit?

I'm currently working my way through a beginner's electronics book(electronics for dummies) where i am introduced to RC circuits as shown in the schematic below. simulate this circuit – ...
1
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1answer
227 views

Fixing 1 failing timing constraint in Xilinx

In the end of my project I have a timing constraint failure as follows : clk_in is the 100 Mhz system clock on ML507 I don't know why it is not meeting the ...
0
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1answer
80 views

Xilinx Design Summary

My project is finished and Xilinx gives lots of statistics in the summary like : How shall I evaluate these values, what can I say about them? What means what? Is this report good or bad? With ...
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0answers
271 views

STM32 FSMC Timing Computation

I'm working on FSMC protocol of STM32 micro controller The formula for calculate FSMC timing is below, but I have a hard time understanding it. From ST Application Note Can someone walk be ...
0
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1answer
301 views

Question about function set_dont_touch_network

I was trying to debug a script written for synthesis using Synopsys primetime. Can someone explain me what is the function of set_dont_touch_network? I have these ...
2
votes
1answer
78 views

Setting up data prior to a rising edge - what's best practice?

I'm a newbie, playing around with a very simple single port block RAM (on an FPGA actually). Its 'read'-timing is standard stuff - i) An address on the RAM input gets latched on a first rising clock ...
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4answers
121 views

Arduino Uno pin response speed

We are attempting to build a coilgun with multiple coils, and each coil needs to be energized and deenergized at precise time intervals. For cost (and inexperience) reasons, we are considering using ...
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1answer
137 views

Timing on a pipeline

I'm basically reviewing for a test in my computer organization class and there's a question about pipelining. The questions is: "If the pipeline consists of 6 stages and each stage executes its ...
0
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2answers
131 views

Timing Diagram question

Can anyone check my timing diagram for me? I have my exam tomorrow and just want to make sure I am understanding these correctly: Any feedback is appreciated. Thanks in advance
0
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1answer
114 views

Verilog “Tick” Generation; Concern over hold time?

In Pong Chu's "FPGA Prototyping by Verilog Examples" he recommends using a periodic enable "tick" to divide the clock while maintaining a synchronous system (to avoid putting the system clock through ...
1
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1answer
439 views

Help me understand this shift register timing diagram

My basic understanding of using a shift register to convert serial to parallel data is this: On every clock pulse, the state of the serial data pin is read As data is read, it gets shifted in to the ...
2
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2answers
807 views

How exactly does this shift-register work? - Fairchild 74HC589

I'm using a PISO shift-register, specifically the Fairchild Semiconductor 74HC589. I got the jist of the workings of a generic shift-register via the very useful animated GIF in Wikipedia link above, ...
0
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3answers
345 views

How to trigger something once a day [duplicate]

What would be the right thing to use if I want the base of a transistor to be high for 12 hours and low for 12 hours? I ask because I would like to make a circuit that regulates temperature in a ...
1
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1answer
298 views

How to determine I2C Master timing parameters

I am relatively new to I2C, but I have done much reading on the topic and I am confused as to the timing parameters necessary when designing an I2C Master. I know of this chart from the manual on ...
6
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1answer
843 views

VGA Decoding - Dealing with tolerances

Update: The VGA Simulator is up and running. You can go simulate your own designs or just use the example file to see it working. I also wrote a blog post to help anyone get started using it for ...
2
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6answers
1k views

What exactly is the start bit error in UART?

The questions are in the bottom of the post. I understand that there are a lot of sources of timing errors inherited in UART communications. The magnitude of these errors is what limits the ...
3
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4answers
258 views

How are LEDs timed? (How is the pulse latency measured?)

Please excuse the awkward phrasing of the question; it seems that LEDs have pulse latencies of nanosecond and sub-nanosecond durations. The question is, how was it possible to measure such precise ...
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0answers
83 views

SDRAM timing requirements

I am interfacing a Micron MT48H16M32LFCM-75 SDRAM with an Atmel AT91SAM9G20 and I need to verify on paper (as far as possible), that the timing specifications between those two devices are compatible. ...
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0answers
752 views

ASIC timing constraints via SDC: How to correctly specify a multiplexed clock?

Introduction Having found multiple, sometimes conflicting or incomplete information on the internet and in some training classes about how to create timing constraints in SDC format correctly, I'd ...