This tag is relevant to issues with timing of a protocol or a standard. This could contain UART/ IIC etc. timing as well as timing for driving a motor.

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133 views

How to implement precise delay function in Keil c51 (for c8051) that waits exact amount of CPU clocks, the number of clocks ranges from 1 to 255

So as the title says, I need exact delays, not too long, ideally in the range of 0 - 350 CPU clocks, but if anything would work in narrower range the absolute minimum range is 20 - 127 CPU clocks. So ...
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0answers
11 views

PartSim - Not possible to view full waveform range

I would never normally ask something like this on here but have been struggling for a while. I'm not sure if i'm missing something obvious but I have the circuit below. When the wire is disconnected ...
5
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0answers
329 views

Time synchronization of two computers [migrated]

I like to synchronize the timing of two computers that are connected via Ethernet (with no router in between) and apart from each other 100 or so meters. There are several protocols that does time ...
3
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1answer
72 views

Advantage of clock enable over clock division

I have an FPGA design which uses different clocks. There is a 100 MHz reference clock provided by an oscillator. The reference clock is used in a DCM (Xilinx FPGA) to generate 3 related clocks, 100 ...
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2answers
61 views

0.5 to 4.0 hours Timing Circuit

This is my first electronics project - apologies for the noob question. I wish to control a power relay, trigged via motion / PIR. After the PIR triggers the relay, the relay should stay "on" for a ...
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1answer
24 views

Quartus Waveform File Representation

I have selected the inputs as 8 bit count values that increment over time. The 8 bit value should be parallel in and parallel out. But the bits are spaced over time. Can you please explain why the ...
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1answer
136 views

Using BLE, how fast can I get ~50 bytes of data from the master to a slave? How does that change when increasing the number of slaves present?

In personal project of mine I'm looking to have a system where a number peripherals need to have provided to them, in as real-time as possible, small (~50 bytes max) amounts of information from a ...
3
votes
1answer
62 views

How to delay a relay closing?

I have a situation where I'd like to delay the closing of an off the shelf relay by ~5 seconds. Assuming it is a 5V coil, and switching 12 V, I'd like the following: t 0:00: 5v applied to input, ...
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1answer
31 views

tCHSL SPI timing

I was going thru the datasheet of Micron SPI Flash. The timing diagram has tCHSL : S# not active hold time (relative to CLK) What exactly is this? According to the timing diagram, this is measured ...
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1answer
107 views

Why there are AC timing characteristics but not DC in I2C interfaced chip?

I'm quite newbie in electronics, and I'd like to learn why there are AC timing characteristics to this particular EEPROM (24LC512) that I'm using but none for DC? Does AC timing constraints apply to ...
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1answer
79 views

Memory timing values for microprocessor (8086)

There is something vague with the memory timing operation of 8086 microprocessor as I read from many sources. There is a TAVDV which is the time from when a valid address goes on the bus until a valid ...
0
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1answer
153 views

nrf24l01 frequency switch timing

How much time does the nrf24l01+ take to switch frequency through RF_CH? Can this switching time be parallel to switch between Tx/Rx/Standby modes?
1
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1answer
84 views

Tradeoffs and design considerations when choosing a crystal + PLL combo for MCU timing

I am in the process of doing more work on ARM platforms (specifically for this example the Atmel SAMD10 Cortex M0+ line). The clock flexibility and lack of ridiculous fuse settings feels like a (very ...
0
votes
1answer
99 views

Multiplication Gate Delay

How do you find the gate delay for a basic multiplier circuit that ANDs each bit of the multiplicand with the multiplier then shifts the multiplicand left and the multiplier right until the multiplier ...
0
votes
1answer
270 views

PWM (Pulse Width Modulation) vs DAC (Digital Analog Convertor)

I am working on a project where I take over the control of a Nintendo 3DS Touch Screen. The touch screen is a 4 pin system. I have it all wired up and working, however I cannot get the screen to ...
1
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1answer
98 views

Multioperand pipelined adder

in order to explain how to a pipelined multioperand adder could be implemented my book shows the image reported below. The idea is to use three adder with 4 stage pipeline. However i tried to make a ...
0
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1answer
62 views

Timing closure suggestions

I've a FPGA design ( I didn't write a single line of sources code) and I've to add a module ( in the design there is a Wishbone bus where it's possible to link others wishbone interface ). The modules ...
0
votes
3answers
67 views

How to measure temporary drop in voltage with meter

What's the easiest way to measure the period of time between the "peaks" when a 5V DC signal goes from high to low to high? I'm trying to debug a power-loss problem, and one of the solutions I'm ...
2
votes
2answers
448 views

How to analyse timing report for Xilinx FPGA

I'm trying to learn FPGA programming, my test project is a 5 stage pipelined MIPS CPU, which works. Up until now I have been optimising for area utilisation, however this has caused a very slow clock ...
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2answers
78 views

Short “High” Output In Response to a “High” Input

I am new to electrical engineering. I would like to make a circuit that will go to low after a short given time (lets say 0.2s) of being High. Using graphics I would like to convert this: to this: ...
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2answers
831 views

Simple circuit to convert a toggle switch turning on into a short pulse

I need to convert a permanent high signal into a short high pulse. I've got a design problem where I have a toggle switch that connects to a variable +11V to +17V power source, providing a signal to ...
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vote
2answers
369 views

How to multiply base system clock using .xdc constraints in Vivado

This question may be ridiculously rudimentary but I have been going through Xilinx's available guides and videos tearing my hair out... my problem is simply this: I want to use the base 100Mhz clock ...
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2answers
220 views

Timing circuit with op amps and capacitors

I understand how a basic comparator op amp works and how a capacitor charges individually, but I can't seem to put it all together to make this circuit. I think I might be messing up with the voltage ...
0
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3answers
76 views

How to get equal number of clock cycles before ISR on an AVR

While writing a time critical piece of code for an Attiny13, I figured I could use the rising edge of an input as a trigger to read in some self clocking data. However, the number of clock cycles ...
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1answer
129 views

Propagation delay from a graph

I'm in the edX class and failed on all my three attempts on one of the questions. Clearly my reasoning is wrong, but I can't figure out where exactly. I would really appreciate if somebody could help ...
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1answer
237 views

What's the dwell signals?

Today When I was seeing this page(Digital multimeters (DMM or DVOM) part) I saw this part: What does "automotive timing"? and What's the dwell signals? are these electronic concepts?
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3answers
406 views

How does oscillator frequency stability affect timing? [duplicate]

If, for example, a crystal oscillator is specified as +/- 100ppm what does that mean? That the exact frequency is uncertain to that degree, or that the frequency varies by that degree over normal ...
2
votes
1answer
391 views

Setup and Hold time VS temperature (and temperature inversion)

So I know that propagation delay and timing inside an ASIC are affected by temperature. In the old days things went faster when colder and slower when hotter. Now at 90nm and below there is ...
1
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2answers
1k views

SPI chip select --> data + clock delay tolerance

I know this likely depends on the specific chips and devices being used, but I'm just looking for estimate ballpark numbers. I'm considering using the spi protocol for a project, and I can't seem to ...
3
votes
1answer
102 views

How to simply introduce a short (2ns) delay on a line?

We found a race condition in one of our production circuits. A CPLD chip acting as address decoder plus a couple other functions, receives address and data signal over two buses. A peripheral device ...
2
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3answers
244 views

Reset the raspberry pi with a relay

I'm going to use my Rasp as a GPS tracking and it should be running even if the car is off; however, I don't want run out the car battery. To make it happens I added a battery controller ...
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votes
1answer
3k views

Calculate the UART Baud Rate register for PIC devices

How do I calculate the UART configuration register values for a PIC 24F device, based on a desired Baud rate? Currently the UART module has 2 values that affect the Baud rate, BRG (16-bit register) ...
0
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1answer
211 views

Timing/buffering issue with Digilent's EPP on Basys2?

I have a Digilent Basys2 FPGA, and I'm implementing the EPP interface described in http://www.digilentinc.com/Data/Products/ADEPT/DpimRef%20programmers%20manual.pdf. This allows a program called ...
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1answer
132 views

FPGA simulates well and passes timing check but fails in PCB

So you have finished your FPGA design. You have simulated it with an extensive test bench created by a different engineer and it works, event at speed after it has been compiled, placed and routed. ...
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1answer
253 views

VHDL delay mechanism

I have difficulty understanding how the delay (mainly inertial delay: AFTER) mechanism works in VHDL. I'll start with this: target <= waveform AFTER 3 NS; As ...
1
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2answers
174 views

AVR SPI slower than expected

I'm running an ATMega88A at 8MHz and have the SPI configured to run at Fosc/2 = 4MHz. In theory, shifting out 5000 bytes over SPI should take 1/4000000 * 8 * 5000 = 10ms. But according to the ...
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1answer
205 views

AVR SPI2X has no effect

I've got an ATMega88A configured to run on internal 8MHz clock: lfuse = 0xE2 hfuse = 0xDF efuse = 0x01 F_CPU defined as 8000000 This in confirmed in the 'real ...
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2answers
359 views

ATtiny2313 vs ATtiny84 software compatibility

I make and sell a variant of the USBtiny AVR programmer. It uses an ATtiny2313 clocked at 12 MHz and does bit-banged USB using hand-tuned assembly language (that someone else wrote - it's an open ...
1
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1answer
319 views

driving LEDs via a PI a attiny and TLC5940 (validation) and possible powering issues

at the moment I am planning my first real (big) electronics project. I want to build a LED lamp, that can be controlled by a RaspberryPi (for e.g. programming a binary clock or changing the brightness ...
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2answers
842 views

Setup and hold time

Of the setup and hold timing constraints which are to be met to get a stable output, which one is critical in estimating the maximum clock frequency of a circuit?
2
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1answer
1k views

DDR4 routing / spacing guidelines

Where can I find the source of routing guidelines for DDR4. I'm talking about things like DQ to DQS timing, maximum length difference in ps for address and command and maybe maximum parallel run ...
3
votes
3answers
354 views

32-way Mux Produces Horrible Timing Problems

I'm coding a 32 way mux in verilog. The input is a counter which counts from 0 to 31, incrementing each clock cycle. Each counter value selects a different slice of a vector as an output. In my ...
2
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1answer
3k views

What actually happens in a RC circuit?

I'm currently working my way through a beginner's electronics book(electronics for dummies) where i am introduced to RC circuits as shown in the schematic below. simulate this circuit – ...
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1answer
408 views

Fixing 1 failing timing constraint in Xilinx

In the end of my project I have a timing constraint failure as follows : clk_in is the 100 Mhz system clock on ML507 I don't know why it is not meeting the ...
0
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1answer
102 views

Xilinx Design Summary

My project is finished and Xilinx gives lots of statistics in the summary like : How shall I evaluate these values, what can I say about them? What means what? Is this report good or bad? With ...
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0answers
425 views

STM32 FSMC Timing Computation

I'm working on FSMC protocol of STM32 micro controller The formula for calculate FSMC timing is below, but I have a hard time understanding it. From ST Application Note Can someone walk be ...
0
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1answer
538 views

Question about function set_dont_touch_network

I was trying to debug a script written for synthesis using Synopsys primetime. Can someone explain me what is the function of set_dont_touch_network? I have these ...
2
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1answer
119 views

Setting up data prior to a rising edge - what's best practice?

I'm a newbie, playing around with a very simple single port block RAM (on an FPGA actually). Its 'read'-timing is standard stuff - i) An address on the RAM input gets latched on a first rising clock ...
2
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4answers
233 views

Arduino Uno pin response speed

We are attempting to build a coilgun with multiple coils, and each coil needs to be energized and deenergized at precise time intervals. For cost (and inexperience) reasons, we are considering using ...
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1answer
183 views

Timing on a pipeline

I'm basically reviewing for a test in my computer organization class and there's a question about pipelining. The questions is: "If the pipeline consists of 6 stages and each stage executes its ...