This tag is relevant to issues with timing of a protocol or a standard. This could contain UART/ IIC etc. timing as well as timing for driving a motor.

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36 views

driving LEDs via a PI a attiny and TLC5940 (validation) and possible powering issues

at the moment I am planning my first real (big) electronics project. I want to build a LED lamp, that can be controlled by a RaspberryPi (for e.g. programming a binary clock or changing the brightness ...
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1answer
38 views

Setup and hold time

Of the setup and hold timing constraints which are to be met to get a stable output, which one is critical in estimating the maximum clock frequency of a circuit?
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1answer
58 views

DDR4 routing / spacing guidelines

Where can I find the source of routing guidelines for DDR4. I'm talking about things like DQ to DQS timing, maximum length difference in ps for address and command and maybe maximum parallel run ...
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3answers
101 views

32-way Mux Produces Horrible Timing Problems

I'm coding a 32 way mux in verilog. The input is a counter which counts from 0 to 31, incrementing each clock cycle. Each counter value selects a different slice of a vector as an output. In my ...
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2answers
129 views

What actually happens in a RC circuit?

I'm currently working my way through a beginner's electronics book(electronics for dummies) where i am introduced to RC circuits as shown in the schematic below. simulate this circuit – ...
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1answer
68 views

Fixing 1 failing timing constraint in Xilinx

In the end of my project I have a timing constraint failure as follows : clk_in is the 100 Mhz system clock on ML507 I don't know why it is not meeting the ...
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0answers
49 views

Xilinx Design Summary

My project is finished and Xilinx gives lots of statistics in the summary like : How shall I evaluate these values, what can I say about them? What means what? Is this report good or bad? With ...
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0answers
78 views

STM32 FSMC Timing Computation

I'm working on FSMC protocol of STM32 micro controller The formula for calculate FSMC timing is below, but I have a hard time understanding it. From ST Application Note Can someone walk be ...
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1answer
76 views

Question about function set_dont_touch_network

I was trying to debug a script written for synthesis using Synopsys primetime. Can someone explain me what is the function of set_dont_touch_network? I have these ...
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1answer
45 views

Setting up data prior to a rising edge - what's best practice?

I'm a newbie, playing around with a very simple single port block RAM (on an FPGA actually). Its 'read'-timing is standard stuff - i) An address on the RAM input gets latched on a first rising clock ...
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4answers
66 views

Arduino Uno pin response speed

We are attempting to build a coilgun with multiple coils, and each coil needs to be energized and deenergized at precise time intervals. For cost (and inexperience) reasons, we are considering using ...
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1answer
69 views

Timing on a pipeline

I'm basically reviewing for a test in my computer organization class and there's a question about pipelining. The questions is: "If the pipeline consists of 6 stages and each stage executes its ...
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2answers
77 views

Timing Diagram question

Can anyone check my timing diagram for me? I have my exam tomorrow and just want to make sure I am understanding these correctly: Any feedback is appreciated. Thanks in advance
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1answer
48 views

Verilog “Tick” Generation; Concern over hold time?

In Pong Chu's "FPGA Prototyping by Verilog Examples" he recommends using a periodic enable "tick" to divide the clock while maintaining a synchronous system (to avoid putting the system clock through ...
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1answer
110 views

Help me understand this shift register timing diagram

My basic understanding of using a shift register to convert serial to parallel data is this: On every clock pulse, the state of the serial data pin is read As data is read, it gets shifted in to the ...
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2answers
329 views

How exactly does this shift-register work? - Fairchild 74HC589

I'm using a PISO shift-register, specifically the Fairchild Semiconductor 74HC589. I got the jist of the workings of a generic shift-register via the very useful animated GIF in Wikipedia link above, ...
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3answers
138 views

How to trigger something once a day [duplicate]

What would be the right thing to use if I want the base of a transistor to be high for 12 hours and low for 12 hours? I ask because I would like to make a circuit that regulates temperature in a ...
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2answers
139 views

How to determine I2C Master timing parameters

I am relatively new to I2C, but I have done much reading on the topic and I am confused as to the timing parameters necessary when designing an I2C Master. I know of this chart from the manual on ...
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1answer
480 views

VGA Decoding - Dealing with tolerances

Update: The VGA Simulator is up and running. You can go simulate your own designs or just use the example file to see it working. I also wrote a blog post to help anyone get started using it for ...
2
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6answers
380 views

What exactly is the start bit error in UART?

The questions are in the bottom of the post. I understand that there are a lot of sources of timing errors inherited in UART communications. The magnitude of these errors is what limits the ...
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4answers
204 views

How are LEDs timed? (How is the pulse latency measured?)

Please excuse the awkward phrasing of the question; it seems that LEDs have pulse latencies of nanosecond and sub-nanosecond durations. The question is, how was it possible to measure such precise ...
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0answers
52 views

SDRAM timing requirements

I am interfacing a Micron MT48H16M32LFCM-75 SDRAM with an Atmel AT91SAM9G20 and I need to verify on paper (as far as possible), that the timing specifications between those two devices are compatible. ...
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0answers
294 views

ASIC timing constraints via SDC: How to correctly specify a multiplexed clock?

Introduction Having found multiple, sometimes conflicting or incomplete information on the internet and in some training classes about how to create timing constraints in SDC format correctly, I'd ...
3
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1answer
846 views

ASIC timing constraints via SDC: How to correctly specify a ripple-divided clock?

Introduction Having found multiple, sometimes conflicting or incomplete information on the internet and in some training classes about how to create timing constraints in SDC format correctly, I'd ...
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2answers
124 views

Debugging DDR bus issues

We have an SBC board, in the style of the Leopardboard or Beagleboard, that is misbehaving. It's based on the Leopardboard design (TI-DM368 CPU, DDR2 RAM, NAND Flash). Developing software on the ...
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1answer
124 views

DDR2 CAS Latency - is it fixed to clock-cycles or time?

We have a (new, prototype) board that is, at best, temperamental. It's using a Micron MT47H64M16HR-25:H DDR RAM, the design reference board uses a Micron MT47H64M16HR-25E:H. Only one letter different, ...
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1answer
144 views

Synchronous circuit timing diagram

I am little confused on how to fill in this timing diagram for the above circuit. Can someone help me out?
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3answers
99 views

Program w/ 2 loops and timing and such

So let's say i have a prog that has a fast loop @e 64uS, and a slow loop @e 8mS. If the fast loop takes 34uS to execute do I need to make sure the slow loop can execute in 30uS, so as to not be ...
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1answer
127 views

MSP430 instruction timing

I have a MSP430G2231. My ultimate goal is to communicate with a device that wants 1 bit of data each microsecond. I believe this is too fast for timers, meaning I need to handwrite assembly code that ...
3
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3answers
136 views

Timings constrains for isochronous clocks

In my Verilog design, I have two clocks of the same frequency, but of different phase. At the moment, my timing constraints look like this: ...
0
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1answer
138 views

Understanding rc time constant

I get that if you put a resistor in series with a capacitor and add DC voltage, the cap will take longer to charge up. How can I calculate, how long it takes for the capacitor to charge up/discharge ...
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2answers
761 views

Synthesis timing summary in Xilinx tool (ISE)

I'm getting the following timing summary from the synthesis: ...
10
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4answers
2k views

MIDI sequencer timing accuracy using the Arduino

I build these music sequencers. Only it's not exactly a sequencer, it's a physical interface for a sequencer. The sequencer is an application that runs on a laptop that the sequencer connects to, ...
2
votes
2answers
192 views

How can I control 8 LEDs with a timing delay with only one microcontroller (PIC12) written in Assembly?

I can have 5 I/O pins enabled. I'm just confused on how to control them individually.
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3answers
199 views

process timing on FPGA

I'm new to fpgas, and there are some timing subtleties that I'm not sure I understand: if all my synchronous processes are triggered on the same edge, then that means my inputs are 'captured' on one ...
2
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2answers
304 views

Receive bytes from UART camera

I am using a dsPIC33E MUC to interface an UART camera(VGA) at 115.2Kbps. The purpose is to save an image to a SD card. The program I wrote works well except that it's inside a loop checking if the ...
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0answers
114 views

Interfacing with ROM chip(C, ASM, & Timing Diagrams)

I am attempting to interface with the following ROM chip via my mc9s12 microcontroller: http://www.alldatasheet.com/datasheet-pdf/pdf/55460/AMD/AM29F040B.html I have several functions written in C, ...
3
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1answer
268 views

SPI routing question…Maximum length SPI can be routed

Basically my question is regarding maximum length of SPI routing, and route efficiently in my scenario and any timing issues(Setup and Hold). I am just explaining my scenario. Please bear with me, it ...
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0answers
128 views

Are there any metastability issues with microcontroller SPI slave ports that can operate during sleep?

If one is using SPI to interface two microcontrollers that may spend much of their time sleeping, and if the SPI slave port is supposed to wake up its controller when data is received, that would ...
3
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2answers
198 views

Flip flops with multiple clocks

Assume I have 2 flipflops FF1 and FF2 which are driven using multiple clocks. What might be the possible violations that we would come across? I was asked this in an interview for which I answered ...
0
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1answer
93 views

Do I have to equate clock and Data Bus propagation delay for Transmission Lines?

My question is about SDRAM timings for clock and DataBUS. Som designer advice that clock pin has to be the shortest one. Data Bus may be longer than these because of the some problems. But clock trace ...
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1answer
344 views

Can someone help check my solution for this timing diagram?

I've been working on some timing diagrams and I keep mixing up the behaviors for the different flip flops. EDIT: I think I have the logic correct. If someone could please let me know if I'm ...
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2answers
370 views

How do I use T-Flip Flops to derive circuits - given the clock signal speed?

I've been trying to do my EE homework for several hours and cannot figure out how to do this stuff.. I've read through the chapter multiple times, searched YouTube and Google, and nothing seems to ...
2
votes
3answers
695 views

Circuit that can convert current pulses to voltage

I have an anemometer which outputs current pulses. I can't take it apart but I know there is a phototransistor and LED in parallel shining through holes to it. I was told that with 30m/s wind there ...
0
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1answer
898 views

hold time violation during FPGA post place and route simulation in modelsim

I am designing a simple encryption circuit on Xilinx Virtex-5 FPGA. I have given the timing constraint in the UCF as below: ...
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1answer
452 views

Rise time for second order RC filter?

Can somebody help me in deriving the expression for rise-time for second order RC filter. simulate this circuit – Schematic created using CircuitLab
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3answers
221 views

I need help Building A Solid state Electro magnetic Mixer

I'm just getting into electronics, and I would like to build an electromagnetic mixer. See here. Most of the tutorials I have found have magnets stuck to a motor spinning under a non magnetic material ...
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2answers
343 views

Is there a glitch / race condition at the output of this circuit?

The input rising and falling edges occur at time t = 0. The propagation delays of the respective gates are 3 and 4 ns, as shown. According to my analysis, the waveforms are as below: As I've ...
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2answers
421 views

what is 555 Timer? [closed]

what is timer 555 ?? can any one give me some links which talk about this topic ? or some references ? or texts ? how can we use this kind of timer ? how to create it ? any information will be ...
2
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1answer
495 views

Logisim: timing problems setting register

I'm having some problems understanding the timing behaviors I observe in Logisim. I've isolated some cases which illustrate the problem. Say I have a register (1-bit, to keep it simple), which is ...