This tag is relevant to issues with timing of a protocol or a standard. This could contain UART/ IIC etc. timing as well as timing for driving a motor.

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Timing/buffering issue with Digilent's EPP on Basys2?

I have a Digilent Basys2 FPGA, and I'm implementing the EPP interface described in http://www.digilentinc.com/Data/Products/ADEPT/DpimRef%20programmers%20manual.pdf. This allows a program called ...
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1answer
66 views

FPGA simulates well and passes timing check but fails in PCB

So you have finished your FPGA design. You have simulated it with an extensive test bench created by a different engineer and it works, event at speed after it has been compiled, placed and routed. ...
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27 views

Timing with jittery pll

Ok this is sort of a follow up to my previous question where I have a 100Mhz input clock with 1ns Jitter, going into a pll that doubles that to 200Mhz. The 100Mhz clock is fed to logic block A, the ...
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1answer
73 views

VHDL delay mechanism

I have difficulty understanding how the delay (mainly inertial delay: AFTER) mechanism works in VHDL. I'll start with this: target <= waveform AFTER 3 NS; As ...
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1answer
47 views

AVR SPI slower than expected

I'm running an ATMega88A at 8MHz and have the SPI configured to run at Fosc/2 = 4MHz. In theory, shifting out 5000 bytes over SPI should take 1/4000000 * 8 * 5000 = 10ms. But according to the ...
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1answer
32 views

AVR SPI2X has no effect

I've got an ATMega88A configured to run on internal 8MHz clock: lfuse = 0xE2 hfuse = 0xDF efuse = 0x01 F_CPU defined as 8000000 This in confirmed in the 'real ...
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0answers
52 views

Interpolate DDR3 timing from DDR3-1600 to DDR3-1866?

This is an interesting math + electrical engineering problem. I have DDR3-2133 memory but it had presets for DDR3-1600 and DDR3-2133 but the fastest my motherboard supports is DDR3-1833. That means I ...
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2answers
142 views

ATtiny2313 vs ATtiny84 software compatibility

I make and sell a variant of the USBtiny AVR programmer. It uses an ATtiny2313 clocked at 12 MHz and does bit-banged USB using hand-tuned assembly language (that someone else wrote - it's an open ...
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1answer
99 views

driving LEDs via a PI a attiny and TLC5940 (validation) and possible powering issues

at the moment I am planning my first real (big) electronics project. I want to build a LED lamp, that can be controlled by a RaspberryPi (for e.g. programming a binary clock or changing the brightness ...
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2answers
86 views

Setup and hold time

Of the setup and hold timing constraints which are to be met to get a stable output, which one is critical in estimating the maximum clock frequency of a circuit?
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1answer
122 views

DDR4 routing / spacing guidelines

Where can I find the source of routing guidelines for DDR4. I'm talking about things like DQ to DQS timing, maximum length difference in ps for address and command and maybe maximum parallel run ...
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3answers
151 views

32-way Mux Produces Horrible Timing Problems

I'm coding a 32 way mux in verilog. The input is a counter which counts from 0 to 31, incrementing each clock cycle. Each counter value selects a different slice of a vector as an output. In my ...
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1answer
176 views

What actually happens in a RC circuit?

I'm currently working my way through a beginner's electronics book(electronics for dummies) where i am introduced to RC circuits as shown in the schematic below. simulate this circuit – ...
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1answer
100 views

Fixing 1 failing timing constraint in Xilinx

In the end of my project I have a timing constraint failure as follows : clk_in is the 100 Mhz system clock on ML507 I don't know why it is not meeting the ...
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1answer
62 views

Xilinx Design Summary

My project is finished and Xilinx gives lots of statistics in the summary like : How shall I evaluate these values, what can I say about them? What means what? Is this report good or bad? With ...
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0answers
123 views

STM32 FSMC Timing Computation

I'm working on FSMC protocol of STM32 micro controller The formula for calculate FSMC timing is below, but I have a hard time understanding it. From ST Application Note Can someone walk be ...
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1answer
133 views

Question about function set_dont_touch_network

I was trying to debug a script written for synthesis using Synopsys primetime. Can someone explain me what is the function of set_dont_touch_network? I have these ...
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1answer
50 views

Setting up data prior to a rising edge - what's best practice?

I'm a newbie, playing around with a very simple single port block RAM (on an FPGA actually). Its 'read'-timing is standard stuff - i) An address on the RAM input gets latched on a first rising clock ...
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4answers
71 views

Arduino Uno pin response speed

We are attempting to build a coilgun with multiple coils, and each coil needs to be energized and deenergized at precise time intervals. For cost (and inexperience) reasons, we are considering using ...
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1answer
84 views

Timing on a pipeline

I'm basically reviewing for a test in my computer organization class and there's a question about pipelining. The questions is: "If the pipeline consists of 6 stages and each stage executes its ...
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2answers
93 views

Timing Diagram question

Can anyone check my timing diagram for me? I have my exam tomorrow and just want to make sure I am understanding these correctly: Any feedback is appreciated. Thanks in advance
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1answer
60 views

Verilog “Tick” Generation; Concern over hold time?

In Pong Chu's "FPGA Prototyping by Verilog Examples" he recommends using a periodic enable "tick" to divide the clock while maintaining a synchronous system (to avoid putting the system clock through ...
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1answer
201 views

Help me understand this shift register timing diagram

My basic understanding of using a shift register to convert serial to parallel data is this: On every clock pulse, the state of the serial data pin is read As data is read, it gets shifted in to the ...
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2answers
452 views

How exactly does this shift-register work? - Fairchild 74HC589

I'm using a PISO shift-register, specifically the Fairchild Semiconductor 74HC589. I got the jist of the workings of a generic shift-register via the very useful animated GIF in Wikipedia link above, ...
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3answers
190 views

How to trigger something once a day [duplicate]

What would be the right thing to use if I want the base of a transistor to be high for 12 hours and low for 12 hours? I ask because I would like to make a circuit that regulates temperature in a ...
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2answers
186 views

How to determine I2C Master timing parameters

I am relatively new to I2C, but I have done much reading on the topic and I am confused as to the timing parameters necessary when designing an I2C Master. I know of this chart from the manual on ...
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1answer
553 views

VGA Decoding - Dealing with tolerances

Update: The VGA Simulator is up and running. You can go simulate your own designs or just use the example file to see it working. I also wrote a blog post to help anyone get started using it for ...
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6answers
517 views

What exactly is the start bit error in UART?

The questions are in the bottom of the post. I understand that there are a lot of sources of timing errors inherited in UART communications. The magnitude of these errors is what limits the ...
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4answers
215 views

How are LEDs timed? (How is the pulse latency measured?)

Please excuse the awkward phrasing of the question; it seems that LEDs have pulse latencies of nanosecond and sub-nanosecond durations. The question is, how was it possible to measure such precise ...
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0answers
62 views

SDRAM timing requirements

I am interfacing a Micron MT48H16M32LFCM-75 SDRAM with an Atmel AT91SAM9G20 and I need to verify on paper (as far as possible), that the timing specifications between those two devices are compatible. ...
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400 views

ASIC timing constraints via SDC: How to correctly specify a multiplexed clock?

Introduction Having found multiple, sometimes conflicting or incomplete information on the internet and in some training classes about how to create timing constraints in SDC format correctly, I'd ...
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1answer
1k views

ASIC timing constraints via SDC: How to correctly specify a ripple-divided clock?

Introduction Having found multiple, sometimes conflicting or incomplete information on the internet and in some training classes about how to create timing constraints in SDC format correctly, I'd ...
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2answers
143 views

Debugging DDR bus issues

We have an SBC board, in the style of the Leopardboard or Beagleboard, that is misbehaving. It's based on the Leopardboard design (TI-DM368 CPU, DDR2 RAM, NAND Flash). Developing software on the ...
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1answer
148 views

DDR2 CAS Latency - is it fixed to clock-cycles or time?

We have a (new, prototype) board that is, at best, temperamental. It's using a Micron MT47H64M16HR-25:H DDR RAM, the design reference board uses a Micron MT47H64M16HR-25E:H. Only one letter different, ...
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1answer
150 views

Synchronous circuit timing diagram

I am little confused on how to fill in this timing diagram for the above circuit. Can someone help me out?
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3answers
100 views

Program w/ 2 loops and timing and such

So let's say i have a prog that has a fast loop @e 64uS, and a slow loop @e 8mS. If the fast loop takes 34uS to execute do I need to make sure the slow loop can execute in 30uS, so as to not be ...
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1answer
146 views

MSP430 instruction timing

I have a MSP430G2231. My ultimate goal is to communicate with a device that wants 1 bit of data each microsecond. I believe this is too fast for timers, meaning I need to handwrite assembly code that ...
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3answers
147 views

Timings constrains for isochronous clocks

In my Verilog design, I have two clocks of the same frequency, but of different phase. At the moment, my timing constraints look like this: ...
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1answer
145 views

Understanding rc time constant

I get that if you put a resistor in series with a capacitor and add DC voltage, the cap will take longer to charge up. How can I calculate, how long it takes for the capacitor to charge up/discharge ...
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2answers
1k views

Synthesis timing summary in Xilinx tool (ISE)

I'm getting the following timing summary from the synthesis: ...
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4answers
2k views

MIDI sequencer timing accuracy using the Arduino

I build these music sequencers. Only it's not exactly a sequencer, it's a physical interface for a sequencer. The sequencer is an application that runs on a laptop that the sequencer connects to, ...
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2answers
209 views

How can I control 8 LEDs with a timing delay with only one microcontroller (PIC12) written in Assembly?

I can have 5 I/O pins enabled. I'm just confused on how to control them individually.
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3answers
228 views

process timing on FPGA

I'm new to fpgas, and there are some timing subtleties that I'm not sure I understand: if all my synchronous processes are triggered on the same edge, then that means my inputs are 'captured' on one ...
2
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2answers
356 views

Receive bytes from UART camera

I am using a dsPIC33E MUC to interface an UART camera(VGA) at 115.2Kbps. The purpose is to save an image to a SD card. The program I wrote works well except that it's inside a loop checking if the ...
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0answers
117 views

Interfacing with ROM chip(C, ASM, & Timing Diagrams)

I am attempting to interface with the following ROM chip via my mc9s12 microcontroller: http://www.alldatasheet.com/datasheet-pdf/pdf/55460/AMD/AM29F040B.html I have several functions written in C, ...
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1answer
295 views

SPI routing question…Maximum length SPI can be routed

Basically my question is regarding maximum length of SPI routing, and route efficiently in my scenario and any timing issues(Setup and Hold). I am just explaining my scenario. Please bear with me, it ...
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0answers
143 views

Are there any metastability issues with microcontroller SPI slave ports that can operate during sleep?

If one is using SPI to interface two microcontrollers that may spend much of their time sleeping, and if the SPI slave port is supposed to wake up its controller when data is received, that would ...
3
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2answers
213 views

Flip flops with multiple clocks

Assume I have 2 flipflops FF1 and FF2 which are driven using multiple clocks. What might be the possible violations that we would come across? I was asked this in an interview for which I answered ...
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1answer
100 views

Do I have to equate clock and Data Bus propagation delay for Transmission Lines?

My question is about SDRAM timings for clock and DataBUS. Som designer advice that clock pin has to be the shortest one. Data Bus may be longer than these because of the some problems. But clock trace ...
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1answer
380 views

Can someone help check my solution for this timing diagram?

I've been working on some timing diagrams and I keep mixing up the behaviors for the different flip flops. EDIT: I think I have the logic correct. If someone could please let me know if I'm ...