This tag is relevant to issues with timing of a protocol or a standard. This could contain UART/ IIC etc. timing as well as timing for driving a motor.

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Verilog “Tick” Generation; Concern over hold time?

In Pong Chu's "FPGA Prototyping by Verilog Examples" he recommends using a periodic enable "tick" to divide the clock while maintaining a synchronous system (to avoid putting the system clock through ...
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1answer
59 views

Help me understand this shift register timing diagram

My basic understanding of using a shift register to convert serial to parallel data is this: On every clock pulse, the state of the serial data pin is read As data is read, it gets shifted in to the ...
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2answers
255 views

How exactly does this shift-register work? - Fairchild 74HC589

I'm using a PISO shift-register, specifically the Fairchild Semiconductor 74HC589. I got the jist of the workings of a generic shift-register via the very useful animated GIF in Wikipedia link above, ...
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3answers
77 views

How to trigger something once a day [duplicate]

What would be the right thing to use if I want the base of a transistor to be high for 12 hours and low for 12 hours? I ask because I would like to make a circuit that regulates temperature in a ...
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1answer
69 views

How to determine I2C Master timing parameters

I am relatively new to I2C, but I have done much reading on the topic and I am confused as to the timing parameters necessary when designing an I2C Master. I know of this chart from the manual on ...
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1answer
302 views

VGA Decoding - Dealing with tolerances

Update: The VGA Simulator is up and running. You can go simulate your own designs or just use the example file to see it working. I also wrote a blog post to help anyone get started using it for ...
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5answers
218 views

What exactly is the start bit error in UART?

The questions are in the bottom of the post. I understand that there are a lot of sources of timing errors inherited in UART communications. The magnitude of these errors is what limits the ...
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4answers
182 views

How are LEDs timed? (How is the pulse latency measured?)

Please excuse the awkward phrasing of the question; it seems that LEDs have pulse latencies of nanosecond and sub-nanosecond durations. The question is, how was it possible to measure such precise ...
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0answers
41 views

SDRAM timing requirements

I am interfacing a Micron MT48H16M32LFCM-75 SDRAM with an Atmel AT91SAM9G20 and I need to verify on paper (as far as possible), that the timing specifications between those two devices are compatible. ...
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0answers
157 views

ASIC timing constraints via SDC: How to correctly specify a multiplexed clock?

Introduction Having found multiple, sometimes conflicting or incomplete information on the internet and in some training classes about how to create timing constraints in SDC format correctly, I'd ...
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1answer
333 views

ASIC timing constraints via SDC: How to correctly specify a ripple-divided clock?

Introduction Having found multiple, sometimes conflicting or incomplete information on the internet and in some training classes about how to create timing constraints in SDC format correctly, I'd ...
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2answers
94 views

Debugging DDR bus issues

We have an SBC board, in the style of the Leopardboard or Beagleboard, that is misbehaving. It's based on the Leopardboard design (TI-DM368 CPU, DDR2 RAM, NAND Flash). Developing software on the ...
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1answer
80 views

DDR2 CAS Latency - is it fixed to clock-cycles or time?

We have a (new, prototype) board that is, at best, temperamental. It's using a Micron MT47H64M16HR-25:H DDR RAM, the design reference board uses a Micron MT47H64M16HR-25E:H. Only one letter different, ...
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1answer
137 views

Synchronous circuit timing diagram

I am little confused on how to fill in this timing diagram for the above circuit. Can someone help me out?
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3answers
97 views

Program w/ 2 loops and timing and such

So let's say i have a prog that has a fast loop @e 64uS, and a slow loop @e 8mS. If the fast loop takes 34uS to execute do I need to make sure the slow loop can execute in 30uS, so as to not be ...
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1answer
101 views

MSP430 instruction timing

I have a MSP430G2231. My ultimate goal is to communicate with a device that wants 1 bit of data each microsecond. I believe this is too fast for timers, meaning I need to handwrite assembly code that ...
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3answers
121 views

Timings constrains for isochronous clocks

In my Verilog design, I have two clocks of the same frequency, but of different phase. At the moment, my timing constraints look like this: ...
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1answer
132 views

Understanding rc time constant

I get that if you put a resistor in series with a capacitor and add DC voltage, the cap will take longer to charge up. How can I calculate, how long it takes for the capacitor to charge up/discharge ...
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2answers
417 views

Synthesis timing summary in Xilinx tool (ISE)

I'm getting the following timing summary from the synthesis: ...
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4answers
1k views

MIDI sequencer timing accuracy using the Arduino

I build these music sequencers. Only it's not exactly a sequencer, it's a physical interface for a sequencer. The sequencer is an application that runs on a laptop that the sequencer connects to, ...
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2answers
173 views

How can I control 8 LEDs with a timing delay with only one microcontroller (PIC12) written in Assembly?

I can have 5 I/O pins enabled. I'm just confused on how to control them individually.
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2answers
151 views

process timing on FPGA

I'm new to fpgas, and there are some timing subtleties that I'm not sure I understand: if all my synchronous processes are triggered on the same edge, then that means my inputs are 'captured' on one ...
2
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2answers
226 views

Receive bytes from UART camera

I am using a dsPIC33E MUC to interface an UART camera(VGA) at 115.2Kbps. The purpose is to save an image to a SD card. The program I wrote works well except that it's inside a loop checking if the ...
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0answers
101 views

Interfacing with ROM chip(C, ASM, & Timing Diagrams)

I am attempting to interface with the following ROM chip via my mc9s12 microcontroller: http://www.alldatasheet.com/datasheet-pdf/pdf/55460/AMD/AM29F040B.html I have several functions written in C, ...
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1answer
239 views

SPI routing question…Maximum length SPI can be routed

Basically my question is regarding maximum length of SPI routing, and route efficiently in my scenario and any timing issues(Setup and Hold). I am just explaining my scenario. Please bear with me, it ...
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0answers
106 views

Are there any metastability issues with microcontroller SPI slave ports that can operate during sleep?

If one is using SPI to interface two microcontrollers that may spend much of their time sleeping, and if the SPI slave port is supposed to wake up its controller when data is received, that would ...
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2answers
179 views

Flip flops with multiple clocks

Assume I have 2 flipflops FF1 and FF2 which are driven using multiple clocks. What might be the possible violations that we would come across? I was asked this in an interview for which I answered ...
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1answer
82 views

Do I have to equate clock and Data Bus propagation delay for Transmission Lines?

My question is about SDRAM timings for clock and DataBUS. Som designer advice that clock pin has to be the shortest one. Data Bus may be longer than these because of the some problems. But clock trace ...
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1answer
304 views

Can someone help check my solution for this timing diagram?

I've been working on some timing diagrams and I keep mixing up the behaviors for the different flip flops. EDIT: I think I have the logic correct. If someone could please let me know if I'm ...
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2answers
308 views

How do I use T-Flip Flops to derive circuits - given the clock signal speed?

I've been trying to do my EE homework for several hours and cannot figure out how to do this stuff.. I've read through the chapter multiple times, searched YouTube and Google, and nothing seems to ...
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3answers
484 views

Circuit that can convert current pulses to voltage

I have an anemometer which outputs current pulses. I can't take it apart but I know there is a phototransistor and LED in parallel shining through holes to it. I was told that with 30m/s wind there ...
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1answer
693 views

hold time violation during FPGA post place and route simulation in modelsim

I am designing a simple encryption circuit on Xilinx Virtex-5 FPGA. I have given the timing constraint in the UCF as below: ...
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1answer
324 views

Rise time for second order RC filter?

Can somebody help me in deriving the expression for rise-time for second order RC filter. simulate this circuit – Schematic created using CircuitLab
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3answers
178 views

I need help Building A Solid state Electro magnetic Mixer

I'm just getting into electronics, and I would like to build an electromagnetic mixer. See here. Most of the tutorials I have found have magnets stuck to a motor spinning under a non magnetic material ...
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2answers
289 views

Is there a glitch / race condition at the output of this circuit?

The input rising and falling edges occur at time t = 0. The propagation delays of the respective gates are 3 and 4 ns, as shown. According to my analysis, the waveforms are as below: As I've ...
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2answers
392 views

what is 555 Timer? [closed]

what is timer 555 ?? can any one give me some links which talk about this topic ? or some references ? or texts ? how can we use this kind of timer ? how to create it ? any information will be ...
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1answer
406 views

Logisim: timing problems setting register

I'm having some problems understanding the timing behaviors I observe in Logisim. I've isolated some cases which illustrate the problem. Say I have a register (1-bit, to keep it simple), which is ...
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2answers
579 views

SPI Clock on PIC unstable

I'm trying to configure the MSSP module of a PIC18F25K22 into SPI master mode. I'm looking at the timing and the clock doesn't remain steady through the whole transmission. A picture shows it better ...
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2answers
157 views

Gate Logic Initial States?

This is probably a silly question but I figured this might be worth another question instead of adding it onto my other one. Referring to this question (About an SR latches first Q state) What is the ...
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3answers
654 views

Why Have Non-Zero Timing on a BLDC?

I've heard you can go faster in one direction if you adjust the timing, but do not understand why? I have a sensored bldc motor with a 30deg shift of the hall-effect sensors, tried going forward (CCW ...
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2answers
145 views

Accurate ADC sampling with in-accurate clock

Im building a datalogger with a LPC11xx as CPU. It needs to wakeup at 256hz to take ADC samples, but this CPU has very in-accurate timed wakeup from deep-sleep, causing jitter on the sampled data. So ...
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1answer
422 views

Implementing the Digilent EPP

I am trying to implement Digilent Parallel Interface from their SDK. You can specifically read up on the interface in this manual. I am using the Basys 2 250k board. I am trying to figure out what I ...
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3answers
158 views

Comparators Dragging Each Other Down

I've assembled a circuit which uses RC timing compared to the voltage across a potentiometer. It is intended to run the motor in this fashion: ...
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1answer
249 views

My design is not meeting timing. What can I do?

I am using the Altera Quartus II software to compile Verilog for a Cyclone IV FPGA. In my case, the FPGA is fixed; I cannot get a faster one. Now one isolated module in my design, which deals with ...
6
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1answer
190 views

Why do standard cells typically have slower timing with high temperature, and faster timing with low temperature?

Threshhold voltage typically falls with increasing temperature, which would seem to indicate that high temperature operating conditions should result in faster gates than low temperature OCs. However, ...
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1answer
205 views

What does “process” mean in PVT?

For timing analysers, FPGA operating conditions are sometimes know as "PVT", which stands for "Process, Voltage and Temperature". While voltage and temperature are self explanatory, what does process ...
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2answers
299 views

How do commercial microprocessors meet timing with a gigahertz clock?

I am having troubles making a relatively simple FPGA design (for an Altera Cyclone IV) meet timing for logic driven by a 250 MHz clock. This makes me wonder how commercial microprocessors (such as the ...
8
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2answers
2k views

What is a false path timing constraint?

In FPGA world, what exactly are false path constraints for an HDL compiler? Why are they useful?
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1answer
559 views

Discrepancy between post-Place-and-Route static timing analysis and ISIM simulation results

Overview I'm implementing a simple Harvard-style CPU using Xilinx ISE version 14.1. I'm using settings compatible with a Digilent Nexys3 board, but for the time being the entire project is performed ...
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2answers
797 views

Arduino vs PIC nop. Is this the same thing?

If I have the following line of code in an Arduino based project: __asm__("nop\n\t"); Will this have exactly the same effect as nop in PIC12F675? Does it matter ...