This tag is relevant to issues with timing of a protocol or a standard. This could contain UART/ IIC etc. timing as well as timing for driving a motor.

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STM32 if-statement timing

I'm working on a porject where I need to communicate with an USB PHY chip. I am using a STM32 microcontoller. (stm32f446ret6, ...
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1answer
23 views

Quartus Waveform File Representation

I have selected the inputs as 8 bit count values that increment over time. The 8 bit value should be parallel in and parallel out. But the bits are spaced over time. Can you please explain why the ...
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1answer
59 views

Using BLE, how fast can I get ~50 bytes of data from the master to a slave? How does that change when increasing the number of slaves present?

In personal project of mine I'm looking to have a system where a number peripherals need to have provided to them, in as real-time as possible, small (~50 bytes max) amounts of information from a ...
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1answer
53 views

How to delay a relay closing?

I have a situation where I'd like to delay the closing of an off the shelf relay by ~5 seconds. Assuming it is a 5V coil, and switching 12 V, I'd like the following: t 0:00: 5v applied to input, ...
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1answer
20 views

tCHSL SPI timing

I was going thru the datasheet of Micron SPI Flash. The timing diagram has tCHSL : S# not active hold time (relative to CLK) What exactly is this? According to the timing diagram, this is measured ...
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35 views

Timing of mask ROM Emulator

I want to emulate a ROM IC (tc534000) in order to load custom samples on a Synthetizer. There is a chip that reads the samples using 19 bit address bus and 8 bit data bus. The first thing that came ...
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0answers
57 views

Why there are AC timing characteristics but not DC in I2C interfaced chip?

I'm quite newbie in electronics, and I'd like to learn why there are AC timing characteristics to this particular EEPROM (24LC512) that I'm using but none for DC? Does AC timing constraints apply to ...
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1answer
58 views

Memory timing values for microprocessor (8086)

There is something vague with the memory timing operation of 8086 microprocessor as I read from many sources. There is a TAVDV which is the time from when a valid address goes on the bus until a valid ...
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1answer
101 views

nrf24l01 frequency switch timing

How much time does the nrf24l01+ take to switch frequency through RF_CH? Can this switching time be parallel to switch between Tx/Rx/Standby modes?
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1answer
63 views

Tradeoffs and design considerations when choosing a crystal + PLL combo for MCU timing

I am in the process of doing more work on ARM platforms (specifically for this example the Atmel SAMD10 Cortex M0+ line). The clock flexibility and lack of ridiculous fuse settings feels like a (very ...
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1answer
76 views

Multiplication Gate Delay

How do you find the gate delay for a basic multiplier circuit that ANDs each bit of the multiplicand with the multiplier then shifts the multiplicand left and the multiplier right until the multiplier ...
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1answer
179 views

PWM (Pulse Width Modulation) vs DAC (Digital Analog Convertor)

I am working on a project where I take over the control of a Nintendo 3DS Touch Screen. The touch screen is a 4 pin system. I have it all wired up and working, however I cannot get the screen to ...
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1answer
58 views

Multioperand pipelined adder

in order to explain how to a pipelined multioperand adder could be implemented my book shows the image reported below. The idea is to use three adder with 4 stage pipeline. However i tried to make a ...
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1answer
54 views

Timing closure suggestions

I've a FPGA design ( I didn't write a single line of sources code) and I've to add a module ( in the design there is a Wishbone bus where it's possible to link others wishbone interface ). The modules ...
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3answers
62 views

How to measure temporary drop in voltage with meter

What's the easiest way to measure the period of time between the "peaks" when a 5V DC signal goes from high to low to high? I'm trying to debug a power-loss problem, and one of the solutions I'm ...
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0answers
66 views

how to calculate the Rise delay of the inverter

how do I calculate the rise delay of the inverter using the "non linear delay model" cell library which has 0.3ns input fall transition time and 0.16pf output load. ? ...
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2answers
247 views

How to analyse timing report for Xilinx FPGA

I'm trying to learn FPGA programming, my test project is a 5 stage pipelined MIPS CPU, which works. Up until now I have been optimising for area utilisation, however this has caused a very slow clock ...
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2answers
71 views

Short “High” Output In Response to a “High” Input

I am new to electrical engineering. I would like to make a circuit that will go to low after a short given time (lets say 0.2s) of being High. Using graphics I would like to convert this: to this: ...
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2answers
593 views

Simple circuit to convert a toggle switch turning on into a short pulse

I need to convert a permanent high signal into a short high pulse. I've got a design problem where I have a toggle switch that connects to a variable +11V to +17V power source, providing a signal to ...
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2answers
253 views

How to multiply base system clock using .xdc constraints in Vivado

This question may be ridiculously rudimentary but I have been going through Xilinx's available guides and videos tearing my hair out... my problem is simply this: I want to use the base 100Mhz clock ...
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2answers
134 views

Timing circuit with op amps and capacitors

I understand how a basic comparator op amp works and how a capacitor charges individually, but I can't seem to put it all together to make this circuit. I think I might be messing up with the voltage ...
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3answers
73 views

How to get equal number of clock cycles before ISR on an AVR

While writing a time critical piece of code for an Attiny13, I figured I could use the rising edge of an input as a trigger to read in some self clocking data. However, the number of clock cycles ...
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1answer
102 views

Propagation delay from a graph

I'm in the edX class and failed on all my three attempts on one of the questions. Clearly my reasoning is wrong, but I can't figure out where exactly. I would really appreciate if somebody could help ...
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1answer
200 views

What's the dwell signals?

Today When I was seeing this page(Digital multimeters (DMM or DVOM) part) I saw this part: What does "automotive timing"? and What's the dwell signals? are these electronic concepts?
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3answers
270 views

How does oscillator frequency stability affect timing? [duplicate]

If, for example, a crystal oscillator is specified as +/- 100ppm what does that mean? That the exact frequency is uncertain to that degree, or that the frequency varies by that degree over normal ...
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1answer
303 views

Setup and Hold time VS temperature (and temperature inversion)

So I know that propagation delay and timing inside an ASIC are affected by temperature. In the old days things went faster when colder and slower when hotter. Now at 90nm and below there is ...
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2answers
818 views

SPI chip select --> data + clock delay tolerance

I know this likely depends on the specific chips and devices being used, but I'm just looking for estimate ballpark numbers. I'm considering using the spi protocol for a project, and I can't seem to ...
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1answer
87 views

How to simply introduce a short (2ns) delay on a line?

We found a race condition in one of our production circuits. A CPLD chip acting as address decoder plus a couple other functions, receives address and data signal over two buses. A peripheral device ...
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3answers
219 views

Reset the raspberry pi with a relay

I'm going to use my Rasp as a GPS tracking and it should be running even if the car is off; however, I don't want run out the car battery. To make it happens I added a battery controller ...
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1answer
3k views

Calculate the UART Baud Rate register for PIC devices

How do I calculate the UART configuration register values for a PIC 24F device, based on a desired Baud rate? Currently the UART module has 2 values that affect the Baud rate, BRG (16-bit register) ...
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1answer
178 views

Timing/buffering issue with Digilent's EPP on Basys2?

I have a Digilent Basys2 FPGA, and I'm implementing the EPP interface described in http://www.digilentinc.com/Data/Products/ADEPT/DpimRef%20programmers%20manual.pdf. This allows a program called ...
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1answer
118 views

FPGA simulates well and passes timing check but fails in PCB

So you have finished your FPGA design. You have simulated it with an extensive test bench created by a different engineer and it works, event at speed after it has been compiled, placed and routed. ...
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1answer
220 views

VHDL delay mechanism

I have difficulty understanding how the delay (mainly inertial delay: AFTER) mechanism works in VHDL. I'll start with this: target <= waveform AFTER 3 NS; As ...
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2answers
133 views

AVR SPI slower than expected

I'm running an ATMega88A at 8MHz and have the SPI configured to run at Fosc/2 = 4MHz. In theory, shifting out 5000 bytes over SPI should take 1/4000000 * 8 * 5000 = 10ms. But according to the ...
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1answer
181 views

AVR SPI2X has no effect

I've got an ATMega88A configured to run on internal 8MHz clock: lfuse = 0xE2 hfuse = 0xDF efuse = 0x01 F_CPU defined as 8000000 This in confirmed in the 'real ...
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2answers
300 views

ATtiny2313 vs ATtiny84 software compatibility

I make and sell a variant of the USBtiny AVR programmer. It uses an ATtiny2313 clocked at 12 MHz and does bit-banged USB using hand-tuned assembly language (that someone else wrote - it's an open ...
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1answer
290 views

driving LEDs via a PI a attiny and TLC5940 (validation) and possible powering issues

at the moment I am planning my first real (big) electronics project. I want to build a LED lamp, that can be controlled by a RaspberryPi (for e.g. programming a binary clock or changing the brightness ...
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2answers
704 views

Setup and hold time

Of the setup and hold timing constraints which are to be met to get a stable output, which one is critical in estimating the maximum clock frequency of a circuit?
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1answer
875 views

DDR4 routing / spacing guidelines

Where can I find the source of routing guidelines for DDR4. I'm talking about things like DQ to DQS timing, maximum length difference in ps for address and command and maybe maximum parallel run ...
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3answers
322 views

32-way Mux Produces Horrible Timing Problems

I'm coding a 32 way mux in verilog. The input is a counter which counts from 0 to 31, incrementing each clock cycle. Each counter value selects a different slice of a vector as an output. In my ...
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1answer
2k views

What actually happens in a RC circuit?

I'm currently working my way through a beginner's electronics book(electronics for dummies) where i am introduced to RC circuits as shown in the schematic below. simulate this circuit – ...
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1answer
348 views

Fixing 1 failing timing constraint in Xilinx

In the end of my project I have a timing constraint failure as follows : clk_in is the 100 Mhz system clock on ML507 I don't know why it is not meeting the ...
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1answer
94 views

Xilinx Design Summary

My project is finished and Xilinx gives lots of statistics in the summary like : How shall I evaluate these values, what can I say about them? What means what? Is this report good or bad? With ...
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0answers
369 views

STM32 FSMC Timing Computation

I'm working on FSMC protocol of STM32 micro controller The formula for calculate FSMC timing is below, but I have a hard time understanding it. From ST Application Note Can someone walk be ...
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1answer
459 views

Question about function set_dont_touch_network

I was trying to debug a script written for synthesis using Synopsys primetime. Can someone explain me what is the function of set_dont_touch_network? I have these ...
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1answer
105 views

Setting up data prior to a rising edge - what's best practice?

I'm a newbie, playing around with a very simple single port block RAM (on an FPGA actually). Its 'read'-timing is standard stuff - i) An address on the RAM input gets latched on a first rising clock ...
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4answers
192 views

Arduino Uno pin response speed

We are attempting to build a coilgun with multiple coils, and each coil needs to be energized and deenergized at precise time intervals. For cost (and inexperience) reasons, we are considering using ...
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1answer
169 views

Timing on a pipeline

I'm basically reviewing for a test in my computer organization class and there's a question about pipelining. The questions is: "If the pipeline consists of 6 stages and each stage executes its ...
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2answers
169 views

Timing Diagram question

Can anyone check my timing diagram for me? I have my exam tomorrow and just want to make sure I am understanding these correctly: Any feedback is appreciated. Thanks in advance
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1answer
191 views

Verilog “Tick” Generation; Concern over hold time?

In Pong Chu's "FPGA Prototyping by Verilog Examples" he recommends using a periodic enable "tick" to divide the clock while maintaining a synchronous system (to avoid putting the system clock through ...