This tag is relevant to issues with timing of a protocol or a standard. This could contain UART/ IIC etc. timing as well as timing for driving a motor.
3
votes
1answer
131 views
SPI routing question…Maximum length SPI can be routed
Basically my question is regarding maximum length of SPI routing, and route efficiently in my scenario and any timing issues(Setup and Hold).
I am just explaining my scenario. Please bear with me, it ...
3
votes
1answer
50 views
MIDI sequencer timing accuracy using the Arduino
I build these music sequencers.
Only it's not exactly a sequencer, it's a physical interface for a sequencer. The sequencer is an application that runs on a laptop that the sequencer connects to, ...
2
votes
2answers
106 views
How can I control 8 LEDs with a timing delay with only one microcontroller (PIC12) written in Assembly?
I can have 5 I/O pins enabled. I'm just confused on how to control them individually.
6
votes
2answers
94 views
process timing on FPGA
I'm new to fpgas, and there are some timing subtleties that I'm not sure I understand: if all my synchronous processes are triggered on the same edge, then that means my inputs are 'captured' on one ...
1
vote
2answers
89 views
Receive bytes from UART camera
I am using a dsPIC33E MUC to interface an UART camera(VGA) at 115.2Kbps. The purpose is to save an image to a SD card.
The program I wrote works well except that it's inside a loop checking if the ...
0
votes
0answers
49 views
Interfacing with ROM chip(C, ASM, & Timing Diagrams)
I am attempting to interface with the following ROM chip via my mc9s12 microcontroller:
http://www.alldatasheet.com/datasheet-pdf/pdf/55460/AMD/AM29F040B.html
I have several functions written in C, ...
0
votes
0answers
49 views
Are there any metastability issues with microcontroller SPI slave ports that can operate during sleep?
If one is using SPI to interface two microcontrollers that may spend much of their time sleeping, and if the SPI slave port is supposed to wake up its controller when data is received, that would ...
19
votes
9answers
5k views
Software to create timing diagrams
In my professional life, I sometimes need to create timing diagrams for UART/SPI/etc protocols. However, I cant find any good programs available. Do any of you recommend any programs for this that ...
0
votes
1answer
157 views
hold time violation during FPGA post place and route simulation in modelsim
I am designing a simple encryption circuit on Xilinx Virtex-5 FPGA. I have given the timing constraint in the UCF as below:
...
3
votes
2answers
133 views
Flip flops with multiple clocks
Assume I have 2 flipflops FF1 and FF2 which are driven using multiple clocks. What might be the possible violations that we would come across? I was asked this in an interview for which I answered ...
0
votes
1answer
63 views
Do I have to equate clock and Data Bus propagation delay for Transmission Lines?
My question is about SDRAM timings for clock and DataBUS. Som designer advice that clock pin has to be the shortest one. Data Bus may be longer than these because of the some problems. But clock trace ...
0
votes
1answer
191 views
Can someone help check my solution for this timing diagram?
I've been working on some timing diagrams and I keep mixing up the behaviors for the different flip flops.
EDIT:
I think I have the logic correct. If someone could please let me know if I'm ...
1
vote
2answers
91 views
How do I use T-Flip Flops to derive circuits - given the clock signal speed?
I've been trying to do my EE homework for several hours and cannot figure out how to do this stuff.. I've read through the chapter multiple times, searched YouTube and Google, and nothing seems to ...
2
votes
3answers
171 views
Circuit that can convert current pulses to voltage
I have an anemometer which outputs current pulses. I can't take it apart but I know there is a phototransistor and LED in parallel shining through holes to it. I was told that with 30m/s wind there ...
1
vote
1answer
119 views
Rise time for second order RC filter?
Can somebody help me in deriving the expression for rise-time for second order RC filter.
simulate this circuit – Schematic created using CircuitLab
1
vote
3answers
95 views
I need help Building A Solid state Electro magnetic Mixer
I'm just getting into electronics, and I would like to build an electromagnetic mixer. See here. Most of the tutorials I have found have magnets stuck to a motor spinning under a non magnetic material ...
2
votes
2answers
4k views
Arduino: better microsecond resolution than micros()?
The micros() documentation notes that the return value will always be a multiple of 4.
Is there any way to get a higher resolution microsecond click, preferably down to the 1 microsecond level?
...
1
vote
2answers
117 views
Is there a glitch / race condition at the output of this circuit?
The input rising and falling edges occur at time t = 0. The propagation delays of the respective gates are 3 and 4 ns, as shown.
According to my analysis, the waveforms are as below:
As I've ...
-3
votes
2answers
299 views
what is 555 Timer? [closed]
what is timer 555 ??
can any one give me some links which talk about this topic ?
or some references ? or texts ?
how can we use this kind of timer ? how to create it ?
any information will be ...
5
votes
2answers
228 views
SPI Clock on PIC unstable
I'm trying to configure the MSSP module of a PIC18F25K22 into SPI master mode. I'm looking at the timing and the clock doesn't remain steady through the whole transmission. A picture shows it better ...
2
votes
1answer
154 views
Logisim: timing problems setting register
I'm having some problems understanding the timing behaviors I observe in Logisim. I've isolated some cases which illustrate the problem.
Say I have a register (1-bit, to keep it simple), which is ...
4
votes
3answers
2k views
What is hold time violation?
I am currently reading about Pulsed Latch Circuit. And there is a frequent mention of "hold time violation". Like:
For latch, "...data must be held for a longer period of time,
increasing the ...
2
votes
2answers
91 views
Gate Logic Initial States?
This is probably a silly question but I figured this might be worth another question instead of adding it onto my other one.
Referring to this question (About an SR latches first Q state)
What is the ...
6
votes
3answers
197 views
Why Have Non-Zero Timing on a BLDC?
I've heard you can go faster in one direction if you adjust the timing, but do not understand why? I have a sensored bldc motor with a 30deg shift of the hall-effect sensors, tried going forward (CCW ...
1
vote
2answers
100 views
Accurate ADC sampling with in-accurate clock
Im building a datalogger with a LPC11xx as CPU. It needs to wakeup at 256hz to take ADC samples, but this CPU has very in-accurate timed wakeup from deep-sleep, causing jitter on the sampled data.
So ...
1
vote
1answer
213 views
Implementing the Digilent EPP
I am trying to implement Digilent Parallel Interface from their SDK. You can specifically read up on the interface in this manual. I am using the Basys 2 250k board.
I am trying to figure out what I ...
0
votes
3answers
115 views
Comparators Dragging Each Other Down
I've assembled a circuit which uses RC timing compared to the voltage across a potentiometer. It is intended to run the motor in this fashion:
...
7
votes
2answers
1k views
Poor eye diagram, where to start looking?
I'm trying to debug a 100Mbit ethernet board and I'm running up against a problem I'm having trouble trying to resolve.
This is the eye diagram for the transmit pair. The receive pair is very ...
2
votes
1answer
168 views
My design is not meeting timing. What can I do?
I am using the Altera Quartus II software to compile Verilog for a Cyclone IV FPGA. In my case, the FPGA is fixed; I cannot get a faster one.
Now one isolated module in my design, which deals with ...
6
votes
1answer
131 views
Why do standard cells typically have slower timing with high temperature, and faster timing with low temperature?
Threshhold voltage typically falls with increasing temperature, which would seem to indicate that high temperature operating conditions should result in faster gates than low temperature OCs. However, ...
8
votes
2answers
257 views
How do commercial microprocessors meet timing with a gigahertz clock?
I am having troubles making a relatively simple FPGA design (for an Altera Cyclone IV) meet timing for logic driven by a 250 MHz clock. This makes me wonder how commercial microprocessors (such as the ...
3
votes
1answer
119 views
What does “process” mean in PVT?
For timing analysers, FPGA operating conditions are sometimes know as "PVT", which stands for "Process, Voltage and Temperature".
While voltage and temperature are self explanatory, what does process ...
8
votes
2answers
561 views
What is a false path timing constraint?
In FPGA world, what exactly are false path constraints for an HDL compiler? Why are they useful?
2
votes
2answers
588 views
Debugging a LPC23XX based CAN bus sniffer
I am trying to get a CAN bus sniffer working, based on LPC2368. I keep getting a bus error interrupt, of type "form error". I suspect my timing settings. I verified that the sending party is ...
4
votes
1answer
299 views
Discrepancy between post-Place-and-Route static timing analysis and ISIM simulation results
Overview
I'm implementing a simple Harvard-style CPU using Xilinx ISE version 14.1. I'm using settings compatible with a Digilent Nexys3 board, but for the time being the entire project is performed ...
2
votes
2answers
559 views
Arduino vs PIC nop. Is this the same thing?
If I have the following line of code in an Arduino based project:
__asm__("nop\n\t");
Will this have exactly the same effect as nop in PIC12F675? Does it matter ...
0
votes
1answer
192 views
PICAXE very short interval timer (for playing sound)
I have a PICAXE (08M2) that I'm using to play sound, using the Roman Black algorithm mentioned in the answer to this question. My question, then, is this: How do I get the PICAXE to wait for the ...
3
votes
3answers
526 views
Help understanding AVR execution timing
I am working with an Atmel ATMEGA32U4 microcontroller - datasheet here with a 16 MHz crystal for system clock.
From my understanding, this chip has a 'Divide clock by 8' fuse programmed from the ...
1
vote
3answers
284 views
How does CPLD propagation delay work?
My question is about CPLDs in general, but take for example this cheap Xilinx one.
I understand that unlike a microcontroller, a CPLD does not have a clock; external edges activate the logic ...
3
votes
1answer
95 views
Phi before datasheet timing value
I have just come across this data sheet that specifies values from a timing diagram as
\$t_1\$ φ 300 ms, \$t_2\$ φ 50 ms, \$t_3\$ φ 25 ms, \$t_4\$ φ 15 ms,
\$t_5\$ = 5 ms (minimum), \$t_6\$ φ ...
1
vote
1answer
76 views
Undefined behaviour in a PSRAM read memory transaction
I am reading the datasheet of a PSRAM (available here). Looking at the timing diagram for burst reads (page 10, figure 8), there is a "undefined behaviour" for a half-cycle on the ...
2
votes
2answers
494 views
Unexpected Verilog warning re FPGA clock assignment
I've got a question about something I don't understand that is going on in my FPGA project. I need to control two devices (AGC and ADC) through an SPI bus. As as the FPGA will be the master device, ...
2
votes
1answer
190 views
RAM writing simulation in VHDL
Writing a value to RAM is a small part of my project, everything is working, but I cannot explain one thing related to RAM/digital timing.
I will write a description in regards to picture I added.
...
-2
votes
3answers
381 views
Implementation of traffic lights
I'd love your help with implementation of traffic lights of 15 second cycle.
The red light is on for 6 seconds, then the yellow (At the same time with the red for two seconds), then the green light ...
3
votes
3answers
283 views
Timing inside a shift register
How I imagine synchronous digital networks work: data lines are sampled at rising clock edge, a set of transients occur, system settles, and data lines are sampled again on next rising edge. I would ...
1
vote
4answers
1k views
Starting motor for 5 seconds after 30 minutes, turning it off and start in reverse direction after 30 minutes
I want to start a 9v DC motor in one direction for 5 seconds after 30 minutes delay, then turn it off and then after 30 minutes, restart it for 5 seconds in reverse direction and then stop it. The ...
0
votes
2answers
360 views
Circuit to shut off power after a short time of turning on
I've got a 3V button battery driving an led and a trembler switch functioning now. However, the sensitivity of the switch is giving me trouble because I need it to remain open when at rest in a ...
6
votes
4answers
235 views
How to find the earliest edge
______
A _____| |________
______
B ______| |_______
Which edge arrives first?
I have two digital pulses that arrive at almost the ...
3
votes
3answers
715 views
Using Logic-Analyzer to reverse-engineer ISM-band ASK/OOK encoding, possible?
Is it possible to use a Logic Analyzer (such as this one), to determine the waveform s.t. on the DATA out pin of an ISM-band ASK/OOK (315/433.92MHz) RF module, in turn to decode it's encoding scheme. ...
3
votes
3answers
231 views
Choosing a DSO, advice sought
As a tinkerer, hobbyist, wannabe-'maker' (as in the protagonists in the Make magazine), sometimes I feel the lack of better tools in some projects, although for most, I can make-do with my DMM for ...
