Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips.

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assign values to all columns in 2D array in one statement

I would like to assign value to an array - mem. it has 16 rows and 16 col. each element is 2 bit wide. i would like to initialize each row of an array like this. if i am initializing 4th row of the ...
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VERILOG CODING FOR CHARACTER TO DECIMAL CONVERSION REGARDING [on hold]

Can anyone post the verilog coding to convert the LCD CHARACTER to decimal numbers? Because I want to display the decimal value in LCD SPARTAN-3AN to 16*2 (1602zfa) LCD device.
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24 views

Verilog “Tick” Generation; Concern over hold time?

In Pong Chu's "FPGA Prototyping by Verilog Examples" he recommends using a periodic enable "tick" to divide the clock while maintaining a synchronous system (to avoid putting the system clock through ...
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1answer
56 views

Resampling with MSB operation

I'm new to verilog and HDL, so please be patient with me. In a code, I have an input variable clk, two input 16 bit samples, that are stored into ...
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Synthesis of Verilog code in Cadence

I am trying to synthesize my Verilog code, which I wrote using Modelsim tool for 8-bit MAC in Cadence Encounter. The file that is generated after synthesis has to be re-checked for functionality in ...
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57 views

Spartan 3AN FPGA DCM

While I use the internal clock for DCM clkin input I am getting clk0 as perfect frequency of output same as internal clock but not in remaining o/p pins. I changed from previous coding like this and ...
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93 views

Help needed with SPARTAN-3AN FPGA frequency doubler

Here I attached the routed nets for this below verilog HDL program with DCM instantiate module. while I am implementing in XC3S50AN FPGA board using using ISE12.3 Design suite clk2x & locked ...
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57 views

How to Implement this special selector?

Is it possible to write a module with 3 wires a,b,c that would output either : z (disconnected) if a=b=c=z a if a=(0 or 1) and b=c=z b if b=(0 or 1) and a=c=z c if c=(0 or 1) and a=b=z x (dont care) ...
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74 views

Synchronizing multiplier with adder to form mac

I have designed an 8-bit multiplier in Verilog which takes a maximum of 8 clock cycles to give the product. I have also coded a 16 bit adder based on combinational logic. I now want to integrate the ...
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47 views

How do I minimize the size of a 3-input parallel adder?

Currently this alu uses 24 logic elements, most likely from the adders. I'm wondering if there is any tool in Altera/Quartus I can use to minimize this? For my design, multiplier and RAM modules are ...
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75 views

How to efficiently implement a single output pulse from a long input on Altera?

I have a fast clock and a switch called 'ready'. When the switch is flipped (ready goes HIGH), I would like the output pcEn to produce a pulse that lasts only for one clock cycle. pcEn will only ...
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1answer
109 views

How do I make use of multipliers to generate a simple adder?

I'm trying to synthesize an Altera circuit using as few logic elements as possible. Also, embedded multipliers do not count against logic elements, so I should be using them. So far the circuit looks ...
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1answer
46 views

Target <tr26> of concurrent assignment or output port connection should be a net type

I am trying to implement Fast Fourier Transform in Verilog for 32-point sample and have written the following butterfly module: ...
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2answers
128 views

generate random numbers using LFSR

I have to generate 2 5-bit random numbers and add them using structural verilog and implement it on FPGA. I have to design LFSR with 5 D flip flops and the 5-bit pseudo random number is given by the ...
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1answer
63 views

Bit compression in Verilog

I am trying to write a Verilog code for a multiplier based on the abacus principle. I want to compress an array of 8X15 bits to the lowest rows. For e.g. for an array of ...
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1answer
45 views

Verilog Iterative Circuit

I found this description in a book for a magnitude comparator, and I don't understand the explanation or why it works. I have commented everything I did understand, but that one line there just kills ...
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1answer
48 views

Understanding square braces in verilog

I don't understand what the square braces mean in the following Verilog code. Can someone please explain their purpose? ...
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2answers
48 views

Difference between setting up clocks on Verilog

These two statements are used quite often, to set up clocks in test benches: initial begin clock = 1'b0; forever #5 clock = ~clock; end ...
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55 views

Relation between delta cycle and event scheduling in verilog simulation?

I understand that in Verilog/SystemVerilog standards there are different regions for event scheduling, thus mimicking the behavior of concurrent hardware. But how does this relate to the delta cycles ...
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133 views

What's the first step to learn Verilog coding to sort values?

I do not know how to start working on this problem. Should I first design the digital circuit of sorting? I am poor on both topic. Suppose I have four numbers R0, R1, R2, R3... What is the digital ...
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76 views

problem with CPLD and 24C16 EEPROM interface

Can any one say if it is possible to implement this code in ATMEL 24C16 EEPROM device for write the data. While I am implementing this with CPLD xc9572 I/O Pin declared as sda, scl there won't have ...
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2answers
100 views

Please explain the following Verilog code of a D flip flop?

I am learning the Verilog language. Can someone explain the questions I ask in square brackets [] : ...
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1answer
45 views

Empty Netlist Vivado Design Suite

I am dealing with synthesis of verilog sources using Vivado Design Suite 2013.3 tool for the first time. The behavior of my design is correct as verified by the pre-synthesis simulation. My problem ...
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52 views

nonblocking statements and fork-join in verilog and/or system verilog

Can anyone please tell me the difference between non-blocking begin-end in a procedural block and fork-join. One of my friends told me that the latter in non-synthesizable and are used only in ...
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1answer
106 views

Unexpected patterns in Verilog $random

I have a Verilog test bench that monitors a 64-bit bus and should randomly schedule a flipped bit (packet corruption) to happen every 1-in-X packets. I was surprised to find it not injecting any ...
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1answer
111 views

Online FPGA/HDL synthesizer

I recall seeing a web-based HDL synthesizer a couple years ago, but I can't find it anymore. I believe it was just a frontend that ran the vendors' synthesis tools on the server. Does this sound ...
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164 views

Connected to Multiple Drivers Problem Verilog

After I synthesize it, the error occured like this: ...
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1answer
63 views

what circuit the following verilog code produce

I was learning Verilog. I was posed by the following code and asked what the following code realize i.e., the circuit implemented. ...
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70 views

What does the following Verilog code realize

I was learning verilog hardware description language. I was confused a bit with the blocking and non-blocking statements. Can someone tell me what the following verilog codes realize and simple hints ...
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2answers
324 views

Implementing parallel CRC in verilog

I am trying to implement a parallel CRC in Verilog but having trouble getting it to work. This is a snippet of the code that I'm having trouble with. ...
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1answer
64 views

High Level Language to HDL [closed]

I need to convert a simple program (C or Java) to HDL (especially Verilog). However, I have no idea about this conversion. Another problem is that the resulting code must be gate level. Now, This ...
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1answer
61 views

Constraining the reset line

I am using Quartus II to compile my Verilog design, and I'm working to properly constrain my signals. I know how to constrain clocks, for example: ...
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3answers
217 views

Setting FPGA pins as virtual

I have a Verilog module for which I want to check its timing in isolation to the rest of the system. The problem is that the FPGA has a limited number of physical pins, and my module has more inputs ...
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1answer
89 views

Difference between blocking and nonblocking assignment Verilog

I was reading this page http://www.asic-world.com/verilog/verilog_one_day3.html when I came across the following: We normally have to reset flip-flops, thus every time the clock makes the ...
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189 views

Confusion over clocks in FPGAs / Verilog

I just purchased an FPGA and I am learning Verilog but I have run into a few confusions, most of them regarding the clock. My first question is, how does sequential logic work? Are the assignments ...
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1answer
56 views

Verilog syntax question

Something like this: a=b?c:d ; would make a=c, if b=1, else a would be made equal to d; But what would doing the same thing on an array do? Like this: assign a = (|b[10:8])?8'hff : b[7:0]; // to ...
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3answers
94 views

Veriog:How to pass a register to a module?

Assume we have a module with 32 bits output like this: module ModuleLow(foo,...); output [31:0] foo; Now we want to use it in another module ( a very simple ...
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3answers
95 views

How is the assignment squence in Verilog?

I want to know if we assign something to a register ( or do anything else ) in a specific clock cycle, this assignment is performed in the current clock cycle or the next cycle? (Setting: Xilinx , ...
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1answer
83 views

How to use “Arbitrary” Vref in FPGA?

Assume we have a simple Verilog module with 1 input (in1) and one output (out). Please look at the truth table at the end of this question. I want to send a signal with the voltage between ...
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2answers
130 views

Rounding Methods in IEEE

I am trying to learn the features of IEEE rounding from the following source On fast IEEE Rounding Can anyone one explain the equation for round up ? What does round up with fix up mean ? And what ...
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1answer
70 views

Arithmetic shifting in verilog

I am going through the book Verilog HDL by Samir Palnitkar. I see that there are two types of shifting, the normal and the arithmetic. But I was not able to understand the difference between them. ...
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1answer
180 views

Flip flop with load/set, reset, clk, and input

I'm not looking for a hardware language description of the flip flop, but the logic gate level to implement. In verilog, the equivalent I'm looking for is ...
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384 views

How to assign a pull-up/down resistor in Verilog for inputs?

As a newbie in FPGA world, I realized that it is possible to set pull-up/down resistors in Verilog but I don't know how. I have written my code that works just fine but when I connect my XC3S400 to ...
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3answers
94 views

Using a Mux to switch between reading and driving a wire

I have been doing some googling and cannot seem to come up with an answer for this. The way I understand a mux is that it is basically a 2 way switch. I understand it is mostly used to select inputs ...
3
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1answer
152 views

what is BUFGP used for?

I'm trying to do some verilog code for my class and I came around BUFGP. After doing some research I only found that it is a buffer for driving clocks. Can anybody explain this to me. For example I ...
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2answers
234 views

Why my FPGA programs does not work?

I am very new to FPGA and sorry for this elementary question. I just made a very simple XOR code like this with Webpack ISE to download to XC2S100 ( just for test!) but it does not work. EDITION1: ...
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58 views

verilog file with own library import into cadence

I need to import a verilog net list file into cadence. I'm writing the verilog file with my own developed application. I defined several library elements inside the net list file which are not part of ...
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1answer
783 views

Control 4 digit 7-segment (2 digits number each) using Verilog [closed]

How to program using verilog, where i want to control 4 digit 7-segment display, that will show 2 digits number for first and second 7-segment display, and the others with 2 digits number too. I know ...
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174 views

pipeline and verilog

I am having a pipelined scheme and I want to have a register at the output for my result. So, I am using this code: ...