Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips.

learn more… | top users | synonyms

0
votes
0answers
65 views

Executing an long equation in one clock cycle

I am using DE2-115 Board for doing traversal in a forest data structure in 50 MHz frequency. Multiple trees have been stored in on-chip ROM, now I need to set the address which can point to a certain ...
1
vote
2answers
68 views

register with enable signal, problem of understanding simulation results

I simulated a 32-bit register with an enable input in Vivado. The following things are unclear to me: I don't understand why 0xFFFFFFFF is latched at 5 ns and not the previous value 0x0abcdeff. ...
0
votes
1answer
19 views

Verilog 'cannot match operand(s)' & 'multiple constant drivers'

I'm working on a Verilog project using a FPGA (BEMICROMAX10) and some breadboard components. The project is to make a digital clock in which you can also set the time using the buttons on the FPGA. I ...
-1
votes
0answers
23 views

How to test digital HPF in verilog [on hold]

I have an HPF generated from MATLAB Into a verilog code. I would like to test it by simulation. How can i do it?
0
votes
1answer
32 views

How to Insert values in 2d array in verilog

I wrote a verilog code for Circular Shift register using a 2-d array, but can't seem to insert values in the array. Here is my code ...
-5
votes
0answers
30 views
-3
votes
0answers
32 views

High pass filter in verilog [closed]

I need to implement a high pass filter for FPGA. Lets say pass 10Khz. Clock sample 40mhz How can i implement this?
0
votes
1answer
34 views

operand isolation in RTL

I'm trying to build some low power circuits at the RTL level. How would I go about coding operand isolation so that the synthesis tool (ASIC/FPGA) recognizes it. Assuming the spec requires the output ...
-2
votes
0answers
23 views

Quartus 2 double increase frequency

How can I create a up/down counter using quartus 2, that allows frequency to increase each time when you press and hold a button for 5s on the board
0
votes
2answers
109 views

Need help with sorting a 32 bit string

I have to program a combinational circuit which sorts a 32 bit array like this: 10011011010101101010101010110010 ==> 00000000000000011111111111111111 The input must be parallel and 32 bit. The output ...
0
votes
1answer
45 views

verilog: binary code decimal and gray code counter implementation

I am trying to implement a 8-bit counter that does both BCD(Binary Code decimal) and gray code sequence. If the input control = 0, the circuit will count in BCD and if the input control = 1, the ...
-1
votes
1answer
69 views

How to establish a communication between FPGA and CPU, in real-time? [closed]

I am working on a project that involves FPGA and CPU communication(in real-time - i.e, CPU and FPGA should function together). I have already designed and tested the UART communication protocol on ...
0
votes
1answer
22 views

Verilog Shift Register with Two Inputs

I am attempting to create a 32-bit shift register in Verilog with two inputs, DATA0 and DATA1. DATA0 is driven low to input a 0 to the register and DATA1 is driven low to input a 1 to the register. ...
0
votes
0answers
41 views

Verilog 8 bit adder & testbench - not working

Resolved - After making it compileable in Quartus by naming the for loop in my8bitadder and doing Greg's fixes, the code works fine now. Thanks guys! I've made an 8 bit adder but I can't seem to get ...
0
votes
0answers
23 views

Nexys4DDR temperature sensor reading code error

I am trying to read the temperature sensor on my Nexys4DDR board using i2c protocol. My code is outputting all of the leds as 1, thus giving me the default value. Where am I going wrong? ...
-1
votes
1answer
54 views

How to use a module in verilog as in build operator like OR, AND, XOR etc. function?

I wanted to module GR as the operator. how can I? ...
1
vote
3answers
239 views

Why would you want to write to a file when writing VHDL? [closed]

I have never so far been in the need to write to a file when making a testbench in vhdl. Seeing the signals being plotted has always been enough so far. Could someone please give me a case or the ...
0
votes
0answers
36 views

CFI flash interface in verilog

I am working on an Intel’s CFI - Flash (28F640J3) interface in verilog. I have written a code and tested it for many commands; read, write, erase. But I am facing problem with 'Write Buffer’ and read ...
0
votes
0answers
16 views

Hardware Co-Simulation using ml605 with ISIM simulator …?

I am trying to do RTL(verilog HDL) and Firmware(System C) Co-Simulation with ISIM Simulator using VIRTEX-6 ML605 FPGA board. I am unable to run co-simulation. I have reffered the document " Hardware ...
-2
votes
1answer
35 views

Showing negative numbers in Verilog

I am writing a program for a 16-bit ripple carry adder and stumbling a little at the end. When I run my code (which includes negative numbers), it's doing the math right, but giving me all positive ...
1
vote
2answers
74 views

Correctly initialize a shift register (Verilog)

I've been struggling with a very simple Verilog program. It's a 4 bit shift register that gets rotated at every clock cycle and drives four LEDs. (As you can tell I'm new to FPAGs and HDLs.) The ...
0
votes
1answer
47 views

How can assign a synthesizable string to a byte array in SystemVerilog?

I want to initialize a byte array (or any other possible type) to a long string. For example define: string str = "abcdefg". I read these two links (1 & 2) but ...
0
votes
1answer
47 views

For loop in `define Macro

I searched on SO, and on web, no where found the ans. I have following code, where It success fully parsed `define and generate expected results, but if number of times calling of macro is large then, ...
-1
votes
1answer
62 views

How to create .VCD file or Simulation activity file of verilog code?

I have Verilog's code. It is simulated correctly and synthesize too. I wanted to write.VCD(value change dumped) file. I got from internet few command to generate VCD file as given below: ...
-1
votes
2answers
62 views

verilog state machine - state won't update

So I'm trying to simulate a state machine with outputs s and v and a state. for some reason our s and v values are updating but the state refuses to change, any help would be awesome ...
2
votes
2answers
94 views

Is it right to initialize a reg in verilog and apply condition with initial value of reg in Verilog?

I have the little doubt related to initializing condition in Verilog. Like in given statement: ...
-3
votes
1answer
49 views

How to find minimum among variables with excluding variables having zero values in Verilog?

I have 6 variables names D1,D2,D3,D4,D5,D6. I wanted to find minimum among them but excluding the zeros if any present. I did same in MATLAB by using below command: ...
3
votes
1answer
72 views

Dividing a clock in Verilog - is it OK?

Dividing a clock down in Verilog is a basic exercise, and there are loads of answers online about how to do it. What I want to know is whether it is OK to use a clock that has been divided down using ...
1
vote
2answers
83 views

Synchronuous Combination Lock

I'm trying to implement a synchronous combination lock that will unlock once it receives "101011" using verilog. It has one input: x, and three outputs: unlock, ready, and error. Following these ...
0
votes
1answer
71 views

Non-Wraping Up-Down Counter

I'm trying to implement a synchronous up-down counter in verilog with the following rules: Counter only changes on rising edge of clock When reset=1, count goes to 00, normal operation when reset=0 ...
0
votes
1answer
28 views

Change array to individual outputs

I'm trying to design a synchronous sequential circuit to implement a tail light controller for a 1965 Ford Thunderbird using verilog as shown below (included with the state diagram). I have the ...
0
votes
3answers
75 views

Assigning x in verilog

Assume there exists a 1 bit data output port and a 1 bit dataValid output port for a module. Is it OK to assign 1'dx to the data output when dataValid is assigned 0? Will this create synthesis issues? ...
1
vote
1answer
30 views

User defined data type in Verilog

I have always used VHDL and now need to use Verilog, so I'm learning Verilog. . . How can I define and use user-defined data type in Verilog for state machines. for eg : In VHDL I would write ...
1
vote
1answer
148 views

Displaying Characters In Verilog With VGA

I'm taking a intro to ECE course as a CS student and for a final project we are to design a game coded in Verilog using the VGA display on a DE1-SoC board. I decided to create a hangman game but I ...
0
votes
1answer
40 views

Generating Channel Select for Multichannel ADC

I am using a FPGA to control a 4-channel ADC (ADC084S101) to sample four different analog voltages. In order to tell the ADC which channel to sample next, there is a control register that can be ...
1
vote
1answer
61 views

Asynchronous Down Counter using D Flip Flops

After fixing my Up Counter, I'm having troubles writing structural verilog code for an Asynchronous 4-bit Down Counter using D Flip Flops. Here's the D Flip Flop code (which was tested and works): ...
1
vote
2answers
47 views

Is there some flag / pragma which can help me in detecting bogus variable names in a module definition?

[icarus verilog] Is there some flag / pragma which can help me in detecting bogus variable names in a module definition? Consider the following code fragment ... ...
-1
votes
2answers
71 views

Increment operation in 24 bit counter

This is a 24 bit counter verilog program. What is the function of highlighted operation? Do we add 1 to the least significant bit? How can we know that the addition was done to the least significant ...
3
votes
1answer
70 views

HCI UART ? what's the difference with simple UART?

For now, I'm sending bytes from FPGA (verilog) to serial at 115200 bps. I would like to send at higher speed and connect to a bluetooth module (RN42). UART (SPP or HCI) and USB (HCI only) data ...
0
votes
0answers
21 views

Event Debug Mode error when performing mixed Verilog/VHDL simulation in VCS

I am getting the following error: ...
1
vote
1answer
85 views

AND Gate and posedge CLK ? simple question

I'm trying to do the seq system as the picture, I'm sure it's simple but I don't remember the "gate" of this. This clock cond will be used for sending bit in ...
2
votes
0answers
98 views

Two different ways of writing the same thing but generating different behaviours in Verilog

I have a part of Verilog code that is basically trying to synthesize a flip-flop. I have been experimenting and it seems that I can come up with two ways of writing it. The first way being : ...
1
vote
1answer
27 views

Verilog outputting specific bit from register to output; getting constant 1's

I am trying to create an program that bit bangs a value from an FPGA to an arduino. In the module I created, every other clock cycle, the FPGAdata output should be set to the next bit of t. The ...
0
votes
1answer
46 views

Task doesn't work in verilog

I created a module that first sorts a byte array then choose last element as minimum.(just for practice). When I moved sort to the task block, it doesn't worked as well as before. How can use task ...
3
votes
6answers
179 views

Blocking vs Non Blocking Assignments

I have been having a really hard time understanding the difference between blocking and non-blocking assignments in Verilog. I mean, I understand the conceptual difference between the two, but I am ...
0
votes
1answer
61 views

D flip flop in verilog

When i tried to code the below flip flop, the program failed. I'm using altera . ...
0
votes
1answer
31 views
6
votes
1answer
66 views

What is the difference between an array and a bus in Verilog?

I have been learning Verilog and Vivado at school, and I am now very confused by the usage of busses and arrays. Can anyone clarify the following? What is the difference between an array and a bus? ...
0
votes
2answers
80 views

Synthesizeable D Flip flop for FPGA

Having played around with Verilog for some time now, I decided to graduate to implementing designs on Alltera CycloneIV FPGA using the Quartus suite. Starting with a simple D flip flop, I face the ...