Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips.

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What would make me choose Verilog or VHDL over schematic design on CPLDs or FPGAs?

I have absolutely no background in programmable logic, I use mostly microcontrollers in my projects but recently I needed to work with video and the microcontroller is just too slow for what I needed ...
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2answers
60 views

I need help with verilog code, I am in trouble?

I am basically setting different control signals for the ALU to perform operations in verilog. But I have tried all possible ways of writing what I want but in vain, can you help me out. How should I ...
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1answer
31 views

How should this code look like in verilog?

I am designing an ALU to add at state 000, I have to assign control signals for a mux, carry in, and operands so that it works. so, i wrote an if statement in the controller module, and the TA told me ...
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2answers
27 views

How to give clock on xilinx spartan 6?

I am trying to run a counter on Digilent Atlys Spartan 6 xc6slx45 development kit, which changes counts on clock edge. I am new user to Verilog, so I don't know how to give clock to my program from ...
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39 views

What CPUs use a skewed associative cache?

What CPUs use a skewed associative cache? I see several people imply that, with roughly the same hardware, a skewed-associative cache often has better performance than a traditional set-associative ...
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1answer
61 views

Solid color display on VGA not working

I'm trying to get VGA working on my Altera DE0 board using Verilog, but haven't had much luck. It has the same pins as a normal VGA interface except red, green, and blue are all 4 bits each. Here is ...
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30 views

NOC ROUTER with Verilog Code [closed]

enter link description here enter link description here i want to design NOC Router with Verilog Programming..!!!
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3answers
66 views

using C libraries inside verilog

I'm implementing a radio in Verilog. the time taken for bit reversal while computing the FFT is more. it is almost equal to a symbol time (OFDM system). Can I use a FFT library in C, which can be ...
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1answer
36 views

Blocking/Nonblocking with Delay

I am now confused by one piece of Verilog Codee, its kind of testing the blocking or non-blocking assignment features that combination with Delay model. ...
2
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2answers
99 views

Efficient use of space in FPGA

Background and clarifications: I've never developed/written a single piece of hardware before, but I'm currently using Verilog to develop a huge project for a FPGA as my final graduation project. ...
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2answers
94 views

Difference between >> and >>> in verilog?

What is the difference between >> and >>> in verilog/system verilog? I know that ...
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16 views

Difference between >> and >>> [duplicate]

What's the difference between >> and >>> in Verilog/SystemVerilog? I know that ...
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1answer
44 views

Verilog: sampling data in both posedge and negedge of the clock

I have a serial input stream which has left data in posedge of the clock, and right data in negedge of the clock. I would like to synchronize and bring them to the posedge of the same clock. I could ...
3
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3answers
736 views

What's the motivation in using Verilog or VHDL over C?

I come from a programming background and not messed around too much with hardware or firmware (at most a bit electronics and Arduino). What is the motivation in using hardware description languages ...
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1answer
35 views

Destination address of 82C37A DMA Controller

How do I select the destination address for the 82C37A DMA controller? I have gone through all the material on the web and they say that the Base Address and Current Address register contains the ...
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3answers
48 views

How is procedural code converted into a circuit?

With non-procedural code, the digital circuit the code represents is relatively obvious. However with procedural code, it's hard/impossible to see how it translates into a circuit. The only method I ...
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1answer
69 views

D flip flop simulation: which simulation output is right?

I have always wondered, what is the right solution to the D flip flop when the input changes right at the rising edge of the clock? I have found two solutions of these online but have no clue which is ...
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3answers
153 views

Verilog always block w/o posedge or negedge

I have a basic Verilog block that I wrote to trigger on any change in the signal. always @ (trigger) begin data_out <= data_in; end I expected this to ...
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0answers
20 views

Disable display in Synopsys VCS

I am currently simulating this large piece of verilog that is full of $display commands for debugging. I believe this is making simulation slower so I want to get rid of most of those. Is there a way ...
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0answers
71 views

Vivado optimizing away my pins

I'm fighting Vivado over what seems like a fairly stupid issue to me. I wrote some Verilog code in ISE (and simulated it). I generated a bitstream in ISE and downloaded it onto the board via impact, ...
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53 views
0
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1answer
80 views

What is wrong with following Verilog code where I am trying to pass a one-dimensional array?

What is wrong with following Verilog code where I am trying to pass a one-dimensional array? ...
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1answer
95 views

FPGA outputs are always high with basic and/or program

So I am just getting started developing with an Altera Cyclone II EP265 mini board, and I am having some trouble getting a program that outputs the "and" and "or" of three inputs working. The full ...
2
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1answer
43 views

Verilog: How to keep process reacting only to clk and reset?

I have some Verilog code that simulates correctly. I decided to synthesize it, and I see these warnings that make me uneasy: ...
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0answers
94 views

How to use for loop inside a case in Verilog

Whether I can use for loop inside a case statement in Verilog? I am writing code for 8-bit memory using Verilog in which I have to execute 3 conditions. They are: Writing and reading data from 0th ...
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1answer
38 views

Verilog assigning wire by iterating over array

How to assign a wire with a AND operation of a wire array? ...
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3answers
138 views

Procedural blocks in verilog

We have two types of procedural blocks in verilog: initial and always block. The statements inside these blocks are executed ...
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3answers
119 views

Can a barrel shifter be done combinatorially?

I was told that 66b/64b encoding in 10Gb Ethernet (10GBASE-R) requires a one-cycle barrel stage, which adds a necessary one cycle to the theoretical terminal latency. The Wikipedia page on barrel ...
2
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1answer
50 views

Difference between HVL and HDL

Hardware description language describes our circuit but what does Hardware Verification Language do? How does it verify the design?
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62 views

Altera Quartus II: FPGA .sof file corrupt all the time

Problem Background: I have a synthesized design using Quartus II 14.0 Output file its in .sof format, to program an Altera Cyclone It works correctly on my computer I can load the file to the FPGA ...
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1answer
64 views

Single Die Roll Counter Wrap Around Nested Ternary Conditional

I have to emulate a single die roll, therefore it needs to wrap back to one at 6. `D1 and `D6 correspond to my 3-bit state ...
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0answers
38 views

Verilog Concatenation Setting LED'sin casex

If I have a casex statement and I have something such as {`idle, `left}: {next, LED} = {`state1 ,`turn1liteON }; and LED corresponds to LEDR[7:0] and ...
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0answers
77 views

How to correct verilog code of given circuit?

I wrote a code : ...
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1answer
52 views

fpga verilog dual access

I need to write to a register from 2 sources.. in this case, a pci host and a microcontroller. The 2 will never access the register at the same time (basically once the PCI is done , it hands it ...
0
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1answer
48 views

Is the simulated clock cycle latency through an entity accurate?

If I write an entity that takes 10 clock cycles to produce output from input, is it safe to assume that this is the case when implemented in hw, or are there other factors to consider? Does the ...
0
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2answers
71 views

Verilog: is connection without wires possible?

I am sorry to ask this question, which I believe is very basic, but I cannot find an answer. The following example clearly works. But I would like to omit the declaration of the wires ay and by. ...
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1answer
44 views

Quartus II: Suppress warnings by Verilog module

In my FPGA project I use the Quartus II PCIe megafunction. The number of warning messages this Altera library module produces baffles me. Is there a way to have Quartus II suppress all the warnings ...
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88 views

Understanding Combinational Feedback Loops

1) Please give me a simple example of a verilog code that results in combo feedback loop. 2) Why are these feedback loops undesired in your design? ...
7
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3answers
567 views

Why delays cannot be synthesized in Verilog?

I have always read that delays declared in RTL code can never be synthesized. They are meant only for simulation purpose and modern synthesis tools will just ignore delays declarations in the code. ...
0
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1answer
77 views

Send signal from one output connected to multiple modules

Hi I am learning verilog and I am trying to find an answer if I have an output of type reg in a main module connected to the inputs of multiple modules, how in verilog would I specify which module I ...
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0answers
86 views

Routing errors when trying to implement PLL onto Spartan-6 FPGA board

I am attempting to synthesize and implement the reference design that is linked to in the 'Reference Design Additional Information' section of the following document. I get the following error ...
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0answers
26 views

Synthing HDL down to waveform-testable format using Synopsys

I've worked a bit with the Quartus II toolset to create small systems that I could construct in Verilog and then test by applying a waveform. Then I could check the output against a Golden Waveform to ...
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1answer
121 views

How to simulate PCIe to debug my FPGA endpoint

I'm working on an FPGA controller connected through PCIe. The only way I can debug the hardware is using chipscope. So I execute commands through my driver and check out the signals from the FPGA. ...
0
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1answer
40 views

contribution statements in verilog-A

How does assignment through a contribution statement (statements with <+ operator) works in verilog-a? I read in the language reference manual of verilog-a the following about the branch ...
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1answer
80 views

How to convert output of 4digit BCD adder to hexadecimal

The output of 4digit BCD adder is "Cout" and "S[15:0]". {Cout,S} is the output of BCD adder. How can i convert this into Hexadecimal.I have tried the following method but its not working ...
0
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1answer
66 views

Verilog to spice using v2s- specificing the port order in the command v2s

I was trying to convert from verilog netlist into a spice netlist using the option v2s. Can I specify the pattern in which the ports will be arranged in my ...
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1answer
207 views

How to design a two-stage synchronizer with a clock divider in Verilog?

I have a very fast clock called CLOCK_50 which I would like to slow down through the use of a clock divider. The output is ...
3
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3answers
132 views

32-way Mux Produces Horrible Timing Problems

I'm coding a 32 way mux in verilog. The input is a counter which counts from 0 to 31, incrementing each clock cycle. Each counter value selects a different slice of a vector as an output. In my ...
0
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1answer
47 views