Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips.

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Need help converting 8 bit input into 3, 4 bit outputs

I have a midterm coming up on digital system design. My professor developed an ASM chart for a problem and I decided that I would try to fill out the code for practice. The simulation runs, it just ...
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1answer
36 views

Designing of a 2:1 multiplexer for 64 bit input and output [closed]

How to design a 2:1 mux for a 64 bit input and output using Verilog code?
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45 views

Using GPIO in Altera

I'm trying to test the GPIO functionality of Altera (DE1, Cyclone II) with this simple program. If the GPIO_0[0] gets a high (1) signal, LEDG[0] will light up. If it receives a low (0) signal, ...
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1answer
198 views

Do If else have priority in verilog?

I have some query about the priority of if else in verilog. For example. If (a) b else if c d else if e f else g At here, those a,b,c...g are ...
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24 views

UART of ZYBO 7000 by using verilog [closed]

I need to send Fibonacci sequence through UART port, I use verilog and ZYBO 7000. Any one knows how to send it ?
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43 views

How to simulate and initialise Block Memory ROM created using Xilinix CORE generator?

I created the ROM correctly using the CORE generator and the correct .coe file. There is supposed to be instruction words inside the memory (32*256). But the data bus out of the memory is always set ...
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1answer
45 views

What are LUT (look up table)? [duplicate]

I am learner in verilog with less knowledge and trying to develop more understanding.I wrote a simple verilog code and synthesize and implement it. I do not have understanding of Look up tables. When ...
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2answers
61 views

Verilog Assignment

I'm designing a Fahrenheit to Celsius converter using algorithmic state machines. I'm trying to get the following code to run, but all I get for output is 0. ...
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1answer
45 views

How to check output after FPGA Implementation?

I have 10 numbers saved in RAM. I sorted it using Verilog code and saved output in another RAM. I did simulation and it was doing correct sorting. I synthesized it and generate bit file. Now i want ...
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2answers
73 views

Finite State Machine in Verilog

So I am trying to make a basic FSM in verilog to turn on 3 different LEDs. I've looked at examples and other people's work, but I can't understand why mine wont work. Maybe someone can help me spot a ...
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1answer
90 views

How to remove the warning (specify below) in verilog?

I took a signal sum[8:0] in my code.Further,I need only sum[8] in my code (M.S.B of sum). So i used statement assign sum[7:0]=0; It giving WARNING after synthesis given below, WARNING:Xst:646 - Signal ...
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62 views

How to get the longest one's sequence in verilog

I have some problems with a question that ask me to get the number of one's in the longest one's sequence in a 16 bit input using a 5 bit number in verilog. For example (0111011111010101 = 00101 the ...
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56 views

Clock doesn't seem to tick

I have been working on a program for class which acts as a stopwatch, but I've been having troubles where it doesn't work. (Only one digit, the first that would be shown on the four digit display is ...
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36 views

multiplication using Carry-Save with Radix-4 Booth’s Recoding

I'm student working in multiplication using Carry-Save with Radix-4 Booth’s Recoding.I want to implement its design into a verilog code. what is actually the Extra dot ?? where the output of the ...
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45 views

Verilog->FPGA: Synthesis, Implementation, and Bitstream (Xilinx Vivado)

I'm taking an introductory course in verilog/fpga. Can someone tell me where I can find detailed information on what the 3 processes (synthesis, implementation and bitstream) are doing before I ...
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1answer
72 views

Finite State Machine

I tried to write a Verilog code for the finite state machine whose diagram shown below. I see nothing as an output. What is the wrong part of my code? or Is my code completely absurd? My code: ...
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1answer
50 views

Radix-4 multiplication problem

I'm writing code in verilog that take A,B as 8 bit input ,multiply them using radix -4 method . when i execute the code the shft output appear as "xx0" and mutipler can't take the value of the input ...
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1answer
21 views

Node assigned to IOBANK

I'm working with an Altera FPGA. In the Pin Planner there is a choice in the combo box for a 1-bit inout node to be connected to an "IOBANK_n" (under "Location" row). I was expecting only "PIN_nn" are ...
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23 views

how to stop line wrapping in verilog output from Synopsys Design Compiler

I'm getting line wrapping in the gate-level verilog file output from Design Compiler. This is causing problems for Cadence verilog-in. This seems like it would be easy to stop in Design Compiler, but ...
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1answer
54 views

Input signal types in verilog

This is a signal diagram of a transmitter. I don't know the mean of parts are shown in the image. What kind of signals are they? What are their meanings?
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3answers
86 views

Do $fopen and $fwrite works with FPGA implementation also?

I used $fopen , $fclose and $ fwrite in my verilog code. It worked with simulation but when i did FPGA implementation it is not working. My question is that these works with FPGA implementation also ...
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22 views

Locked transfer and split transfer in AHB [closed]

How does the ahb behave when HLOCK = 1, but the slave wants to perform a split transfer. So, does the arbiter consider the HLOCK and decline to assign the bus to a different master or does the ahb ...
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82 views

Verilog for 4 bit wide 2:1 Parameterized MUX (output needs to be decoded to 7 segment display)

I'm working on a project, which I can't seem to figure out. It has to be a parameterized 2:1 MUX, and we're to assume that the inputs are BCD (0-9). The output needs to be displayed on the 7 segment ...
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1answer
46 views

How to remove the below error when doing FPGA implementation of program that use RAM using Xilinx block generator?

I wrote a code that use RAM (created by Xilinx block generator). It's size is 10X10 (total 100 data) . I used INSTANTIATION as below: ...
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32 views

Cadence encounter power analysis

I have written a verilog code for a circuit (test.v) and a testbench (testd_tb.v).I use these commands for generating the power using cadence encounter RTL compiler. I have made 3 folders. ...
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64 views

4 bit x 4 bit using look up table (rom)

This is an introductory level verilog course. I'm trying to generate a 8 bit output from 4 bit multiplied with 4 bit. Here is the code I have so far. ...
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30 views

syntax error verilog code

this sub-code that read the selection line s4-s1 and take the summation of a,b in the selection line =0000, When running this code in ISE project negotiator it gives syntax error tell " Syntax ...
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76 views

Verilog Testbench

I designed a Binary Counter using Basys-2 FPGA Board.Its working on the Basys-2 board,but my test bench is giving me some errors.I couldn't figure out what's the problem,since the timing diagram is ...
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2answers
48 views

How Verilog decides upon simultaneous events

Say we have a function, simple as f(x) = x. Say we have a clock that ticks every 20 nanoseconds, and say we change x as we wish. ...
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35 views

Can't Search for specific value at RAM - verilog

My module has search for specific value at RAM and then return its location address. when I wrote a test bench, I see that the module didn't work correctly! always the output value is "don't care". ...
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1answer
43 views

searching in memory at verilog

I need to make a module which responsible to search overall memory to find a specific value and return the address location, but I have the following error after do Synthesize in Xilinx. ...
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1answer
92 views

Creating a verilog code for 4-bit multiplier using lookup table

I am having trouble creating a verilog code for a 4-bit multipler using a lookup table. I am still trying to grasp the concept of a lookup table. If anyone could help me it would be greatly ...
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How does design compiler constrain combinational paths?

This is with reference to the question asked here: Finding Critical Path of Combinational Logic. When design compiler command report_timing is run, it appears the ...
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1answer
46 views

Synthesizable memory blocks

In Verilog, I am trying to store the input up to 4 previous values and then operate on them.The code is fine in simulation but on FPGA, it calculates output with the current input instead of previous ...
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3answers
50 views

Asynchronous reset in verilog

I am new to verilog and having a bit of trouble getting along with it. I read about asynchronous and synchronous reset and i think i got hold of it but while implementing the same with verilog i am ...
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79 views

Design serial adder for 16 bit register using on full FA

I wrote a serial bit adder for a 15 bit width shift register and a full adder (positive edge trigger, asynchronous reset) I don't know where the error in this code is. This is the code: ...
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1answer
109 views

debouncing pushbuttons in verilog

I have two circuits which I have designed using verilog.One is Counter circuit and other is the debouncing pushbutton circuit.but I dont now how to instantiate a model so that the pushbutton circuit ...
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1answer
207 views

Keypad Scanner Verilog code problem with state machine and column input

I am developing a Keypad both in hardware and Verilog using a DE2 Cyclone II board. I made a keypad using buttons (switches) that follows this schematic: The scanner works by setting the Column ...
2
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1answer
87 views

Why does this Verilog code produce no output on my FPGA?

I am trying to learn Verilog on my own using the DE1-Soc and the Altera university program labs. I am on the very first lab and trying to make a 4 bit-wide two input multiplexer. I wrote this verilog ...
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1answer
67 views

Is it possible to drive a net from two processes when the assignments are conditionally mutually exclusive?

In my experience, driving a net from two separate processes (or always blocks) is a bad idea and will result in a multi-driver error in the tools. However, one of my acquaintances claims that if the ...
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37 views

Verilog multidimensional array

first of all, I already read a lot about multidimensional arrays in Verilog, but I was not able to find an answer. The following code is part of a example program using an oled display on my ...
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109 views

How to connect Xbee to FPGA using SPI?

I am trying to connect an Xbee to a FPGA using SPI. I found some code online to read in the MISO and convert to an 8bit output register. I have it working in the simulation but I cannot get the ...
2
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1answer
26 views

Sensitivity List in Verilog

for example, if there is a case when an output "clear" is sensitive for both the negedge and posedge, do we write it as: always @ (negedge clear, posedge clear)? Or is it impossible to have both ...
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29 views

Digilent EPP handshaking problem

I intend to use my Spartan-6 board as an interface between my mic (which produces I2S data) and PC for live recording. Since UART is too slow, i planned on using Digilent's parallel interface with ...
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2answers
26 views

Number of I/O pins in Xilinx Virtex 5

This might not be a typical Stackoverflow question, but I wasn't sure where I could get this answered. I have Verilog code to multiply two matrices and read them out, but my throughput is limited ...
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2answers
115 views

Reading ADC using Altera DE2 Board (Beginner)

Question: Would it be possible and feasible for a beginner to use Verilog HDL and an Altera DE2 board to read input from a weight sensor's HX711 ADC (see below), and if so: What kind of data am I ...
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142 views

Running UVM example on MODELSIM - ALTERA 10.1d

I want to compile and simulate this simple UVM example using Modelsim-Altera 10.1d tool. ...
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2answers
98 views

Using iSim to simulate 16-bit CLA schematic on Xilinx, all inputs and outputs on the waveform are 'X'. How can I debug?

I'm building a sixteen bit Carry Lookahead Adder for my EE class. I'm definitely a noob to all this so bear with me, however I've been googling for a WHILE and haven't found any answers. Here is the ...
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Verilog inital value for flip flop

I am trying to write verilog code that will set the initial value of the output of a positive-edge triggered flip-flop to 0. The behaviour of the flip-flop circuit is exactly what I want AFTER the ...