Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips.

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How to make full adder (say 4) using just for loop in verilog?

I am making a multiplier and I need a lot of full adder. How to make full adder (say 4) using just for loop? Can I use an instance name with index?
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40 views

Tips on linking SW and HW simulation.

I am total layman about this topic and I would appreciate experienced users to give me some useful tips and hints. I develop some code for arm cortex m0 which I want to simulate in ...
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28 views

Results analysis of the sequential filter and strength-reduced filter in frequency domain

I realized two low-pass filters by Verilog. The filter can be represented as following equation: 1. Sequential filter with 32 stages. For saving the multipliers, I only use one multiplier and do ...
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71 views

A simple FIFO buffer in verilog

I have decided to implement a FIFO buffer in verilog (for fun). Here is my primary prototype you can say : It will consist of a register bank or memory. Each register will be of size N and there ...
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1answer
25 views

Cursor (waveform) reading not the same with transcript window

I have run a simulation of a Verilog code testbench. I ran it in ModelSim, but why the reading I got from just using the cursor on the waveform is different from the one in transcript window. While ...
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47 views

Why does iSim give a different result than hardware

I am working on a MIPS CPU for an FPGA - this is mostly a personal project to understand FPGA's. I have a 5 stage pipeline CPU implementation working correctly when run on iSim, however when I run it ...
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1answer
67 views

Can someone explain a couple of lines of Verilog to me?

I'm a student trying to learn Verilog on my own with a dev board. This is just a simple and short module. I just need some clarifications. ...
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2answers
47 views

bit shifting using verilog

Im using verilog language for my program using ISE 14.5, when I give input for example x=0.707 and simulate it in test bench, it gives me wrong output because it consider 0.707 as 1. my question is ...
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1answer
22 views

Error Loading Design Unresolved Reference

Please help! DUT: AND gate module ANDgate(a, b, c); input a; input b; output c; assign c = a & b; endmodule TESTBENCH: Without task ...
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16 views

How to check input data and out data match using Verilog-A

I am trying to check data on an input and output of a circuit using verilog-a. So far I have tried bitwise comparison and masking, ex: ...
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1answer
76 views

UART to Bluetooth

I seem to find only partial explanations regarding this question, I've used Bluetooth in previous projects but I plan to use it on an FPGA project. Currently The FPGA is connecting using a UART ...
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1answer
40 views

where should I instantiate the DUT object? In the testbench file or in the task?

I am making a testbench in Verilog where it will call different test cases from different modules, each module, one test case/task. I am a beginner in making testbench, can I know where should I ...
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Verilog, JKFF, Finite State Macine [duplicate]

I am to implement these two JKFFs (this is for Finite State machine). However, I cannot get this to work correctly. Someone please fix my code! Disregard z1 and z0 as they are correctly done. ...
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31 views

Finite State Machine, Verilog, JKFF [duplicate]

I am to implement this state diagram using two JKFFs, to which I have found minimal expressions to (J1, J0, K1, and K0 in JKFF and RG (z1) and RN (z0) in main file). However, it puzzles me how in my ...
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1answer
101 views

Finite State Machine, Verilog Code

I have everything right now, but the output I desire should be 00 00 11 00 00 00 00 10 00 00 00 when the clock is 1(z1z0). Can someone tell me what is wrong with my code? I've checked my Kmap numerous ...
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59 views

Having FPGA to output sound on “line out” pin using verilog

I am trying to write a verilog code for FPGA which will output sound from the embedded "line out" pin. I use Quartus II and Altera DE1. I am new to hardware programming, therefore it just takes too ...
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4answers
122 views

Generate an 40MHz Clock on an FPGA with 100Mhz clock

I'm trying to generate an 40MHz clock on an 100Mhz FPGA kind of strugle with the Verilog CODE, I rediredted the Clock to a pin to check the 100Mhz: ...
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1answer
47 views

Need help converting 8 bit input into 3, 4 bit outputs

I have a midterm coming up on digital system design. My professor developed an ASM chart for a problem and I decided that I would try to fill out the code for practice. The simulation runs, it just ...
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1answer
40 views

Designing of a 2:1 multiplexer for 64 bit input and output [closed]

How to design a 2:1 mux for a 64 bit input and output using Verilog code?
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60 views

Using GPIO in Altera

I'm trying to test the GPIO functionality of Altera (DE1, Cyclone II) with this simple program. If the GPIO_0[0] gets a high (1) signal, LEDG[0] will light up. If it receives a low (0) signal, ...
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1answer
212 views

Do If else have priority in verilog?

I have some query about the priority of if else in verilog. For example. If (a) b else if c d else if e f else g At here, those a,b,c...g are ...
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59 views

How to simulate and initialise Block Memory ROM created using Xilinix CORE generator?

I created the ROM correctly using the CORE generator and the correct .coe file. There is supposed to be instruction words inside the memory (32*256). But the data bus out of the memory is always set ...
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1answer
63 views

What are LUT (look up table)? [duplicate]

I am learner in verilog with less knowledge and trying to develop more understanding.I wrote a simple verilog code and synthesize and implement it. I do not have understanding of Look up tables. When ...
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2answers
65 views

Verilog Assignment

I'm designing a Fahrenheit to Celsius converter using algorithmic state machines. I'm trying to get the following code to run, but all I get for output is 0. ...
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1answer
49 views

How to check output after FPGA Implementation?

I have 10 numbers saved in RAM. I sorted it using Verilog code and saved output in another RAM. I did simulation and it was doing correct sorting. I synthesized it and generate bit file. Now i want ...
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2answers
89 views

Finite State Machine in Verilog

So I am trying to make a basic FSM in verilog to turn on 3 different LEDs. I've looked at examples and other people's work, but I can't understand why mine wont work. Maybe someone can help me spot a ...
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105 views

How to remove the warning (specify below) in verilog?

I took a signal sum[8:0] in my code.Further,I need only sum[8] in my code (M.S.B of sum). So i used statement assign sum[7:0]=0; It giving WARNING after synthesis given below, WARNING:Xst:646 - Signal ...
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1answer
68 views

How to get the longest one's sequence in verilog

I have some problems with a question that ask me to get the number of one's in the longest one's sequence in a 16 bit input using a 5 bit number in verilog. For example (0111011111010101 = 00101 the ...
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1answer
60 views

Clock doesn't seem to tick

I have been working on a program for class which acts as a stopwatch, but I've been having troubles where it doesn't work. (Only one digit, the first that would be shown on the four digit display is ...
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48 views

multiplication using Carry-Save with Radix-4 Booth’s Recoding

I'm student working in multiplication using Carry-Save with Radix-4 Booth’s Recoding.I want to implement its design into a verilog code. what is actually the Extra dot ?? where the output of the ...
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1answer
80 views

Finite State Machine

I tried to write a Verilog code for the finite state machine whose diagram shown below. I see nothing as an output. What is the wrong part of my code? or Is my code completely absurd? My code: ...
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1answer
55 views

Radix-4 multiplication problem

I'm writing code in verilog that take A,B as 8 bit input ,multiply them using radix -4 method . when i execute the code the shft output appear as "xx0" and mutipler can't take the value of the input ...
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23 views

Node assigned to IOBANK

I'm working with an Altera FPGA. In the Pin Planner there is a choice in the combo box for a 1-bit inout node to be connected to an "IOBANK_n" (under "Location" row). I was expecting only "PIN_nn" are ...
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1answer
24 views

how to stop line wrapping in verilog output from Synopsys Design Compiler

I'm getting line wrapping in the gate-level verilog file output from Design Compiler. This is causing problems for Cadence verilog-in. This seems like it would be easy to stop in Design Compiler, but ...
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1answer
56 views

Input signal types in verilog

This is a signal diagram of a transmitter. I don't know the mean of parts are shown in the image. What kind of signals are they? What are their meanings?
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3answers
103 views

Do $fopen and $fwrite works with FPGA implementation also?

I used $fopen , $fclose and $ fwrite in my verilog code. It worked with simulation but when i did FPGA implementation it is not working. My question is that these works with FPGA implementation also ...
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24 views

Locked transfer and split transfer in AHB [closed]

How does the ahb behave when HLOCK = 1, but the slave wants to perform a split transfer. So, does the arbiter consider the HLOCK and decline to assign the bus to a different master or does the ahb ...
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147 views

Verilog for 4 bit wide 2:1 Parameterized MUX (output needs to be decoded to 7 segment display)

I'm working on a project, which I can't seem to figure out. It has to be a parameterized 2:1 MUX, and we're to assume that the inputs are BCD (0-9). The output needs to be displayed on the 7 segment ...
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1answer
52 views

How to remove the below error when doing FPGA implementation of program that use RAM using Xilinx block generator?

I wrote a code that use RAM (created by Xilinx block generator). It's size is 10X10 (total 100 data) . I used INSTANTIATION as below: ...
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Cadence encounter power analysis

I have written a verilog code for a circuit (test.v) and a testbench (testd_tb.v).I use these commands for generating the power using cadence encounter RTL compiler. I have made 3 folders. ...
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96 views

4 bit x 4 bit using look up table (rom)

This is an introductory level verilog course. I'm trying to generate a 8 bit output from 4 bit multiplied with 4 bit. Here is the code I have so far. ...
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1answer
30 views

syntax error verilog code

this sub-code that read the selection line s4-s1 and take the summation of a,b in the selection line =0000, When running this code in ISE project negotiator it gives syntax error tell " Syntax ...
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106 views

Verilog Testbench

I designed a Binary Counter using Basys-2 FPGA Board.Its working on the Basys-2 board,but my test bench is giving me some errors.I couldn't figure out what's the problem,since the timing diagram is ...
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2answers
53 views

How Verilog decides upon simultaneous events

Say we have a function, simple as f(x) = x. Say we have a clock that ticks every 20 nanoseconds, and say we change x as we wish. ...
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1answer
43 views

Can't Search for specific value at RAM - verilog

My module has search for specific value at RAM and then return its location address. when I wrote a test bench, I see that the module didn't work correctly! always the output value is "don't care". ...
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1answer
47 views

searching in memory at verilog

I need to make a module which responsible to search overall memory to find a specific value and return the address location, but I have the following error after do Synthesize in Xilinx. ...
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1answer
135 views

Creating a verilog code for 4-bit multiplier using lookup table

I am having trouble creating a verilog code for a 4-bit multipler using a lookup table. I am still trying to grasp the concept of a lookup table. If anyone could help me it would be greatly ...
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How does design compiler constrain combinational paths?

This is with reference to the question asked here: Finding Critical Path of Combinational Logic. When design compiler command report_timing is run, it appears the ...