Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips.

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How to use UART port for sending status in verilog

I am developing various verilog modules with state machine for a fpga board. When i have done simulation of the modules i have used "$display" to get what is happening in the module or otherwise the ...
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Can I design a health monitoring system to monitor ECG and pulse by coding in Verilog? [on hold]

I have sample ECG and Pulse signals in my database.
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82 views

32 Bit Increment Circuit and Verilog Program

I have to build a circuit that stores a 32-bit number. The circuit features a control signal inc that, when active, increments the stored value by 3 in each cycle. If inc is 0, the circuit simply ...
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55 views

T Flip Flop Verilog

I don't quite understand flip flops that well so I just wanted to see if this verilog code I wrote makes sense and if the outputs are what are expected from a T Flip Flop verilog code: ...
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3answers
33 views

Verilog assign result of module

I am trying to take the result of a module and assign it to an input of another module, however I keep getting an error about declaring net types. I feel like I'm missing part of the syntax rules ...
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1answer
41 views

How do i connect my Nexys 4 Artix-7 Digilent FPGA board to my PN532 NFC/RFID Controller Shield for Arduino?

I am currently working on a FPGA project which i know nothing about. Truth to be told, I am learning how the FPGA and the Verilog language works from scratch and I am indeed experiencing lots of ...
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41 views

Verilog 8 Bit ALU

Here's what I have so far but I'm stuck with what to do for the f values for the last two and whether the if statement syntax is correct. Any tips? ...
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1answer
58 views

Modelling Circuit from FSM using Verilog

I am trying to understand the concept of modeling a circuit from a FSM in Verilog. I have tried to write down the procedure that I have used in the image below just to make sure that I did it right: ...
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20 views

3 Bits Booth's Algorithm Verilog

I am trying to write a 3 Bits Booth's Algorithm in verilog and I believe I have it done but I keep getting the wrong output when I run the simulation. I still haven't found the issue. Here's my code: ...
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17 views

Sharing output of module in verilog

Having started to learn Verilog there was this doubt that crept my mind which is as follows:- 1) Consider the following Verilog code with 3 modules. Module 'Clock' that simulates a clock, module D ...
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How would you implement a System like this easily using Altera Tools and the DE1-SOC

I want to implement a system as follows: Four cores (Processing Elements) to read a black and white image of 240x240 pixels = 57.600 pixels in total (each pixel with a intensity integer value of 0 to ...
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1answer
23 views

verilog code to perform {w=(3*(p+t-1))/t} with look up taples

I want verilog code to perform {w=(p+t-1)/t} with look up taples . The lookup table is to be realized as a ROM where: p is 3 bits t is 2 bits (and not equal to 0)
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4answers
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Are FPGAs more intuitive to learn than microprocessors for doing DSP

I want to learn to make DSP hardware I have never done any DSP and only a little bit of programming, but I have been making analog circuits for 15 years. I like the idea of learning FPGAs because it ...
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1answer
64 views

How to properly describe a Math Equation in Verilog to be synthesizable?

I have not been able to find a book or information in internet, about the correct way to describe a Math Equation in Verilog. With the correct way I mean for example, how to analyze the equation and ...
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1answer
57 views

Verilog BitSet Circuit

A specific type of bit-level manipulation consists in setting or clearing one single bit in a multi-bit value, given its index and its new value. This operation can be implemented in hardware by a ...
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39 views

designing a state machine to detect a certain bit

So, I need to create a state machine (mealy machine) to detect the bit 1010 and also I need to code it in verilog. Here is a picture of my state machine: So, I created the state machine and Now I ...
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1answer
23 views

Quartus Waveform File Representation

I have selected the inputs as 8 bit count values that increment over time. The 8 bit value should be parallel in and parallel out. But the bits are spaced over time. Can you please explain why the ...
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1answer
41 views

Eight bit ALU with Overflow in Verilog

I have the above assignment and here's what I have so far in verilog: ...
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84 views

7-1 Multiplexer Inputs

I'm a computer science student taking a required Computer Organization course so I'm very new to this electrical engineering stuff. I want to know how does one construct a 7-1 multiplexer? I know the ...
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136 views

pulse width modulation

I need help on number one of this practice assignment. I barely learned about this so it is kind of hard me to understand it right now. So any advice or help is appreciated. I want to determine the ...
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1answer
52 views

FPGA design rules - Using a Module Output Register Value Internaly

I'm trying to optimize a verilog code and I found something that I don't feel it's correct. I found a module that has an output and it's using that output value as a condition in a case statement. ...
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30 views

I am trying to build a 4 bit squarer [duplicate]

I need some help with building a 4-bit squarer block diagram. Can anyone help me or know a link to a 4 bit squarer block diagram or a verilog code for it? Thanks in advance.
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62 views

I need some assistance on improving my Verilog code

Basically, I am using a lookup table to output in bcd the square of a single digit bcd. I need help on improving my code. So, when I input a number I get a square. But what I want to do is output the ...
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1answer
249 views

Vivado is removing registers which will be used

I am working on a verilog program that I want to have display some sort of audio waveform (captured from my microphone) over a VGA. I use the following module to shift in new audio samples, and swap ...
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33 views

Generated clock constraints in vivado

I created my own clock since I need a 2Mhz clock and the clock generator IP wont let me go bellow 6Mhz. I created a clock divider module. ...
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1answer
42 views

Is $realtobits synthsizeiable?

I have been trying to figure out why my verilog program is not working for hours. To test it I just added some constants as inputs to my module and I am using the integrated logic analyser to check ...
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creating a bcd squarer using verilog

Basically, I am using a lookup table to output in bcd the square of a single digit bcd. The problem that I have is that it is not outputting the correct answer. For example: the result I get for the ...
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1answer
31 views

Multiplier 4-bit with verilog using just full adders

I am trying to write the test bench part but I don't know how to do it. Basically, I want to test out 0x10 or 5x5. I don't if what I have is right. here's a pic to give you some idea of what i am ...
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40 views

Index in block ram is offset by one from position of write

I am having an issue with block ram I am using to create a table to powers of a 64 bit floating point number. I store powers between x^1600 and x^-1600. For some reason when I try to read the table ...
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2answers
80 views

When should I use negedge on a clock signal?

I was reading about block ram and I came across the following post. I notice here that whoever wrote the code is using negedge on the clock signal. Thus far almost all the examples I have seen of ...
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30 views

Xilinx ISE ERROR:Xst:2369 - Empty project file “C:\xxxx” what is it about?

I am trying to see the schematic output of my verilog module in Xilinx ISE. However, I am getting this silly error: ERROR:Xst:2369 - Empty project file "C:\Users\aozel\Desktop\Verilog ...
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34 views

I get error in vivado when I try to use source clock of generated one

I want to have two clocks in my project. One that sends output to a VGA and runs at 25 Mhz and another which runs my mandelbrot set calculation at a higher frequency. Here is the code I have. ...
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39 views

impact of removing “+:d” in verilog timing section

I would like to start with the simple example of a flop, and my concentration lies in the specify section , so please ignore the functionality part ...
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38 views

Do I have to create generated clocks in the top level module?

I have been working on a module to send VGA output from my fpga. I want to generate the 25 MHz clock inside of the vga module. vga_clk_gen is from the clocking wizzard IP in vivado. I get the ...
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1answer
45 views

FPGA VGA driver not working

I am not really sure what is wrong with my code bellow for a vga. All I want the program to do is display a solid color on the monitor. I want to use the switches on my card to change the color ...
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1answer
65 views

how to reset a memory array in verilog?

I have a memory like this: reg [7:0] memory [1023:0] How should I use a for-loop to reset the memory in verilog? Please give me the code. For example if ...
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2answers
53 views

Verilog: how to synchronously assign wire out with register?

This is the output of ISim simulation: I want to decrease tx_data_ctr by 1 when flags_from_clk_div turns to 4'b0000 so sda_flag_from_transmit_byte take initial bit from tx_data[7:0]. However, I ...
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1answer
37 views

Verilog: How to avoid 'Redeclaration of ansi port'

I am trying to implement a start condition for i2c. And to ISim simulation I did. However, I keep getting this warning: ...
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0answers
26 views

Strange verilog errors in vivado

I am trying to make a floating point module to take the integer power of a double base. I want to compute it using x^y = e^(y*ln(x)). I am using the non-blocking floating point IPs provided by ...
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1answer
33 views

Verilog-A: pass an array without predefined size as input to a function

It seems fairly easy to pass to a function array if its size is already known: analog function integer ArrayIsZeros; input [7:0] array; integer array [7:0] ; But ...
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Verilog, how to get quotent and remainder in same operation

Say I need to get the quotient and remainder of a divsion operation. For instance. ...
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48 views

Why do I get a “[Synth 8-5413] Mix of synchronous and asynchronous control for register” warning in Vivado?

The code bellow is to take the reciprocal of a fixed point number using Newton's method. When start is asserted the state machine enters the estimate state. To get ...
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1answer
116 views

Verilog: Are there some basic rules for port settings?

Iam trying to write a SPI master module by myself to learn FPGA-Verilog efficiently. Here is the spi_master module: ...
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4answers
161 views

Driving a 7 Segment Display with a register vs wire

I few days ago when I got my FPGA I created a module to drive my 7-Segment display. I used only continuous assignments to drive the leds. ...
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1answer
42 views

Error when passing wire of different size to module input

I have a module to display a base 10 number on my 7-Segment display. ...
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2answers
42 views

BASYS2 - Verilog: how to properly edit ucf file?

I am a newbie at FPGA. I bought BASYS2 digilent board(Spartan3E). I have background on microcontrollers. C/C++ is no problem for me. But I am having some trouble with FPGA. Actually, not with FPGA ...
3
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1answer
42 views

Xilinx FPGA, error creating generated clock

I just got a Digilent Basys 3 board (Artix-7 FPGA) and I am trying to create a program to transmit data over the UART-USB connection. I wrote a module but when I tried to implement it I got a timing ...
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2answers
50 views

Verilog code question

I'm new in Verilog and I need to create a module that when Entry=1, it will increment 5'b000100 in the "Money" output. This is the code that I made, but it's not working properly. The program it's ...
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40 views

JTAG TAP Design code verilog( Advanced Debug Interface)

I am designing a JTAG unit for a processor. For that, i have initially designed a TAP controller by looking at the FSM of the TAP. Now, i have being given this snippet of code: ...