Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips.

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Finite State Machine

I tried to write a Verilog code for the finite state machine whose diagram shown below. I see nothing as an output. What is the wrong part of my code? or Is my code completely absurd? My code: ...
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Radix-4 multiplication problem

I'm writing code in verilog that take A,B as 8 bit input ,multiply them using radix -4 method . when i execute the code the shft output appear as "xx0" and mutipler can't take the value of the input ...
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Node assigned to IOBANK

I'm working with an Altera FPGA. In the Pin Planner there is a choice in the combo box for a 1-bit inout node to be connected to an "IOBANK_n" (under "Location" row). I was expecting only "PIN_nn" are ...
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how to stop line wrapping in verilog output from Synopsys Design Compiler

I'm getting line wrapping in the gate-level verilog file output from Design Compiler. This is causing problems for Cadence verilog-in. This seems like it would be easy to stop in Design Compiler, but ...
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50 views

Input signal types in verilog

This is a signal diagram of a transmitter. I don't know the mean of parts are shown in the image. What kind of signals are they? What are their meanings?
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Do $fopen and $fwrite works with FPGA implementation also?

I used $fopen , $fclose and $ fwrite in my verilog code. It worked with simulation but when i did FPGA implementation it is not working. My question is that these works with FPGA implementation also ...
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Locked transfer and split transfer in AHB [on hold]

How does the ahb behave when HLOCK = 1, but the slave wants to perform a split transfer. So, does the arbiter consider the HLOCK and decline to assign the bus to a different master or does the ahb ...
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53 views

Verilog for 4 bit wide 2:1 Parameterized MUX (output needs to be decoded to 7 segment display)

I'm working on a project, which I can't seem to figure out. It has to be a parameterized 2:1 MUX, and we're to assume that the inputs are BCD (0-9). The output needs to be displayed on the 7 segment ...
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37 views

How to remove the below error when doing FPGA implementation of program that use RAM using Xilinx block generator?

I wrote a code that use RAM (created by Xilinx block generator). It's size is 10X10 (total 100 data) . I used INSTANTIATION as below: ...
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Cadence encounter power analysis

I have written a verilog code for a circuit (test.v) and a testbench (testd_tb.v).I use these commands for generating the power using cadence encounter RTL compiler. I have made 3 folders. ...
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45 views

4 bit x 4 bit using look up table (rom)

This is an introductory level verilog course. I'm trying to generate a 8 bit output from 4 bit multiplied with 4 bit. Here is the code I have so far. ...
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27 views

syntax error verilog code

this sub-code that read the selection line s4-s1 and take the summation of a,b in the selection line =0000, When running this code in ISE project negotiator it gives syntax error tell " Syntax ...
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57 views

Verilog Testbench

I designed a Binary Counter using Basys-2 FPGA Board.Its working on the Basys-2 board,but my test bench is giving me some errors.I couldn't figure out what's the problem,since the timing diagram is ...
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How Verilog decides upon simultaneous events

Say we have a function, simple as f(x) = x. Say we have a clock that ticks every 20 nanoseconds, and say we change x as we wish. ...
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30 views

Can't Search for specific value at RAM - verilog

My module has search for specific value at RAM and then return its location address. when I wrote a test bench, I see that the module didn't work correctly! always the output value is "don't care". ...
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33 views

searching in memory at verilog

I need to make a module which responsible to search overall memory to find a specific value and return the address location, but I have the following error after do Synthesize in Xilinx. ...
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61 views

Creating a verilog code for 4-bit multiplier using lookup table

I am having trouble creating a verilog code for a 4-bit multipler using a lookup table. I am still trying to grasp the concept of a lookup table. If anyone could help me it would be greatly ...
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How does design compiler constrain combinational paths?

This is with reference to the question asked here: Finding Critical Path of Combinational Logic. When design compiler command report_timing is run, it appears the ...
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Synthesizable memory blocks

In Verilog, I am trying to store the input up to 4 previous values and then operate on them.The code is fine in simulation but on FPGA, it calculates output with the current input instead of previous ...
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Asynchronous reset in verilog

I am new to verilog and having a bit of trouble getting along with it. I read about asynchronous and synchronous reset and i think i got hold of it but while implementing the same with verilog i am ...
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56 views

Design serial adder for 16 bit register using on full FA

I wrote a serial bit adder for a 15 bit width shift register and a full adder (positive edge trigger, asynchronous reset) I don't know where the error in this code is. This is the code: ...
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82 views

debouncing pushbuttons in verilog

I have two circuits which I have designed using verilog.One is Counter circuit and other is the debouncing pushbutton circuit.but I dont now how to instantiate a model so that the pushbutton circuit ...
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128 views

Keypad Scanner Verilog code problem with state machine and column input

I am developing a Keypad both in hardware and Verilog using a DE2 Cyclone II board. I made a keypad using buttons (switches) that follows this schematic: The scanner works by setting the Column ...
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68 views

Why does this Verilog code produce no output on my FPGA?

I am trying to learn Verilog on my own using the DE1-Soc and the Altera university program labs. I am on the very first lab and trying to make a 4 bit-wide two input multiplexer. I wrote this verilog ...
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57 views

Is it possible to drive a net from two processes when the assignments are conditionally mutually exclusive?

In my experience, driving a net from two separate processes (or always blocks) is a bad idea and will result in a multi-driver error in the tools. However, one of my acquaintances claims that if the ...
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Verilog multidimensional array

first of all, I already read a lot about multidimensional arrays in Verilog, but I was not able to find an answer. The following code is part of a example program using an oled display on my ...
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87 views

How to connect Xbee to FPGA using SPI?

I am trying to connect an Xbee to a FPGA using SPI. I found some code online to read in the MISO and convert to an 8bit output register. I have it working in the simulation but I cannot get the ...
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25 views

Sensitivity List in Verilog

for example, if there is a case when an output "clear" is sensitive for both the negedge and posedge, do we write it as: always @ (negedge clear, posedge clear)? Or is it impossible to have both ...
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25 views

Digilent EPP handshaking problem

I intend to use my Spartan-6 board as an interface between my mic (which produces I2S data) and PC for live recording. Since UART is too slow, i planned on using Digilent's parallel interface with ...
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Number of I/O pins in Xilinx Virtex 5

This might not be a typical Stackoverflow question, but I wasn't sure where I could get this answered. I have Verilog code to multiply two matrices and read them out, but my throughput is limited ...
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80 views

Reading ADC using Altera DE2 Board (Beginner)

Question: Would it be possible and feasible for a beginner to use Verilog HDL and an Altera DE2 board to read input from a weight sensor's HX711 ADC (see below), and if so: What kind of data am I ...
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88 views

Running UVM example on MODELSIM - ALTERA 10.1d

I want to compile and simulate this simple UVM example using Modelsim-Altera 10.1d tool. ...
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Using iSim to simulate 16-bit CLA schematic on Xilinx, all inputs and outputs on the waveform are 'X'. How can I debug?

I'm building a sixteen bit Carry Lookahead Adder for my EE class. I'm definitely a noob to all this so bear with me, however I've been googling for a WHILE and haven't found any answers. Here is the ...
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67 views

Verilog inital value for flip flop

I am trying to write verilog code that will set the initial value of the output of a positive-edge triggered flip-flop to 0. The behaviour of the flip-flop circuit is exactly what I want AFTER the ...
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108 views

sequence detector in verilog

I have the task of building a sequence detector Here's the code : ...
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75 views

Convert IEEE Double to Integer - Verilog

I want to convert the IEEE Double value computed in my code to Integer. E.g. I have computed: X = 64'hxxxxxxxxxxxxxxxx; Now i want to use it as index of an array as: some_array[X]; How can I do it? ...
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19 views

Convert IEEE Double to Integer - Verilog [duplicate]

I want to convert the IEEE Double value computed in my code to Integer. E.g. I have computed: X = 64'hxxxxxxxxxxxxxxxx; Now i want to use it as index of an array as: some_array[X]; How can I do it? ...
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61 views

Simulating IP core (i.e ALT_FP_DIV) on Altera modelSim gives “z” (high impedance) as output

I'm trying to simulate (functional Test) a project that contains both my own codes and some instances of Altera Floating Point IP Core generated using MegaWizard on ModelSim. All the instantiated IP ...
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28 views

how to use generate for multiple module instantiation in verilog

Please tell me the error. I'm using the following code and each time I get this error during compilation for the "generate" wordsize has already been defined ...
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109 views

What are some things that can be done in VHDL but not in verilog and vice versa?

VHDL and Verilog are quite similar but do not have the same features, there is certainly a massive overlap though. What are some things which are easier to do in VHDL but not so easy or even ...
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SystemC vs HDLs

I am currently involved in a university project to implementing a processor of an existing instruction set. The idea is that by the end of the project I should be able to synthesise this design and ...
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65 views

4 port 12 bit mux is consuming 48 macrocells!

I'm programming on the coolrunner II cpld. It is running out of resources so I decided to implement my own 4 port, 12 bit mux. After implementation I find that it's using over 40 macrocells. Any way ...
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Verilog, register values

For learning purposes, I am trying to implement a very simple processor in verilog. The idea is that every clock cycle the machine either fetches the next 4 instructions from memory (each instruction ...
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90 views

More elegant code for synchronous square wave generator in Verilog

I'm self studying with Chu's FPGA prototyping book. Exercise 4.7.1 asks for a programmable square wave generator: A programmable square-wave generator is a circuit that can generate a square wave ...
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85 views

Ring counter in verilog

I have the task of designing a ring counter in verilog using shift operator. Here is the code so far along with test bench : ...
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95 views

What does “+:” mean in Verilog?

When I was looking at someone's Verilog code, I found "+:" in Verilog. It looks like an arithmetic function but I'm not sure. I never seen before. Does anyone know this usage? Update: ...
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This state machine does not go into an initial state on start

This is my state machine code: ...
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317 views

What is the set in D FF?

I'm trying to implement a 3-bit counter using basic gates (AND, OR, XOR, NOT etc..) around 3 D-type flip-flops. The input is an increment signal that when set to 1 will allow the counter to increment ...
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Emulation of slideshow

I am doing emulation of slideshow of images in which i store pixel values in SRAM using processor and read data using VGA .It works fine when i store data in sram and read it through VGA seperately. ...