Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips.

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Unable to assign value in an always-block

NO IDEA that the value of register just never changes whatever the clock and the cases are. but no problem while compiling. WHAT is happenning? It is really confusing... ...
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1answer
30 views

What does this sentence mean in this question (simulator can handle X inputs)?

In my book, one question requires me to find the verification sequence for a circuit. From what I understand, verification sequence must be such that every path is traversed. Then the book ...
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1answer
29 views

Xilinx XPS : On what bases the AXI master changes AWSIZE/ARSIZE…?

I have built my system with AXI interface using AXI4 From XILINX PLATFORM STUDIO(XPS). I used 32 bit data and address buses.I am facing problem with respect to xSIZE. In firmware(SYSTEM C), I have 8 ...
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2answers
54 views

Introduce delays of alternating value for synthesis on hardware

My question here is with reference to this question previously asked. Currently, I am able to generate delays for each signal as desired. Next, I want to generate different delays for alternate ...
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2answers
93 views

Introduce delay on a single bit signal w.r.t. input clock

I have seen this question and removed the "#.." part of my code to introduce delay, since my code will ultimately run on hardware. Anyway, I am trying with counters and not able to introduce the ...
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1answer
66 views

Reseting a 128 adress* 16 words memory

I'm doing my term project, in which I have a memory, which can be changed by the user. The specification is that whenever reset is activated, data on this register should be reset to all zeros. I ...
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58 views

Can an AHB master be connected directly to an AHB slave

I am trying to design AMBA 3 AHB (only one master and one slave) using verilog. My design consists of two modules, the master module to write data from master to slave, the second module is the slave ...
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1answer
55 views

Verilog Ring Oscillator problem

I am trying to make a ring oscillator inside of a Xilinx's CoolRunner-II CPLD and trying to measure how many ring-oscillator cycle fits inside a low half of external 10MHz clock. Below is simple code ...
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1answer
49 views

case statement without always

Can I have a case statement without a always block like an inline if condition does not need a always function? ...
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2answers
38 views

data and control path [closed]

While designing a digital system, do we always have to partition Data paths and the control units? If not, what could be the situations where we really don't have to bother about the partitioning of ...
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1answer
53 views

Can these group of statements be reduced or optimized?

First block of code: ...
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2answers
52 views

GUI for writing HDL and viewing simulation? [closed]

I am a software developer and I'd like to code for FPGAs. Prior to buying an FPGA I thought it might be better to obtain a simulator where I could practice my HDL and see whether I can get the hang of ...
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1answer
69 views

Mux and Adder going into Infinite Loop

I have been trying to learn verilog with help of a project. The mix that takes adder output as input and gives input to adder as per the control signal is going into an infinite loop, but it should ...
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1answer
62 views

Signal is connected to following multiple drivers

This is the top module combining the Circular Shift Register, Multiplexer and Adder. ...
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2answers
37 views

Verilog - creating a timer to count a second [duplicate]

I'm using a FPGA (BEMICROMAX10) to create a digital clock using seven segment displays on a breadboard, and I'm having issues getting the seconds to count exactly 1 second. The clock system input I'm ...
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2answers
129 views

Executing an long equation in one clock cycle [closed]

I am using DE2-115 Board for doing traversal in a forest data structure in 50 MHz frequency. Multiple trees have been stored in on-chip ROM, now I need to set the address which can point to a certain ...
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2answers
133 views

register with enable signal, problem of understanding simulation results

I simulated a 32-bit register with an enable input in Vivado. The following things are unclear to me: I don't understand why 0xFFFFFFFF is latched at 5 ns and not the previous value 0x0abcdeff. ...
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1answer
25 views

Verilog 'cannot match operand(s)' & 'multiple constant drivers'

I'm working on a Verilog project using a FPGA (BEMICROMAX10) and some breadboard components. The project is to make a digital clock in which you can also set the time using the buttons on the FPGA. I ...
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1answer
48 views

How to Insert values in 2d array in verilog

I wrote a verilog code for Circular Shift register using a 2-d array, but can't seem to insert values in the array. Here is my code ...
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1answer
42 views

operand isolation in RTL

I'm trying to build some low power circuits at the RTL level. How would I go about coding operand isolation so that the synthesis tool (ASIC/FPGA) recognizes it. Assuming the spec requires the output ...
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2answers
111 views

Need help with sorting a 32 bit string

I have to program a combinational circuit which sorts a 32 bit array like this: 10011011010101101010101010110010 ==> 00000000000000011111111111111111 The input must be parallel and 32 bit. The output ...
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1answer
55 views

verilog: binary code decimal and gray code counter implementation

I am trying to implement a 8-bit counter that does both BCD(Binary Code decimal) and gray code sequence. If the input control = 0, the circuit will count in BCD and if the input control = 1, the ...
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1answer
76 views

How to establish a communication between FPGA and CPU, in real-time? [closed]

I am working on a project that involves FPGA and CPU communication(in real-time - i.e, CPU and FPGA should function together). I have already designed and tested the UART communication protocol on ...
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1answer
25 views

Verilog Shift Register with Two Inputs

I am attempting to create a 32-bit shift register in Verilog with two inputs, DATA0 and DATA1. DATA0 is driven low to input a 0 to the register and DATA1 is driven low to input a 1 to the register. ...
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53 views

Verilog 8 bit adder & testbench - not working

Resolved - After making it compileable in Quartus by naming the for loop in my8bitadder and doing Greg's fixes, the code works fine now. Thanks guys! I've made an 8 bit adder but I can't seem to get ...
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30 views

Nexys4DDR temperature sensor reading code error

I am trying to read the temperature sensor on my Nexys4DDR board using i2c protocol. My code is outputting all of the leds as 1, thus giving me the default value. Where am I going wrong? ...
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1answer
59 views

How to use a module in verilog as in build operator like OR, AND, XOR etc. function?

I wanted to module GR as the operator. how can I? ...
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3answers
242 views

Why would you want to write to a file when writing VHDL? [closed]

I have never so far been in the need to write to a file when making a testbench in vhdl. Seeing the signals being plotted has always been enough so far. Could someone please give me a case or the ...
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39 views

CFI flash interface in verilog

I am working on an Intel’s CFI - Flash (28F640J3) interface in verilog. I have written a code and tested it for many commands; read, write, erase. But I am facing problem with 'Write Buffer’ and read ...
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1answer
37 views

Showing negative numbers in Verilog

I am writing a program for a 16-bit ripple carry adder and stumbling a little at the end. When I run my code (which includes negative numbers), it's doing the math right, but giving me all positive ...
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2answers
81 views

Correctly initialize a shift register (Verilog)

I've been struggling with a very simple Verilog program. It's a 4 bit shift register that gets rotated at every clock cycle and drives four LEDs. (As you can tell I'm new to FPAGs and HDLs.) The ...
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1answer
53 views

How can assign a synthesizable string to a byte array in SystemVerilog?

I want to initialize a byte array (or any other possible type) to a long string. For example define: string str = "abcdefg". I read these two links (1 & 2) but ...
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1answer
54 views

For loop in `define Macro

I searched on SO, and on web, no where found the ans. I have following code, where It success fully parsed `define and generate expected results, but if number of times calling of macro is large then, ...
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1answer
77 views

How to create .VCD file or Simulation activity file of verilog code?

I have Verilog's code. It is simulated correctly and synthesize too. I wanted to write.VCD(value change dumped) file. I got from internet few command to generate VCD file as given below: ...
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63 views

verilog state machine - state won't update

So I'm trying to simulate a state machine with outputs s and v and a state. for some reason our s and v values are updating but the state refuses to change, any help would be awesome ...
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2answers
154 views

Is it right to initialize a reg in verilog and apply condition with initial value of reg in Verilog?

I have the little doubt related to initializing condition in Verilog. Like in given statement: ...
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1answer
49 views

How to find minimum among variables with excluding variables having zero values in Verilog?

I have 6 variables names D1,D2,D3,D4,D5,D6. I wanted to find minimum among them but excluding the zeros if any present. I did same in MATLAB by using below command: ...
3
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1answer
83 views

Dividing a clock in Verilog - is it OK?

Dividing a clock down in Verilog is a basic exercise, and there are loads of answers online about how to do it. What I want to know is whether it is OK to use a clock that has been divided down using ...
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2answers
128 views

Synchronuous Combination Lock

I'm trying to implement a synchronous combination lock that will unlock once it receives "101011" using verilog. It has one input: x, and three outputs: unlock, ready, and error. Following these rules:...
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1answer
82 views

Non-Wraping Up-Down Counter

I'm trying to implement a synchronous up-down counter in verilog with the following rules: Counter only changes on rising edge of clock When reset=1, count goes to 00, normal operation when reset=0 ...
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1answer
30 views

Change array to individual outputs

I'm trying to design a synchronous sequential circuit to implement a tail light controller for a 1965 Ford Thunderbird using verilog as shown below (included with the state diagram). I have the ...
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3answers
86 views

Assigning x in verilog

Assume there exists a 1 bit data output port and a 1 bit dataValid output port for a module. Is it OK to assign 1'dx to the data output when dataValid is assigned 0? Will this create synthesis issues? ...
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1answer
33 views

User defined data type in Verilog

I have always used VHDL and now need to use Verilog, so I'm learning Verilog. . . How can I define and use user-defined data type in Verilog for state machines. for eg : In VHDL I would write ...
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1answer
219 views

Displaying Characters In Verilog With VGA

I'm taking a intro to ECE course as a CS student and for a final project we are to design a game coded in Verilog using the VGA display on a DE1-SoC board. I decided to create a hangman game but I ...
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1answer
44 views

Generating Channel Select for Multichannel ADC

I am using a FPGA to control a 4-channel ADC (ADC084S101) to sample four different analog voltages. In order to tell the ADC which channel to sample next, there is a control register that can be ...
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1answer
74 views

Asynchronous Down Counter using D Flip Flops

After fixing my Up Counter, I'm having troubles writing structural verilog code for an Asynchronous 4-bit Down Counter using D Flip Flops. Here's the D Flip Flop code (which was tested and works): <...
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2answers
47 views

Is there some flag / pragma which can help me in detecting bogus variable names in a module definition?

[icarus verilog] Is there some flag / pragma which can help me in detecting bogus variable names in a module definition? Consider the following code fragment ... ...
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2answers
82 views

Increment operation in 24 bit counter

This is a 24 bit counter verilog program. What is the function of highlighted operation? Do we add 1 to the least significant bit? How can we know that the addition was done to the least significant ...
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1answer
86 views

HCI UART ? what's the difference with simple UART?

For now, I'm sending bytes from FPGA (verilog) to serial at 115200 bps. I would like to send at higher speed and connect to a bluetooth module (RN42). UART (SPP or HCI) and USB (HCI only) data ...