Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips.

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Design serial adder for 16 bit register using on full FA

I wrote a serial bit adder for a 15 bit width shift register and a full adder (positive edge trigger, asynchronous reset) I don't know where the error in this code is. This is the code: ...
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1answer
42 views

debouncing pushbuttons in verilog

I have two circuits which I have designed using verilog.One is Counter circuit and other is the debouncing pushbutton circuit.but I dont now how to instantiate a model so that the pushbutton circuit ...
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52 views

Keypad Scanner Verilog code problem with state machine and column input

I am developing a Keypad both in hardware and Verilog using a DE2 Cyclone II board. I made a keypad using buttons (switches) that follows this schematic: The scanner works by setting the Column ...
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1answer
49 views

Why does this Verilog code produce no output on my FPGA?

I am trying to learn Verilog on my own using the DE1-Soc and the Altera university program labs. I am on the very first lab and trying to make a 4 bit-wide two input multiplexer. I wrote this verilog ...
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1answer
51 views

Is it possible to drive a net from two processes when the assignments are conditionally mutually exclusive?

In my experience, driving a net from two separate processes (or always blocks) is a bad idea and will result in a multi-driver error in the tools. However, one of my acquaintances claims that if the ...
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21 views

Verilog multidimensional array

first of all, I already read a lot about multidimensional arrays in Verilog, but I was not able to find an answer. The following code is part of a example program using an oled display on my ...
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47 views

How to connect Xbee to FPGA using SPI?

I am trying to connect an Xbee to a FPGA using SPI. I found some code online to read in the MISO and convert to an 8bit output register. I have it working in the simulation but I cannot get the ...
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1answer
23 views

Sensitivity List in Verilog

for example, if there is a case when an output "clear" is sensitive for both the negedge and posedge, do we write it as: always @ (negedge clear, posedge clear)? Or is it impossible to have both ...
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19 views

Digilent EPP handshaking problem

I intend to use my Spartan-6 board as an interface between my mic (which produces I2S data) and PC for live recording. Since UART is too slow, i planned on using Digilent's parallel interface with ...
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23 views

synthesizable random number in verilog within a range [duplicate]

how to generate a random number generator in verilog without using $random. And which is in a particular range and which can be dumped in fpga.
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2answers
48 views

Reading ADC using Altera DE2 Board (Beginner)

Question: Would it be possible and feasible for a beginner to use Verilog HDL and an Altera DE2 board to read input from a weight sensor's HX711 ADC (see below), and if so: What kind of data am I ...
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1answer
45 views

Running UVM example on MODELSIM - ALTERA 10.1d

I want to compile and simulate this simple UVM example using Modelsim-Altera 10.1d tool. ...
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2answers
65 views

Using iSim to simulate 16-bit CLA schematic on Xilinx, all inputs and outputs on the waveform are 'X'. How can I debug?

I'm building a sixteen bit Carry Lookahead Adder for my EE class. I'm definitely a noob to all this so bear with me, however I've been googling for a WHILE and haven't found any answers. Here is the ...
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1answer
56 views

Verilog inital value for flip flop

I am trying to write verilog code that will set the initial value of the output of a positive-edge triggered flip-flop to 0. The behaviour of the flip-flop circuit is exactly what I want AFTER the ...
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1answer
45 views

sequence detector in verilog

I have the task of building a sequence detector Here's the code : ...
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4answers
63 views

Convert IEEE Double to Integer - Verilog

I want to convert the IEEE Double value computed in my code to Integer. E.g. I have computed: X = 64'hxxxxxxxxxxxxxxxx; Now i want to use it as index of an array as: some_array[X]; How can I do it? ...
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18 views

Convert IEEE Double to Integer - Verilog [duplicate]

I want to convert the IEEE Double value computed in my code to Integer. E.g. I have computed: X = 64'hxxxxxxxxxxxxxxxx; Now i want to use it as index of an array as: some_array[X]; How can I do it? ...
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1answer
42 views

Simulating IP core (i.e ALT_FP_DIV) on Altera modelSim gives “z” (high impedance) as output

I'm trying to simulate (functional Test) a project that contains both my own codes and some instances of Altera Floating Point IP Core generated using MegaWizard on ModelSim. All the instantiated IP ...
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20 views

how to use generate for multiple module instantiation in verilog

Please tell me the error. I'm using the following code and each time I get this error during compilation for the "generate" wordsize has already been defined ...
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87 views

What are some things that can be done in VHDL but not in verilog and vice versa?

VHDL and Verilog are quite similar but do not have the same features, there is certainly a massive overlap though. What are some things which are easier to do in VHDL but not so easy or even ...
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1answer
80 views

SystemC vs HDLs

I am currently involved in a university project to implementing a processor of an existing instruction set. The idea is that by the end of the project I should be able to synthesise this design and ...
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1answer
59 views

4 port 12 bit mux is consuming 48 macrocells!

I'm programming on the coolrunner II cpld. It is running out of resources so I decided to implement my own 4 port, 12 bit mux. After implementation I find that it's using over 40 macrocells. Any way ...
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1answer
48 views

Verilog, register values

For learning purposes, I am trying to implement a very simple processor in verilog. The idea is that every clock cycle the machine either fetches the next 4 instructions from memory (each instruction ...
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59 views

More elegant code for synchronous square wave generator in Verilog

I'm self studying with Chu's FPGA prototyping book. Exercise 4.7.1 asks for a programmable square wave generator: A programmable square-wave generator is a circuit that can generate a square wave ...
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1answer
51 views

Ring counter in verilog

I have the task of designing a ring counter in verilog using shift operator. Here is the code so far along with test bench : ...
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1answer
91 views

What does “+:” mean in Verilog?

When I was looking at someone's Verilog code, I found "+:" in Verilog. It looks like an arithmetic function but I'm not sure. I never seen before. Does anyone know this usage? Update: ...
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81 views

This state machine does not go into an initial state on start

This is my state machine code: ...
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4answers
309 views

What is the set in D FF?

I'm trying to implement a 3-bit counter using basic gates (AND, OR, XOR, NOT etc..) around 3 D-type flip-flops. The input is an increment signal that when set to 1 will allow the counter to increment ...
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1answer
40 views

Emulation of slideshow

I am doing emulation of slideshow of images in which i store pixel values in SRAM using processor and read data using VGA .It works fine when i store data in sram and read it through VGA seperately. ...
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2answers
70 views

Modelling current to remain in particular range for fixed simulation time

I am a novice in SystemVerilog. I wish to know how to model a 8-bit signal X to attain four levels for certain ranges of time. For example,let the legal values of X be from 40 to 80(40 < X < 80) ...
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85 views

D flip flop with asynchronous level triggered reset

Ref : Is making a D flip flop with asynchronous level triggered reset possible? My code : ...
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1answer
37 views

Resources for learning verilog

I have started learning verilog recently and i am finding it difficult to understand how should i approach it because i am doing it all by myself and not from any training institute. The problems i ...
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158 views

BCD to 7 segment display in verilog

I am trying to implement a BCD to seven segment display in verilog using modelsim as a simulator. When I am doing so I am getting this as my output: But when I am forcing the values I am getting the ...
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2answers
51 views

How to design a circuit that works on both negedge and posedge

I have a clock phase bit which decides on which clock edge the design must work. I cannot use an always block inside an if statement. Is it possible to use ...
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29 views

How to pass a signal from one module to another using dot operator in verilog

I have got a memory module which consists of a memory module memory(clk,rst,addr,data,wrt,rd); reg [7:0] mem [254:0]; I am using this memory module in the ...
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1answer
194 views

Clock divider circuit with flip D flip flop

I am using D flip flops in my clock divider circuit. I have started with one FF and moving up with the number of divisions I want to have in my clock. This is how I want my D ffs to work. Now I ...
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1answer
58 views

How can I calculate max, min frequency between FF to FF in RTL design?

I am trying to review regarding RTL design. The RTL design as follows --FF---Comb----FF----FF---- And each FF have same configure like this setup 1ns hold 1ns output 0.5ns Also, the ...
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1answer
86 views

Interfacing DDS with FPGA

I'm trying to use an FPGA (Altera Deo-Nano) to send data to a DDS (AD9910) using the parallel ports of the DDS. I am using the GPIO headers of the FPGA. I have only connected the parallel input pins ...
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43 views

Differential equation in verilog

I want to implement a simple differential equation in Veriloge (VHDL).Please, if any one could give me an idea how it is possible. I searched a lot but I could not find anything.
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1answer
54 views

Signals not showing in Vivado simulation

I have the below Verilog code and simulation where I want to view the signals and compare the clocks for each of them. ...
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2answers
57 views

Unsure if this asynchronous D-Flip-Flop Verilog code makes sense

This is my code for an async-reset-set D-flip-flop. I'm using quartus, and the module compiles, but there is no way to check if my logic is valid. I could use some outside opinions. The reset is ...
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1answer
31 views

Trouble understanding Verilog decoder logical left shift

This code is from asic-world: ...
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2answers
68 views

Code to add two 4bit numbers in verilog doesn't work

I have a code that adds two 4 bit numbers; unfortunately it is not working for every case even though the formulas are really simple and I don't find the problem... ...
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1answer
52 views

I can't get a meaningful output from a circuit in Thomas & Moorby's exercise 2.7

I'm working out the exercises in "The Verilog Hardware Description Language" to learn Verilog. I'm currently stuck in exercise 2.7, and since I couldn't find anything on the web about it I thought I'd ...
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1answer
91 views

Use Xilinx Primitive elements in Verilog inside ISE

I generated Verilog Post-Route simulation model of my original Verilog module, using Xilinx ISE. It will generate a Verilog module using LUT and fpga level primitives such as IBUF,X_LUT4, ... When ...
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1answer
29 views

What's the order of the array generated by Verilog? Syntax

What is the correct interpretation between these two lines: wire[2:0] w = SW[17:15] = {SW[17], SW[16], SW[15]} wire[2:0] w = SW[17:15] = {SW[15], SW[16], SW[17]} When I call w[0] will I get SW[15] ...
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1answer
103 views

How do for loops work in verilog? Why can't I achieve what I want?

This is my code for a simple 2-1 8 bit multiplexor, where SW[17] is my selector. If it is on, show Y = SW[15:8], if it is off, ...
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2answers
78 views

Help! Verilog loop! The following signal(s) form a combinatorial loop

I'm trying to complete an assignment using Verilog, the details aren't too important, except that it must be a combinatorial design. Unfortunately I'm running into what I assume is the hardware ...
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54 views

Extracting a sub array from an array of switches with Verilog?

I am working with a Cyclone board. A basic code to assign every switch to the red leds is: ...
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2answers
47 views

Verilog megawizard RAM not read

I used Quartus II Magawizard to ask for a two port RAM(one read and one write). The addresses are correct but the data out is always z. Can some one help me with this problem? I have stuck here for a ...