Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips.

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UART Transmitter in Verilog (using Basys 2 for hardware implementation)

regarding to UART transmitter, i use the transmitter verilog code provided at fpga4fun.com and it works greatly as hyperterminal displays the output correctly(using switches on board as data/input) ...
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11 views

Trouble understanding Verilog decoder logical left shift

This code is from asic-world: ...
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24 views

Code to add two 4bit numbers in verilog doesn't work

I have a code that adds two 4 bit numbers; unfortunately it is not working for every case even though the formulas are really simple and I don't find the problem... ...
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43 views

I can't get a meaningful output from a circuit in Thomas & Moorby's exercise 2.7

I'm working out the exercises in "The Verilog Hardware Description Language" to learn Verilog. I'm currently stuck in exercise 2.7, and since I couldn't find anything on the web about it I thought I'd ...
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29 views

Use Xilinx Primitive elements in Verilog inside ISE

I generated Verilog Post-Route simulation model of my original Verilog module, using Xilinx ISE. It will generate a Verilog module using LUT and fpga level primitives such as IBUF,X_LUT4, ... When ...
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26 views

What's the order of the array generated by Verilog? Syntax

What is the correct interpretation between these two lines: wire[2:0] w = SW[17:15] = {SW[17], SW[16], SW[15]} wire[2:0] w = SW[17:15] = {SW[15], SW[16], SW[17]} When I call w[0] will I get SW[15] ...
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80 views

How do for loops work in verilog? Why can't I achieve what I want?

This is my code for a simple 2-1 8 bit multiplexor, where SW[17] is my selector. If it is on, show Y = SW[15:8], if it is off, ...
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47 views

Help! Verilog loop! The following signal(s) form a combinatorial loop

I'm trying to complete an assignment using Verilog, the details aren't too important, except that it must be a combinatorial design. Unfortunately I'm running into what I assume is the hardware ...
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27 views

Extracting a sub array from an array of switches with Verilog?

I am working with a Cyclone board. A basic code to assign every switch to the red leds is: ...
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34 views

Verilog megawizard RAM not read

I used Quartus II Magawizard to ask for a two port RAM(one read and one write). The addresses are correct but the data out is always z. Can some one help me with this problem? I have stuck here for a ...
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1answer
45 views

Reading a serial data stream with Verilog

I'm using an FPGA to sample a serial data stream (happens to be PCM audio in this case). Basically, there are two signals: Bit clock: a basic clock signal (square wave) Data: the bit to be read is ...
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231 views

What is the purpose of pre-synthesis simulation?

I have used Verilog to develop RTL representations of synthesizable digital circuits, and have recently been using Verilator to run simulations of these. My understanding of Verilog semantics, ...
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104 views

Generate flip-flops using only combinational logic

Just for fun, I wanted to design and simulate D-type flip-flops using only combinational logic in Verilog (or SystemVerilog). I am using using Verilator for the simulation. My initial attempt, which ...
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28 views

how to compare each and every element with other element of two multi dimensional arrays in verilog?

I want to compare two multi dimensional arrays with each element of one array with the other array. What is the procedure to make it possible? ...
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71 views

Check for change in input

I have a problem checking for the change in input, that is when A changes value x changes state. where a is an N-bit input and "x" is a single bit out
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41 views

Verilog: Change a Certain Delay According to the Current Output

For Verilog 2005, when writing the test bench, is it possible to create a lookup table of delay values, and then assign a certain value in it to be the delay of some procedural block? For example: ...
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63 views

How to resolve this Syntax error

Am trying to code a top level module that would connect different modules to make an up/down counter that would display a hexadecimal character on a 7 segment LED on posedges; but every time I try to ...
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42 views

Verilog: Check, if a signal is 100 ticks active?

I have one input and one output. And I want to turn the output to 1, if the input was 100 ticks active (100 cycles). ...
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1answer
85 views

Shift Register Vs Multiplexer

I am not sure about an implementation. I've a multiplexer 8 input, 1 output and 3 select signal. One of these selects signal sequentialy acquires all value of a bit vector. Now I can choose 2 way. ...
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1answer
44 views

Switching tone on and off at 120 bpm not working

I am trying to make a design that toggles a sound at a rate of 120 BPM (once every .5 seconds), and I am using a 50 MHz clock. Here's the tone module: ...
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1answer
105 views

CLK net warning for stopwatch code on FPGA nexys2 board?

I'm coding for a stopwatch which displays 10ths of a second on the rightmost two displays and seconds on the left two displays. The synthesis completes properly but after I make the UCF file and try ...
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37 views

Verilog file handling

I tried to open a file ff.txt and write into it some random numbers say seven times. I used EDA playground website for it. Below is the link for that code as well as that code. ...
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1answer
29 views

Verilog only assigns first bit of a bus

I'm trying to assign a 12bit parallel bus to a 12bit register. I've reduced the problem to this literal assignment but as with the previous case, only the first bit is being written to anything when ...
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57 views

Blocking and Nonblocking statements in same procedural block

Code module block; reg a; reg b = 1'b0; reg c = 1'b1; initial begin c = b; a <= c; end endmodule I simulated the code fragment shown in ...
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34 views

Checking Full condition of RBR FIFO of LPC2148 UART

1)How do you check whether the RBR FIFO is full in case of LPC2148 UART? I know that the empty condition can be checked using Receiver Data Ready(RDR) of Line Status Register(LSR). But there is no way ...
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47 views

Switch DEBUG doesn't seem to be working in my code

Following code I tried on EDA playground with command appended with +define+DEBUG but DEBUG switch doesn't seem to be working. Its always block is sensitive to error and this variable is changing ...
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40 views

Same address for different registers in LPC2418 UART

I have a very basic question regarding LPC2418 UART. The UART has got different registers with the same addresses. So while loading the data from the test bench, will it not load into all the ...
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Verilog module to read/write a register

I would like to create a module that can change the value of a register passed to it (+/- 1) using an inout port. I wrote this: ...
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112 views

How do FPGA's implement sequential circuits?

I know they implement combinational circuits using LUTs, but LUTs don't have feedback, so I don't see how they can be used for sequential circuits. So how do FPGA's implement sequential circuits? ...
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82 views

quartus signaltap not accurate?

I am using Quartus SignalTap to debug my FPGA design: I always been persuaded SignalTap is not accurate !! This is what i found: I monitor the reset signal with SignalTap :Reset toggles around, ...
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64 views

Reconfiguration of FPGA in ML605 Board- THe ICAP IS NOT WORKING

The aim of my project is to load 3 bitstreams into the PROM; according to our requirement we load the 1or second or 3 bit file. PROBLEM FACING: THe problem is I'm unable to know whether the ICAP ...
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1answer
191 views

Verilog FIR filter using FPGA

I am implementing an FIR filter in Verilog, using the DE2 board. For some reason the output out of the speakers is full of static, although it does appear to filter out some frequencies. Here is the ...
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59 views

Function call isn't executed in verilog

Why function call to clogb2 is not being executed in the following code. I don't get any compilation errors but still parameter ...
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44 views

Timing/buffering issue with Digilent's EPP on Basys2?

I have a Digilent Basys2 FPGA, and I'm implementing the EPP interface described in http://www.digilentinc.com/Data/Products/ADEPT/DpimRef%20programmers%20manual.pdf. This allows a program called ...
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70 views

Functional and Timing accuracy of an RTL Model

I am sometimes really confused by the abusive use of jargon in EDA/VLSI design articles and books. With no precise definitions, its upto the reader to make interpretation which is very ambiguous and ...
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66 views

FPGA based theremin , is possible?

I remember a while ago , i saw some Digital based Theremins circuits from glasgow university... http://www.theremin.info/-/viewpub/tid/10/pid/65 would it be possible to make a theremin by using an ...
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(Solved) Clock code does not oscillate

Am new to HDL and I was given the following clock code as a part of a school project, but I can't seem to make it oscillate between 1 and 0 when I run a test bench or instantiate it from another ...
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Implementing Processor Core for Cache Module in Verilog

I have written a simulation module for a Direct Mapped Cache (consisting of data, tag, and valid rams and cache controller) in Verilog. I now want to implement a Processor Core/Driver (also in ...
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134 views

Text File tranfer between PC and Atlys board (FPGA)

I am new to FPGA. While doing calculations I found that I can not input number in real time to FPGA. My instructor told me to write my numbers (or data) in a text file on PC and tranfer it to FPGA in ...
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85 views

Why is seed value getting changed on its own in this code?

In the following code why is seed value getting altered each time it enters for loop? http://www.edaplayground.com/x/J8s ...
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77 views

Random Access Memory Modelling in Verilog

Is there a better/alternative way of modelling RAM Memory in Verilog other than declaring it as an array of registers? Most of the sources I referred to have memories coded in the following manner. ...
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Verilog-AMS model to Spectre CMI

I am trying to compile some Verilog-AMS models to Spectre CMI in order to use them in Spectre Simulator. I have tried using ADMS (http://ngspice.sourceforge.net/admshowto.html), but Cadence provide ...
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100 views

Building a framebuffer

I'm trying to build a framebuffer using an FPGA and an external memory. I have a soft core CPU running on the FPGA as well a small chunk of logic to output signals to an LCD. My goal is to have the ...
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86 views

$random in Verilog doesn't seem to be working

In Verilog, $random generates different random inputs but this doesn't seem to be working when I try. Each time I use $random ...
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93 views

Finding Critical Path of Combinational Logic

I have a combinational circuit and I would like to find its critical path in design compiler. Essentially, I want to find out by how much the combinational logic will reduce the maximum clock ...
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1answer
97 views

What does a double array do?

While looking through some Verilog code, I came across this: input [7:0] data [0:16] The code referred to this as memory. Could someone explain what it does? I ...
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1answer
98 views

How can I read in an image in Verilog?

I have a .mif image that I want to encrypt in Verilog. To do so, I need to read the image into the program and store it in an array. The image would be 160 by 120 and I would like to store it in an ...
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73 views

RAM memory modelling in Verilog

I am trying to model a 0.125GB RAM memory in Verilog using ModelSim of width 512 bit using memory chips of width 32 bit. So I have created a 32 * \$\2^{18}\$ memory array whose code is as follows: ...
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Best way to look for the rising edge of 2 signals using verilog?

I know how to look for an edge of a signal using verilog. Signal RESET Signal OS_OK Signal REBOOT Signal RESET will have a positive edge Signal OS_OK must have a positive edge within X ms or Signal ...