Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips.

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Verilog: Change a Certain Delay According to the Current Output

For Verilog 2005, when writing the test bench, is it possible to create a lookup table of delay values, and then assign a certain value in it to be the delay of some procedural block? For example: ...
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54 views

How to resolve this Syntax error

Am trying to code a top level module that would connect different modules to make an up/down counter that would display a hexadecimal character on a 7 segment LED on posedges; but every time I try to ...
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36 views

Verilog: Check, if a signal is 100 ticks active?

I have one input and one output. And I want to turn the output to 1, if the input was 100 ticks active (100 cycles). ...
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62 views

Shift Register Vs Multiplexer

I am not sure about an implementation. I've a multiplexer 8 input, 1 output and 3 select signal. One of these selects signal sequentialy acquires all value of a bit vector. Now I can choose 2 way. ...
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1answer
41 views

Switching tone on and off at 120 bpm not working

I am trying to make a design that toggles a sound at a rate of 120 BPM (once every .5 seconds), and I am using a 50 MHz clock. Here's the tone module: ...
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1answer
63 views

CLK net warning for stopwatch code on FPGA nexys2 board?

I'm coding for a stopwatch which displays 10ths of a second on the rightmost two displays and seconds on the left two displays. The synthesis completes properly but after I make the UCF file and try ...
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27 views

Verilog file handling

I tried to open a file ff.txt and write into it some random numbers say seven times. I used EDA playground website for it. Below is the link for that code as well as that code. ...
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21 views

Verilog only assigns first bit of a bus

I'm trying to assign a 12bit parallel bus to a 12bit register. I've reduced the problem to this literal assignment but as with the previous case, only the first bit is being written to anything when ...
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1answer
50 views

Blocking and Nonblocking statements in same procedural block

Code module block; reg a; reg b = 1'b0; reg c; initial begin c = b; a <= b; end endmodule I simulated the code fragment shown in figure ...
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27 views

Checking Full condition of RBR FIFO of LPC2148 UART

1)How do you check whether the RBR FIFO is full in case of LPC2148 UART? I know that the empty condition can be checked using Receiver Data Ready(RDR) of Line Status Register(LSR). But there is no way ...
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1answer
45 views

Switch DEBUG doesn't seem to be working in my code

Following code I tried on EDA playground with command appended with +define+DEBUG but DEBUG switch doesn't seem to be working. Its always block is sensitive to error and this variable is changing ...
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1answer
35 views

Same address for different registers in LPC2418 UART

I have a very basic question regarding LPC2418 UART. The UART has got different registers with the same addresses. So while loading the data from the test bench, will it not load into all the ...
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27 views

Verilog module to read/write a register

I would like to create a module that can change the value of a register passed to it (+/- 1) using an inout port. I wrote this: ...
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104 views

How do FPGA's implement sequential circuits?

I know they implement combinational circuits using LUTs, but LUTs don't have feedback, so I don't see how they can be used for sequential circuits. So how do FPGA's implement sequential circuits? ...
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75 views

quartus signaltap not accurate?

I am using Quartus SignalTap to debug my FPGA design: I always been persuaded SignalTap is not accurate !! This is what i found: I monitor the reset signal with SignalTap :Reset toggles around, ...
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1answer
48 views

Reconfiguration of FPGA in ML605 Board- THe ICAP IS NOT WORKING

The aim of my project is to load 3 bitstreams into the PROM; according to our requirement we load the 1or second or 3 bit file. PROBLEM FACING: THe problem is I'm unable to know whether the ICAP ...
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1answer
85 views

Verilog FIR filter using FPGA

I am implementing an FIR filter in Verilog, using the DE2 board. For some reason the output out of the speakers is full of static, although it does appear to filter out some frequencies. Here is the ...
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1answer
56 views

Function call isn't executed in verilog

Why function call to clogb2 is not being executed in the following code. I don't get any compilation errors but still parameter ...
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1answer
39 views

Timing/buffering issue with Digilent's EPP on Basys2?

I have a Digilent Basys2 FPGA, and I'm implementing the EPP interface described in http://www.digilentinc.com/Data/Products/ADEPT/DpimRef%20programmers%20manual.pdf. This allows a program called ...
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1answer
69 views

Functional and Timing accuracy of an RTL Model

I am sometimes really confused by the abusive use of jargon in EDA/VLSI design articles and books. With no precise definitions, its upto the reader to make interpretation which is very ambiguous and ...
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63 views

FPGA based theremin , is possible?

I remember a while ago , i saw some Digital based Theremins circuits from glasgow university... http://www.theremin.info/-/viewpub/tid/10/pid/65 would it be possible to make a theremin by using an ...
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46 views

(Solved) Clock code does not oscillate

Am new to HDL and I was given the following clock code as a part of a school project, but I can't seem to make it oscillate between 1 and 0 when I run a test bench or instantiate it from another ...
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47 views
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34 views

Implementing Processor Core for Cache Module in Verilog

I have written a simulation module for a Direct Mapped Cache (consisting of data, tag, and valid rams and cache controller) in Verilog. I now want to implement a Processor Core/Driver (also in ...
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96 views

Text File tranfer between PC and Atlys board (FPGA)

I am new to FPGA. While doing calculations I found that I can not input number in real time to FPGA. My instructor told me to write my numbers (or data) in a text file on PC and tranfer it to FPGA in ...
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77 views

Why is seed value getting changed on its own in this code?

In the following code why is seed value getting altered each time it enters for loop? http://www.edaplayground.com/x/J8s ...
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1answer
65 views

Random Access Memory Modelling in Verilog

Is there a better/alternative way of modelling RAM Memory in Verilog other than declaring it as an array of registers? Most of the sources I referred to have memories coded in the following manner. ...
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32 views

Verilog-AMS model to Spectre CMI

I am trying to compile some Verilog-AMS models to Spectre CMI in order to use them in Spectre Simulator. I have tried using ADMS (http://ngspice.sourceforge.net/admshowto.html), but Cadence provide ...
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89 views

Building a framebuffer

I'm trying to build a framebuffer using an FPGA and an external memory. I have a soft core CPU running on the FPGA as well a small chunk of logic to output signals to an LCD. My goal is to have the ...
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79 views

$random in Verilog doesn't seem to be working

In Verilog, $random generates different random inputs but this doesn't seem to be working when I try. Each time I use $random ...
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1answer
83 views

Finding Critical Path of Combinational Logic

I have a combinational circuit and I would like to find its critical path in design compiler. Essentially, I want to find out by how much the combinational logic will reduce the maximum clock ...
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1answer
95 views

What does a double array do?

While looking through some Verilog code, I came across this: input [7:0] data [0:16] The code referred to this as memory. Could someone explain what it does? I ...
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1answer
87 views

How can I read in an image in Verilog?

I have a .mif image that I want to encrypt in Verilog. To do so, I need to read the image into the program and store it in an array. The image would be 160 by 120 and I would like to store it in an ...
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1answer
62 views

RAM memory modelling in Verilog

I am trying to model a 0.125GB RAM memory in Verilog using ModelSim of width 512 bit using memory chips of width 32 bit. So I have created a 32 * \$\2^{18}\$ memory array whose code is as follows: ...
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Best way to look for the rising edge of 2 signals using verilog?

I know how to look for an edge of a signal using verilog. Signal RESET Signal OS_OK Signal REBOOT Signal RESET will have a positive edge Signal OS_OK must have a positive edge within X ms or Signal ...
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What is the difference between testing and verification?

Every textbook I've seen makes a big deal of the fact that testing and verification are two different concepts. Yet none of them provides a clear (or clear enough to me, at last) distinction. To ...
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38 views

Accepting real numbers as input in Verilog

I am designing a double precision floating point multiplier in Verilog. It accepts two real numbers in the decimal form (e.g. 2.334 and -89.5) from the user, converts them into the standard binary ...
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58 views

Structural D flip flop in Verilog

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282 views

Generate a 100 Hz Clock from a 50 MHz Clock in Verilog

I have a DE0 board with a 50 Mhz clock that am I trying to to bring down to 100 Hz in Verilog. Could anyone help me with the code to do this?
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21 views

why modelsim error is failing?

I have a project that contains 2 modules, one of them in test-bench, but when running them in ModelSim I'm getting this error: vsim +pulse_e/20 -gui work.Testbench vsim Start time: 18:08:42 on Nov ...
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46 views

Using explicit registers in RTL designs

Is it a good practice to use explicit register IPs in RTL designs? For instance, having separate IPs for each type of register and instantiating them in the design instead of coding them on-the-fly. ...
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28 views

Modelsim is not able to force some verilog signals

I have a verilog module that I must force some signals, however, if the signal has multiple bits and it is an escaped name (need to have a space after the signal) this is not possible because Modelsim ...
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3answers
85 views

Does it take long to implement RSA in hardware?

I just finished my first Digital Hardware course. We covered combinational circuits, sequential circuits and FSMs. We now need to create a final design project. We have 2 weeks to do so and we work ...
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1answer
37 views

Does modelsim support shift right arithmetic in verilog?

I am using ModelSim PE Student Edition, and I am trying to write a module which shifts right arithmetic. After searching online, and consulting a Verilog textbook, I found to shift right arithmetic I ...
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1answer
57 views

Verilog Down Counter Logic Implementation

I'm trying to write logic for storing trigger data. For example, I'm using a 3-bit counter as an address generator to store data samples. When I have a trigger event, I want to store the 4 data ...
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458 views

What would make me choose Verilog or VHDL over schematic design on CPLDs or FPGAs?

I have absolutely no background in programmable logic, I use mostly microcontrollers in my projects but recently I needed to work with video and the microcontroller is just too slow for what I needed ...
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I need help with verilog code, I am in trouble?

I am basically setting different control signals for the ALU to perform operations in verilog. But I have tried all possible ways of writing what I want but in vain, can you help me out. How should I ...
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39 views

How should this code look like in verilog?

I am designing an ALU to add at state 000, I have to assign control signals for a mux, carry in, and operands so that it works. so, i wrote an if statement in the controller module, and the TA told me ...
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108 views

How to give clock on xilinx spartan 6?

I am trying to run a counter on Digilent Atlys Spartan 6 xc6slx45 development kit, which changes counts on clock edge. I am new user to Verilog, so I don't know how to give clock to my program from ...
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What CPUs use a skewed associative cache?

What CPUs use a skewed associative cache? I see several people imply that, with roughly the same hardware, a skewed-associative cache often has better performance than a traditional set-associative ...