Tagged Questions

Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips.

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(Solved) Clock code does not oscillate

Am new to HDL and I was given the following clock code as a part of a school project, but I can't seem to make it oscillate between 1 and 0 when I run a test bench or instantiate it from another ...
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1answer
36 views
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12 views

Implementing Processor Core for Cache Module in Verilog

I have written a simulation module for a Direct Mapped Cache (consisting of data, tag, and valid rams and cache controller) in Verilog. I now want to implement a Processor Core/Driver (also in ...
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2answers
59 views

Text File tranfer between PC and Atlys board (FPGA)

I am new to FPGA. While doing calculations I found that I can not input number in real time to FPGA. My instructor told me to write my numbers (or data) in a text file on PC and tranfer it to FPGA in ...
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1answer
55 views

Why is seed value getting changed on its own in this code?

In the following code why is seed value getting altered each time it enters for loop? http://www.edaplayground.com/x/J8s ...
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1answer
48 views

Random Access Memory Modelling in Verilog

Is there a better/alternative way of modelling RAM Memory in Verilog other than declaring it as an array of registers? Most of the sources I referred to have memories coded in the following manner. ...
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16 views

Verilog-AMS model to Spectre CMI

I am trying to compile some Verilog-AMS models to Spectre CMI in order to use them in Spectre Simulator. I have tried using ADMS (http://ngspice.sourceforge.net/admshowto.html), but Cadence provide ...
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2answers
78 views

Building a framebuffer

I'm trying to build a framebuffer using an FPGA and an external memory. I have a soft core CPU running on the FPGA as well a small chunk of logic to output signals to an LCD. My goal is to have the ...
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2answers
60 views

$random in Verilog doesn't seem to be working

In Verilog, $random generates different random inputs but this doesn't seem to be working when I try. Each time I use $random ...
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1answer
71 views

Finding Critical Path of Combinational Logic

I have a combinational circuit and I would like to find its critical path in design compiler. Essentially, I want to find out by how much the combinational logic will reduce the maximum clock ...
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1answer
48 views

What does a double array do?

While looking through some Verilog code, I came across this: input [7:0] data [0:16] The code referred to this as memory. Could someone explain what it does? I ...
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1answer
51 views

How can I read in an image in Verilog?

I have a .mif image that I want to encrypt in Verilog. To do so, I need to read the image into the program and store it in an array. The image would be 160 by 120 and I would like to store it in an ...
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1answer
48 views

RAM memory modelling in Verilog

I am trying to model a 0.125GB RAM memory in Verilog using ModelSim of width 512 bit using memory chips of width 32 bit. So I have created a 32 * \$\2^{18}\$ memory array whose code is as follows: ...
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32 views

Best way to look for the rising edge of 2 signals using verilog?

I know how to look for an edge of a signal using verilog. Signal RESET Signal OS_OK Signal REBOOT Signal RESET will have a positive edge Signal OS_OK must have a positive edge within X ms or Signal ...
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6answers
637 views

What is the difference between testing and verification?

Every textbook I've seen makes a big deal of the fact that testing and verification are two different concepts. Yet none of them provides a clear (or clear enough to me, at last) distinction. To ...
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31 views

Accepting real numbers as input in Verilog

I am designing a double precision floating point multiplier in Verilog. It accepts two real numbers in the decimal form (e.g. 2.334 and -89.5) from the user, converts them into the standard binary ...
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2answers
49 views

Structural D flip flop in Verilog

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1answer
163 views

Generate a 100 Hz Clock from a 50 MHz Clock in Verilog

I have a DE0 board with a 50 Mhz clock that am I trying to to bring down to 100 Hz in Verilog. Could anyone help me with the code to do this?
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52 views

why all the variables are 'x' during the simulation

I'm trying to simulate this module, but during the simulation all the variables 'x's. why ? this is the module and the test-bench: ...
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27 views

Verilog code - compiles fine, but simulation does not run

I have had some fairly good experiences with structural modelling in Verilog, but I barely have any with other modelling methods. So, kindly help me out. The code compiles fine, but when simulating it ...
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21 views

why modelsim error is failing?

I have a project that contains 2 modules, one of them in test-bench, but when running them in ModelSim I'm getting this error: vsim +pulse_e/20 -gui work.Testbench vsim Start time: 18:08:42 on Nov ...
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44 views

Using explicit registers in RTL designs

Is it a good practice to use explicit register IPs in RTL designs? For instance, having separate IPs for each type of register and instantiating them in the design instead of coding them on-the-fly. ...
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0answers
20 views

Modelsim is not able to force some verilog signals

I have a verilog module that I must force some signals, however, if the signal has multiple bits and it is an escaped name (need to have a space after the signal) this is not possible because Modelsim ...
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3answers
77 views

Does it take long to implement RSA in hardware?

I just finished my first Digital Hardware course. We covered combinational circuits, sequential circuits and FSMs. We now need to create a final design project. We have 2 weeks to do so and we work ...
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1answer
33 views

Does modelsim support shift right arithmetic in verilog?

I am using ModelSim PE Student Edition, and I am trying to write a module which shifts right arithmetic. After searching online, and consulting a Verilog textbook, I found to shift right arithmetic I ...
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1answer
45 views

Verilog Down Counter Logic Implementation

I'm trying to write logic for storing trigger data. For example, I'm using a 3-bit counter as an address generator to store data samples. When I have a trigger event, I want to store the 4 data ...
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3answers
420 views

What would make me choose Verilog or VHDL over schematic design on CPLDs or FPGAs?

I have absolutely no background in programmable logic, I use mostly microcontrollers in my projects but recently I needed to work with video and the microcontroller is just too slow for what I needed ...
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2answers
74 views

I need help with verilog code, I am in trouble?

I am basically setting different control signals for the ALU to perform operations in verilog. But I have tried all possible ways of writing what I want but in vain, can you help me out. How should I ...
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1answer
37 views

How should this code look like in verilog?

I am designing an ALU to add at state 000, I have to assign control signals for a mux, carry in, and operands so that it works. so, i wrote an if statement in the controller module, and the TA told me ...
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2answers
57 views

How to give clock on xilinx spartan 6?

I am trying to run a counter on Digilent Atlys Spartan 6 xc6slx45 development kit, which changes counts on clock edge. I am new user to Verilog, so I don't know how to give clock to my program from ...
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47 views

What CPUs use a skewed associative cache?

What CPUs use a skewed associative cache? I see several people imply that, with roughly the same hardware, a skewed-associative cache often has better performance than a traditional set-associative ...
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1answer
92 views

Solid color display on VGA not working

I'm trying to get VGA working on my Altera DE0 board using Verilog, but haven't had much luck. It has the same pins as a normal VGA interface except red, green, and blue are all 4 bits each. Here is ...
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3answers
74 views

using C libraries inside verilog

I'm implementing a radio in Verilog. the time taken for bit reversal while computing the FFT is more. it is almost equal to a symbol time (OFDM system). Can I use a FFT library in C, which can be ...
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1answer
48 views

Blocking/Nonblocking with Delay

I am now confused by one piece of Verilog Codee, its kind of testing the blocking or non-blocking assignment features that combination with Delay model. ...
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2answers
109 views

Efficient use of space in FPGA

Background and clarifications: I've never developed/written a single piece of hardware before, but I'm currently using Verilog to develop a huge project for a FPGA as my final graduation project. ...
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2answers
106 views

Difference between >> and >>> in verilog?

What is the difference between >> and >>> in verilog/system verilog? I know that ...
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0answers
18 views

Difference between >> and >>> [duplicate]

What's the difference between >> and >>> in Verilog/SystemVerilog? I know that ...
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1answer
55 views

Verilog: sampling data in both posedge and negedge of the clock

I have a serial input stream which has left data in posedge of the clock, and right data in negedge of the clock. I would like to synchronize and bring them to the posedge of the same clock. I could ...
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3answers
822 views

What's the motivation in using Verilog or VHDL over C?

I come from a programming background and not messed around too much with hardware or firmware (at most a bit electronics and Arduino). What is the motivation in using hardware description languages ...
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1answer
43 views

Destination address of 82C37A DMA Controller

How do I select the destination address for the 82C37A DMA controller? I have gone through all the material on the web and they say that the Base Address and Current Address register contains the ...
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3answers
60 views

How is procedural code converted into a circuit?

With non-procedural code, the digital circuit the code represents is relatively obvious. However with procedural code, it's hard/impossible to see how it translates into a circuit. The only method I ...
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1answer
82 views

D flip flop simulation: which simulation output is right?

I have always wondered, what is the right solution to the D flip flop when the input changes right at the rising edge of the clock? I have found two solutions of these online but have no clue which is ...
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3answers
200 views

Verilog always block w/o posedge or negedge

I have a basic Verilog block that I wrote to trigger on any change in the signal. always @ (trigger) begin data_out <= data_in; end I expected this to ...
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20 views

Disable display in Synopsys VCS

I am currently simulating this large piece of verilog that is full of $display commands for debugging. I believe this is making simulation slower so I want to get rid of most of those. Is there a way ...
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0answers
91 views

Vivado optimizing away my pins

I'm fighting Vivado over what seems like a fairly stupid issue to me. I wrote some Verilog code in ISE (and simulated it). I generated a bitstream in ISE and downloaded it onto the board via impact, ...
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2answers
65 views
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1answer
123 views

What is wrong with following Verilog code where I am trying to pass a one-dimensional array?

What is wrong with following Verilog code where I am trying to pass a one-dimensional array? ...
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1answer
129 views

FPGA outputs are always high with basic and/or program

So I am just getting started developing with an Altera Cyclone II EP265 mini board, and I am having some trouble getting a program that outputs the "and" and "or" of three inputs working. The full ...
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1answer
45 views

Verilog: How to keep process reacting only to clk and reset?

I have some Verilog code that simulates correctly. I decided to synthesize it, and I see these warnings that make me uneasy: ...