Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips.

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FPGA to C Variable Transfer [on hold]

Is there a way to actively send data to a computer program written in C in order to utilize that data within the program?
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29 views

Convert IEEE Double to Integer - Verilog

I want to convert the IEEE Double value computed in my code to Integer. E.g. I have computed: X = 64'hxxxxxxxxxxxxxxxx; Now i want to use it as index of an array as: some_array[X]; How can I do it? ...
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Sexism in hardware engineering [on hold]

Documentation about sexism in the STEM field (Science, Technology, Engineering and Mathematics) is largely documented and readily available through Google. Furthermore, sexism specific to IT, ...
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14 views

Simulating IP core (i.e ALT_FP_DIV) on Altera modelSim gives “z” (high impedance) as output

I'm trying to simulate (functional Test) a project that contains both my own codes and some instances of Altera Floating Point IP Core generated using MegaWizard on ModelSim. All the instantiated IP ...
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11 views

how to use generate for multiple module instantiation in verilog

Please tell me the error. I'm using the following code and each time I get this error during compilation for the "generate" wordsize has already been defined ...
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1answer
54 views

What are some things that can be done in VHDL but not in verilog and vice versa?

VHDL and Verilog are quite similar but do not have the same features, there is certainly a massive overlap though. What are some things which are easier to do in VHDL but not so easy or even ...
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58 views

SystemC vs HDLs

I am currently involved in a university project to implementing a processor of an existing instruction set. The idea is that by the end of the project I should be able to synthesise this design and ...
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1answer
47 views

4 port 12 bit mux is consuming 48 macrocells!

I'm programming on the coolrunner II cpld. It is running out of resources so I decided to implement my own 4 port, 12 bit mux. After implementation I find that it's using over 40 macrocells. Any way ...
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43 views

Verilog, register values

For learning purposes, I am trying to implement a very simple processor in verilog. The idea is that every clock cycle the machine either fetches the next 4 instructions from memory (each instruction ...
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42 views

More elegant code for synchronous square wave generator in Verilog

I'm self studying with Chu's FPGA prototyping book. Exercise 4.7.1 asks for a programmable square wave generator: A programmable square-wave generator is a circuit that can generate a square wave ...
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1answer
29 views

Ring counter in verilog

I have the task of designing a ring counter in verilog using shift operator. Here is the code so far along with test bench : ...
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1answer
85 views

What does “+:” mean in Verilog?

When I was looking at someone's Verilog code, I found "+:" in Verilog. It looks like an arithmetic function but I'm not sure. I never seen before. Does anyone know this usage? Update: ...
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75 views

This state machine does not go into an initial state on start

This is my state machine code: ...
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4answers
302 views

What is the set in D FF?

I'm trying to implement a 3-bit counter using basic gates (AND, OR, XOR, NOT etc..) around 3 D-type flip-flops. The input is an increment signal that when set to 1 will allow the counter to increment ...
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39 views

Emulation of slideshow

I am doing emulation of slideshow of images in which i store pixel values in SRAM using processor and read data using VGA .It works fine when i store data in sram and read it through VGA seperately. ...
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2answers
70 views

Modelling current to remain in particular range for fixed simulation time

I am a novice in SystemVerilog. I wish to know how to model a 8-bit signal X to attain four levels for certain ranges of time. For example,let the legal values of X be from 40 to 80(40 < X < 80) ...
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1answer
56 views

D flip flop with asynchronous level triggered reset

Ref : Is making a D flip flop with asynchronous level triggered reset possible? My code : ...
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1answer
31 views

Resources for learning verilog

I have started learning verilog recently and i am finding it difficult to understand how should i approach it because i am doing it all by myself and not from any training institute. The problems i ...
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63 views

BCD to 7 segment display in verilog

I am trying to implement a BCD to seven segment display in verilog using modelsim as a simulator. When I am doing so I am getting this as my output: But when I am forcing the values I am getting the ...
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2answers
47 views

How to design a circuit that works on both negedge and posedge

I have a clock phase bit which decides on which clock edge the design must work. I cannot use an always block inside an if statement. Is it possible to use ...
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How to pass a signal from one module to another using dot operator in verilog

I have got a memory module which consists of a memory module memory(clk,rst,addr,data,wrt,rd); reg [7:0] mem [254:0]; I am using this memory module in the ...
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1answer
70 views

Clock divider circuit with flip D flip flop

I am using D flip flops in my clock divider circuit. I have started with one FF and moving up with the number of divisions I want to have in my clock. This is how I want my D ffs to work. Now I ...
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1answer
45 views

How can I calculate max, min frequency between FF to FF in RTL design?

I am trying to review regarding RTL design. The RTL design as follows --FF---Comb----FF----FF---- And each FF have same configure like this setup 1ns hold 1ns output 0.5ns Also, the ...
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1answer
66 views

Interfacing DDS with FPGA

I'm trying to use an FPGA (Altera Deo-Nano) to send data to a DDS (AD9910) using the parallel ports of the DDS. I am using the GPIO headers of the FPGA. I have only connected the parallel input pins ...
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38 views

Differential equation in verilog

I want to implement a simple differential equation in Veriloge (VHDL).Please, if any one could give me an idea how it is possible. I searched a lot but I could not find anything.
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1answer
41 views

Signals not showing in Vivado simulation

I have the below Verilog code and simulation where I want to view the signals and compare the clocks for each of them. ...
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2answers
46 views

Unsure if this asynchronous D-Flip-Flop Verilog code makes sense

This is my code for an async-reset-set D-flip-flop. I'm using quartus, and the module compiles, but there is no way to check if my logic is valid. I could use some outside opinions. The reset is ...
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28 views

Trouble understanding Verilog decoder logical left shift

This code is from asic-world: ...
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51 views

Code to add two 4bit numbers in verilog doesn't work

I have a code that adds two 4 bit numbers; unfortunately it is not working for every case even though the formulas are really simple and I don't find the problem... ...
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1answer
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I can't get a meaningful output from a circuit in Thomas & Moorby's exercise 2.7

I'm working out the exercises in "The Verilog Hardware Description Language" to learn Verilog. I'm currently stuck in exercise 2.7, and since I couldn't find anything on the web about it I thought I'd ...
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1answer
59 views

Use Xilinx Primitive elements in Verilog inside ISE

I generated Verilog Post-Route simulation model of my original Verilog module, using Xilinx ISE. It will generate a Verilog module using LUT and fpga level primitives such as IBUF,X_LUT4, ... When ...
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29 views

What's the order of the array generated by Verilog? Syntax

What is the correct interpretation between these two lines: wire[2:0] w = SW[17:15] = {SW[17], SW[16], SW[15]} wire[2:0] w = SW[17:15] = {SW[15], SW[16], SW[17]} When I call w[0] will I get SW[15] ...
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1answer
92 views

How do for loops work in verilog? Why can't I achieve what I want?

This is my code for a simple 2-1 8 bit multiplexor, where SW[17] is my selector. If it is on, show Y = SW[15:8], if it is off, ...
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66 views

Help! Verilog loop! The following signal(s) form a combinatorial loop

I'm trying to complete an assignment using Verilog, the details aren't too important, except that it must be a combinatorial design. Unfortunately I'm running into what I assume is the hardware ...
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Extracting a sub array from an array of switches with Verilog?

I am working with a Cyclone board. A basic code to assign every switch to the red leds is: ...
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41 views

Verilog megawizard RAM not read

I used Quartus II Magawizard to ask for a two port RAM(one read and one write). The addresses are correct but the data out is always z. Can some one help me with this problem? I have stuck here for a ...
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1answer
58 views

Reading a serial data stream with Verilog

I'm using an FPGA to sample a serial data stream (happens to be PCM audio in this case). Basically, there are two signals: Bit clock: a basic clock signal (square wave) Data: the bit to be read is ...
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4answers
258 views

What is the purpose of pre-synthesis simulation?

I have used Verilog to develop RTL representations of synthesizable digital circuits, and have recently been using Verilator to run simulations of these. My understanding of Verilog semantics, ...
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2answers
133 views

Generate flip-flops using only combinational logic

Just for fun, I wanted to design and simulate D-type flip-flops using only combinational logic in Verilog (or SystemVerilog). I am using using Verilator for the simulation. My initial attempt, which ...
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1answer
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how to compare each and every element with other element of two multi dimensional arrays in verilog?

I want to compare two multi dimensional arrays with each element of one array with the other array. What is the procedure to make it possible? ...
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73 views

Check for change in input

I have a problem checking for the change in input, that is when A changes value x changes state. where a is an N-bit input and "x" is a single bit out
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Verilog: Change a Certain Delay According to the Current Output

For Verilog 2005, when writing the test bench, is it possible to create a lookup table of delay values, and then assign a certain value in it to be the delay of some procedural block? For example: ...
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65 views

How to resolve this Syntax error

Am trying to code a top level module that would connect different modules to make an up/down counter that would display a hexadecimal character on a 7 segment LED on posedges; but every time I try to ...
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2answers
44 views

Verilog: Check, if a signal is 100 ticks active?

I have one input and one output. And I want to turn the output to 1, if the input was 100 ticks active (100 cycles). ...
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1answer
96 views

Shift Register Vs Multiplexer

I am not sure about an implementation. I've a multiplexer 8 input, 1 output and 3 select signal. One of these selects signal sequentialy acquires all value of a bit vector. Now I can choose 2 way. ...
2
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1answer
45 views

Switching tone on and off at 120 bpm not working

I am trying to make a design that toggles a sound at a rate of 120 BPM (once every .5 seconds), and I am using a 50 MHz clock. Here's the tone module: ...
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1answer
154 views

CLK net warning for stopwatch code on FPGA nexys2 board?

I'm coding for a stopwatch which displays 10ths of a second on the rightmost two displays and seconds on the left two displays. The synthesis completes properly but after I make the UCF file and try ...
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2answers
41 views

Verilog file handling

I tried to open a file ff.txt and write into it some random numbers say seven times. I used EDA playground website for it. Below is the link for that code as well as that code. ...
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1answer
38 views

Verilog only assigns first bit of a bus

I'm trying to assign a 12bit parallel bus to a 12bit register. I've reduced the problem to this literal assignment but as with the previous case, only the first bit is being written to anything when ...
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61 views

Blocking and Nonblocking statements in same procedural block

Code module block; reg a; reg b = 1'b0; reg c = 1'b1; initial begin c = b; a <= c; end endmodule I simulated the code fragment shown in ...