Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips.

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Can a barrel shifter be done combinatorially?

I was told that 66b/64b encoding in 10Gb Ethernet (10GBASE-R) requires a one-cycle barrel stage, which adds a necessary one cycle to the theoretical terminal latency. The Wikipedia page on barrel ...
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29 views

Difference between HVL and HDL

Hardware description language describes our circuit but what does Hardware Verification Language do? How does it verify the design?
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17 views

Altera Quartus II: FPGA .sof file corrupt all the time

Problem Background: I have a synthesized design using Quartus II 14.0 Output file its in .sof format, to program an Altera Cyclone It works correctly on my computer I can load the file to the FPGA ...
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49 views

Single Die Roll Counter Wrap Around Nested Ternary Conditional

I have to emulate a single die roll, therefore it needs to wrap back to one at 6. `D1 and `D6 correspond to my 3-bit state ...
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23 views

Verilog Concatenation Setting LED'sin casex

If I have a casex statement and I have something such as {`idle, `left}: {next, LED} = {`state1 ,`turn1liteON }; and LED corresponds to LEDR[7:0] and ...
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66 views

How to correct verilog code of given circuit?

I wrote a code : ...
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42 views

fpga verilog dual access

I need to write to a register from 2 sources.. in this case, a pci host and a microcontroller. The 2 will never access the register at the same time (basically once the PCI is done , it hands it ...
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35 views

Is the simulated clock cycle latency through an entity accurate?

If I write an entity that takes 10 clock cycles to produce output from input, is it safe to assume that this is the case when implemented in hw, or are there other factors to consider? Does the ...
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60 views

Verilog: is connection without wires possible?

I am sorry to ask this question, which I believe is very basic, but I cannot find an answer. The following example clearly works. But I would like to omit the declaration of the wires ay and by. ...
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28 views

Quartus II: Suppress warnings by Verilog module

In my FPGA project I use the Quartus II PCIe megafunction. The number of warning messages this Altera library module produces baffles me. Is there a way to have Quartus II suppress all the warnings ...
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52 views

Understanding Combinational Feedback Loops

1) Please give me a simple example of a verilog code that results in combo feedback loop. 2) Why are these feedback loops undesired in your design? ...
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494 views

Why cannot delays be synthesized in Verilog?

I have always read that delays declared in RTL code can never be synthesized. They are meant only for simulation purpose and modern synthesis tools will just ignore delays declarations in the code. ...
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27 views

Send signal from one output connected to multiple modules

Hi I am learning verilog and I am trying to find an answer if I have an output of type reg in a main module connected to the inputs of multiple modules, how in verilog would I specify which module I ...
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51 views

Routing errors when trying to implement PLL onto Spartan-6 FPGA board

I am attempting to synthesize and implement the reference design that is linked to in the 'Reference Design Additional Information' section of the following document. I get the following error ...
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22 views

Synthing HDL down to waveform-testable format using Synopsys

I've worked a bit with the Quartus II toolset to create small systems that I could construct in Verilog and then test by applying a waveform. Then I could check the output against a Golden Waveform to ...
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65 views

How to simulate PCIe to debug my FPGA endpoint

I'm working on an FPGA controller connected through PCIe. The only way I can debug the hardware is using chipscope. So I execute commands through my driver and check out the signals from the FPGA. ...
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20 views

contribution statements in verilog-A

How does assignment through a contribution statement (statements with <+ operator) works in verilog-a? I read in the language reference manual of verilog-a the following about the branch ...
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44 views

How to convert output of 4digit BCD adder to hexadecimal

The output of 4digit BCD adder is "Cout" and "S[15:0]". {Cout,S} is the output of BCD adder. How can i convert this into Hexadecimal.I have tried the following method but its not working ...
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1answer
34 views

Verilog to spice using v2s- specificing the port order in the command v2s

I was trying to convert from verilog netlist into a spice netlist using the option v2s. Can I specify the pattern in which the ports will be arranged in my ...
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55 views

How to design a two-stage synchronizer with a clock divider in Verilog?

I have a very fast clock called CLOCK_50 which I would like to slow down through the use of a clock divider. The output is ...
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32-way Mux Produces Horrible Timing Problems

I'm coding a 32 way mux in verilog. The input is a counter which counts from 0 to 31, incrementing each clock cycle. Each counter value selects a different slice of a vector as an output. In my ...
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73 views

To Remove Debounce from MicroJoystick installed on LogicStart MegaWing (FPGA) and read input correctly

I am working on an FPGA board and coding in Verilog. I am trying to use the MicroJoystick installed on LogicStartMegaWing, the shield with Papilio-One 500k (my FPGA board). I have to do simple tasks ...
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46 views

How do I duplicate data from a text file into registers?

Let's say I have text file containing 8 bits of data on each line, up to 128 lines. The design should be synthesizable and the text file is a placeholder for some buffer. The contents of that buffer ...
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164 views

3D Rotation Using Fixed Point Arithmetic - Rotating Object is Deforming (and Shrinking)

I have an FPGA board (Virtex 5) for which I have created a Wireframe GPU with the ability to rotate a sample object using a 3 Axis Trackball. Additionally, I have connected the board to a PC Monitor. ...
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52 views

Why does this Verilog replicator statement produce a 64 bit long wire?

I'm attempting to capture the carry out of the addition of two N bit numbers with a carry in. My code is: ...
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259 views

My serial receiver verilog implementation does not act as expected

I have coded my own implementation of a serial receiver. It will work for incoming data at a baud rate of 115200. Here's my code: ...
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1answer
77 views

Computational complexity of current netlist matching algorithms

I understand that the problem of matching two netlists could be reduced to the graph isomorphism problem which is NP-intermediate. Apart from that what are the complexity results of some of the ...
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171 views

Using Digital Clock Manager with Verilog to generate 25Mhz clock from 32Mhz internal clock

I am writing a VGA driver program in Verilog on a Spartan 3E (FPGA board Papilio one- 500k bundled with LogicStart MegaWIng). The frequency of the internal clock of Spartan 3E is 32MHz. But I need to ...
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47 views

Verilog code synthesis error

I'm having problem with my verilog code when I synthesize it. It shows multiple drivers error. I think may be it's because of multiple always blocks I'm using in it. So how can I fix it!!? Here it is: ...
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109 views

Input pins in top module unconnected

I have a problem connecting different modules in a top module. I want to do a very simple PWM using a counter and a comparator. Counter: ...
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1answer
100 views

Synthesis of a multiplier design

I have written a verilog code for a multiplier which gives correct results after simulation. But, the code generated after synthesis of the above mentioned code does not give correct results. In fact, ...
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Learning FPGA Design (Books, Resources, VHDL/Verilog) [closed]

I used to use FPGA's back in college and I really enjoyed it. Years have passed though and I haven't had much time to play with it since then. I have realized I have forgotten some stuff (quite a bit ...
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42 views

how to show the internal wire wave in verilog output?

Suppose I have a code written as ...
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51 views

Is it fine to have different number of input/output port in module and module instant in verilog?

For example if i am going to model T flip flop using D flip flop. I am not writing the whole code of T flip flop as here it is not related to my query. ...
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73 views

Digital Clock Circuit With A Buzzer

I developed a digital clock circuit that simply resembles the function of a stopwatch. The circuit works fine, but I decided to add an extra functionality: A buzz is produced each hour, but I seem to ...
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80 views

Using '$display' in Xilinx(verilog)

I am trying to write a testbench for a 16-bit RISC processor using verilog in Xilinx. I have the following modules: - TOP -datapath -instruction_fetch -program_counter ...
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1answer
51 views

Please explain the following integer constant used in verilog

The integer constant in verilog specified as "size base value". 8'h81 : I think in this 8 is size h(hexadecimal) 81(value). but I am confused, it has 8 size. 81 ...
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1answer
106 views

How does this direct digital synthesis accumulator work?

So, I grabbed some code online and morphed it to work with my DE2-115 board, and now I need some help understanding exactly how it works. ...
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70 views

assign values to all columns in 2D array in one statement

I would like to assign value to an array. The array is 2 dimensional it has 16 rows and 16 col. Each element is 2 bits wide. I would like to initialize each row of an array like so: Initialize the ...
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43 views

Verilog “Tick” Generation; Concern over hold time?

In Pong Chu's "FPGA Prototyping by Verilog Examples" he recommends using a periodic enable "tick" to divide the clock while maintaining a synchronous system (to avoid putting the system clock through ...
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72 views

Resampling with MSB operation

I'm new to verilog and HDL, so please be patient with me. In a code, I have an input variable clk, two input 16 bit samples, that are stored into ...
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51 views

Synthesis of Verilog code in Cadence

I am trying to synthesize my Verilog code, which I wrote using Modelsim tool for 8-bit MAC in Cadence Encounter. The file that is generated after synthesis has to be re-checked for functionality in ...
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1answer
93 views

Spartan 3AN FPGA DCM

While I use the internal clock for DCM clkin input I am getting clk0 as perfect frequency of output same as internal clock but not in remaining o/p pins. I changed from previous coding like this and ...
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132 views

Help needed with SPARTAN-3AN FPGA frequency doubler

Here I attached the routed nets for this below verilog HDL program with DCM instantiate module. while I am implementing in XC3S50AN FPGA board using using ISE12.3 Design suite clk2x & locked ...
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79 views

How to Implement this special selector?

Is it possible to write a module with 3 wires a,b,c that would output either : z (disconnected) if a=b=c=z a if a=(0 or 1) and b=c=z b if b=(0 or 1) and a=c=z c if c=(0 or 1) and a=b=z x (dont care) ...
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101 views

Synchronizing multiplier with adder to form mac

I have designed an 8-bit multiplier in Verilog which takes a maximum of 8 clock cycles to give the product. I have also coded a 16 bit adder based on combinational logic. I now want to integrate the ...
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58 views

How do I minimize the size of a 3-input parallel adder?

Currently this alu uses 24 logic elements, most likely from the adders. I'm wondering if there is any tool in Altera/Quartus I can use to minimize this? For my design, multiplier and RAM modules are ...
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How to efficiently implement a single output pulse from a long input on Altera?

I have a fast clock and a switch called 'ready'. When the switch is flipped (ready goes HIGH), I would like the output pcEn to produce a pulse that lasts only for one clock cycle. pcEn will only ...