Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips.

learn more… | top users | synonyms

0
votes
0answers
21 views

Initial blocks not synthesized but with XST, yes

Usually, initial blocks are not synthesizable but with Xilinx XST, they do. Where can I find this information ? I didn't find anything in the datasheet of my FPGA (XC3S1400A, spartan 3A). I read ...
2
votes
3answers
216 views

Why would you want to write to a file when writing VHDL? [on hold]

I have never so far been in the need to write to a file when making a testbench in vhdl. Seeing the signals being plotted has always been enough so far. Could someone please give me a case or the ...
0
votes
0answers
31 views

CFI flash interface in verilog

I am working on an Intel’s CFI - Flash (28F640J3) interface in verilog. I have written a code and tested it for many commands; read, write, erase. But I am facing problem with 'Write Buffer’ and read ...
-3
votes
0answers
36 views

how to encrypt string of characters in AES using verilog [closed]

For encryption in AES I have used the key and plaintext in the testbench as given below- assign key = 128'h78afe7c98872dc7ea22767627ccf9fbd; assign text_in = ...
-3
votes
0answers
20 views

Mixcolumn operation using systolic architecture [closed]

How can i design the systolic architecture and write fsm for the mixcolumn operation in AES using verilog. Code: ...
0
votes
0answers
13 views

Hardware Co-Simulation using ml605 with ISIM simulator …?

I am trying to do RTL(verilog HDL) and Firmware(System C) Co-Simulation with ISIM Simulator using VIRTEX-6 ML605 FPGA board. I am unable to run co-simulation. I have reffered the document " Hardware ...
-2
votes
1answer
32 views

Showing negative numbers in Verilog

I am writing a program for a 16-bit ripple carry adder and stumbling a little at the end. When I run my code (which includes negative numbers), it's doing the math right, but giving me all positive ...
1
vote
2answers
54 views

Correctly initialize a shift register (Verilog)

I've been struggling with a very simple Verilog program. It's a 4 bit shift register that gets rotated at every clock cycle and drives four LEDs. (As you can tell I'm new to FPAGs and HDLs.) The ...
0
votes
1answer
41 views

How can assign a synthesizable string to a byte array in SystemVerilog?

I want to initialize a byte array (or any other possible type) to a long string. For example define: string str = "abcdefg". I read these two links (1 & 2) but ...
0
votes
1answer
35 views

For loop in `define Macro

I searched on SO, and on web, no where found the ans. I have following code, where It success fully parsed `define and generate expected results, but if number of times calling of macro is large then, ...
-1
votes
1answer
41 views

How to create .VCD file or Simulation activity file of verilog code?

I have Verilog's code. It is simulated correctly and synthesize too. I wanted to write.VCD(value change dumped) file. I got from internet few command to generate VCD file as given below: ...
0
votes
0answers
52 views

rs232 verilog & c++

I am now working on a project using fpga rs232. I want to send the data from the computer via c++ writefile. When the computer sent the data to fpga it will show the result on the led. My problem is ...
-1
votes
2answers
62 views

verilog state machine - state won't update

So I'm trying to simulate a state machine with outputs s and v and a state. for some reason our s and v values are updating but the state refuses to change, any help would be awesome ...
2
votes
2answers
61 views

Is it right to initialize a reg in verilog and apply condition with initial value of reg in Verilog?

I have the little doubt related to initializing condition in Verilog. Like in given statement: ...
-3
votes
1answer
47 views

How to find minimum among variables with excluding variables having zero values in Verilog?

I have 6 variables names D1,D2,D3,D4,D5,D6. I wanted to find minimum among them but excluding the zeros if any present. I did same in MATLAB by using below command: ...
3
votes
1answer
60 views

Dividing a clock in Verilog - is it OK?

Dividing a clock down in Verilog is a basic exercise, and there are loads of answers online about how to do it. What I want to know is whether it is OK to use a clock that has been divided down using ...
1
vote
2answers
73 views

Synchronuous Combination Lock

I'm trying to implement a synchronous combination lock that will unlock once it receives "101011" using verilog. It has one input: x, and three outputs: unlock, ready, and error. Following these ...
0
votes
1answer
58 views

Non-Wraping Up-Down Counter

I'm trying to implement a synchronous up-down counter in verilog with the following rules: Counter only changes on rising edge of clock When reset=1, count goes to 00, normal operation when reset=0 ...
0
votes
1answer
25 views

Change array to individual outputs

I'm trying to design a synchronous sequential circuit to implement a tail light controller for a 1965 Ford Thunderbird using verilog as shown below (included with the state diagram). I have the ...
0
votes
0answers
55 views

Using 4-Channel ADC With FPGA

I am using an ADC084S101 4 Channel 8-bit A/D Converter to sample 4 different analog voltages. The ADC is being driven by a Nexys3 FPGA. I am having issues getting the ADC to cycle through all four ...
0
votes
2answers
59 views

Assigning x in verilog

Assume there exists a 1 bit data output port and a 1 bit dataValid output port for a module. Is it OK to assign 1'dx to the data output when dataValid is assigned 0? Will this create synthesis issues? ...
1
vote
1answer
27 views

User defined data type in Verilog

I have always used VHDL and now need to use Verilog, so I'm learning Verilog. . . How can I define and use user-defined data type in Verilog for state machines. for eg : In VHDL I would write ...
1
vote
1answer
121 views

Displaying Characters In Verilog With VGA

I'm taking a intro to ECE course as a CS student and for a final project we are to design a game coded in Verilog using the VGA display on a DE1-SoC board. I decided to create a hangman game but I ...
0
votes
1answer
35 views

Generating Channel Select for Multichannel ADC

I am using a FPGA to control a 4-channel ADC (ADC084S101) to sample four different analog voltages. In order to tell the ADC which channel to sample next, there is a control register that can be ...
1
vote
1answer
57 views

Asynchronous Down Counter using D Flip Flops

After fixing my Up Counter, I'm having troubles writing structural verilog code for an Asynchronous 4-bit Down Counter using D Flip Flops. Here's the D Flip Flop code (which was tested and works): ...
0
votes
0answers
54 views

Asynchronous 4-bit Up Counter using D Flip Flops

I'm trying to write structural verilog code for an Asynchronous 4-bit Up Counter using D Flip Flops. Here is my D Flip Flop Code made from this image: ...
1
vote
2answers
47 views

Is there some flag / pragma which can help me in detecting bogus variable names in a module definition?

[icarus verilog] Is there some flag / pragma which can help me in detecting bogus variable names in a module definition? Consider the following code fragment ... ...
-1
votes
2answers
62 views

Increment operation in 24 bit counter

This is a 24 bit counter verilog program. What is the function of highlighted operation? Do we add 1 to the least significant bit? How can we know that the addition was done to the least significant ...
3
votes
1answer
48 views

HCI UART ? what's the difference with simple UART?

For now, I'm sending bytes from FPGA (verilog) to serial at 115200 bps. I would like to send at higher speed and connect to a bluetooth module (RN42). UART (SPP or HCI) and USB (HCI only) data ...
0
votes
0answers
20 views

Event Debug Mode error when performing mixed Verilog/VHDL simulation in VCS

I am getting the following error: ...
1
vote
1answer
82 views

AND Gate and posedge CLK ? simple question

I'm trying to do the seq system as the picture, I'm sure it's simple but I don't remember the "gate" of this. This clock cond will be used for sending bit in ...
2
votes
0answers
85 views

Two different ways of writing the same thing but generating different behaviours in Verilog

I have a part of Verilog code that is basically trying to synthesize a flip-flop. I have been experimenting and it seems that I can come up with two ways of writing it. The first way being : ...
1
vote
1answer
24 views

Verilog outputting specific bit from register to output; getting constant 1's

I am trying to create an program that bit bangs a value from an FPGA to an arduino. In the module I created, every other clock cycle, the FPGAdata output should be set to the next bit of t. The ...
0
votes
1answer
35 views

Task doesn't work in verilog

I created a module that first sorts a byte array then choose last element as minimum.(just for practice). When I moved sort to the task block, it doesn't worked as well as before. How can use task ...
2
votes
5answers
148 views

Blocking vs Non Blocking Assignments

I have been having a really hard time understanding the difference between blocking and non-blocking assignments in Verilog. I mean, I understand the conceptual difference between the two, but I am ...
0
votes
1answer
58 views

D flip flop in verilog

When i tried to code the below flip flop, the program failed. I'm using altera . ...
0
votes
1answer
30 views
6
votes
1answer
61 views

What is the difference between an array and a bus in Verilog?

I have been learning Verilog and Vivado at school, and I am now very confused by the usage of busses and arrays. Can anyone clarify the following? What is the difference between an array and a bus? ...
0
votes
0answers
52 views

4-bit Comparator Verilog Code

I need to create structural verliog code to make a four bit comparator (out of four behavioral-coded one bit comparators). But I've only gotten my greater than output to work. I'm using this circuit ...
0
votes
2answers
72 views

Synthesizeable D Flip flop for FPGA

Having played around with Verilog for some time now, I decided to graduate to implementing designs on Alltera CycloneIV FPGA using the Quartus suite. Starting with a simple D flip flop, I face the ...
1
vote
4answers
127 views

How to make a Karnaugh Map with “don't care” inputs?

I know that don't cares mean that it doesn't matter whether it is a 0 or a 1 and when don't cares are just outputs I can kind of understand how they work. But I am having a really hard time ...
0
votes
1answer
33 views

Compact multi-cycle adder for fpga: adding 1 to wide counter

I want to implement some kind of event counter in my FPGA design (Vendor-A or Vendor-X). I have several dozens of signals: half are 1-bit and other half of them is 5-bit. Signals are located in ...
-7
votes
1answer
79 views

how to find square root of a number by using babylonian method [closed]

how to find the square root of number by using babylonian method equation: Xn+1=1/2(Xn+(s/Xn)) by using verilog code any one help me ........I have written a code but its not synthesis not running. ...
0
votes
1answer
46 views

What exactly does a High Impedance imply in Verilog?

When would we want to use High Impedance signals? In simulation, what causes the result of a high impedance signal? Seeing as its generally a bad thing, what should be looked for in terms of ...
6
votes
1answer
143 views

I want to implement a math equation in FPGA, should I describe a CPU or can I do it just by code?

For a school project I'm trying to implement an equation for example like this: (EDIT) B = ((A + 2) * |A - 10|) / (c * c) everything is unsigned binary values, ...
0
votes
1answer
66 views

Modeling a Time to Digital Converter in Verilog-AMS

I'm trying to write a TDC model in Verilog AMS. I'm really new at the AMS part of Verilog. The problem I'm running into is in assigning the final state of the TDC to the outputs. Below I present the ...
0
votes
1answer
39 views

Port Connection Rules in Verilog

I am a beginner in Verilog I would like to know why the port connection rules as outlined in the attached description are necessary. Why must inputs be internally of a net type signal? And ...
0
votes
2answers
148 views

8 bit counter from T Flip Flops

I'm trying to build an 8bit counter in Verilog. I specifically need to create a module that I instantiate 8 times. I have followed the diagram below (and assumed that I can just build on it to make it ...
0
votes
1answer
62 views

Quartus: Error (12004): Port z does not exist in primitive x of instance y

I cannot find any source for this error, any help much appreciated! Error: Error (12004): Port "a" does not exist in primitive "tff" of instance "t1" ...