Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips.

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Issues on using VHDL module in verilog

I'm having Synthesis errors on using a VHDL module in Verilog. The error message below says that the type of rd_ptr input in the VHDL module does not match the rd_ptr_integer variable in the verilog ...
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48 views

Efficient way of setting bits in verilog

I'm just learning verilog and have a question regarding setting bits in a 2 bit register (assuming I'm even making the register correctly). Suppose I have a hypothetical module, foo(), which has two ...
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56 views

How can we use D flip flop and a combinational circuit to retain a bit?

I am trying to solve a problem, which involves designing a gate level circuit, and I'm stuck on the last part of the problem. The last part wants me to retain the carry flag generated from the adder ...
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45 views

Unable to understand Verilog syntax

I found an example Verilog code as following: module test #(parameter p=1) (); localparam [1:0] lp = ~(p)'(1'b0); endmodule I'm unable to undestand the ...
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1answer
45 views

How is the signal assigned to a pin by default

Here's the simple verilog code that contains WR_n signal. This signal (net) is not explicitly assigned to a LOC (pin) in the .ucf file. The design implements without any errors. I would assume that ...
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Reading of hex file in testbench : Verilog [duplicate]

I have converted an image file into hex file which has R,G,B and alpha values in multiple columns. For example : 3c 48 36 ff 1d 2b 19 ff 08 18 06 ff 08 17 05 ff 14 1f 0d ff 1b 22 11 ff 1a 1f 0e ff 1a ...
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1answer
48 views

How to pass value from linux command to verilog? [closed]

I have some problem. once, look at this codes. Runit- #!/bin/csh -f ncverilog +access+w+r ₩ -f ff.list ₩ +define+LEVEL=$1 text.txt- ...
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60 views

“Unresolved reference to 'countmode1'” , Verilog simulation error

When I want to simulate the following code, I get these errors: ...
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32 views

Altera Megafunction generics

I am using the Altera Megafunction LPM_ROM in one of my designs using the block diagram editor in Quartus. I want the ROM to have a configurable initialization file. For example for my component X ...
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1answer
54 views

Does not the wire signal affect in sequencial logic?

I want to make 1 delay signal with an wire signal. Let's here my case. ...
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20 views

What is Verilog Output (.vo) file? When it is created?

I was running PCI Express reference design simulation in Modelsim. Compilation failed and an error "cannot open top_core.vo file in read mode" was displayed. I went through respective folder, but that ...
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My output in verilog is high impedance all the time. Why is that?

I am new to verilog and I have been writing code for 4 bit adder/substractor in structural model. My values of x0,x1,x2,x3,c1,c2,c3,cb and ...
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How to make choice in two different code with same output and different synthesis result?

I wrote a same verilog code with two different approach A and B. Both approach giving same output with different synthesis report. Results are as : Clock frequency= 50 Mhz A) Approach A giving: ...
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70 views

Cheapest FPGA PCIe board for Software Acceleration [closed]

This question is somewhat related to an earlier question: Cheapest FPGA's. I have been searching for a cheap FPGA board with PCI express 2.0 or 3.x support. Such boards can be plugged in one of the ...
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47 views

Verilog #parameter

What is equivalent VHDL code of these verilog lines: dfslckd_q <= #TCQ DFSLCKD; dfslckd_rising <=#TCQ !dfslckd_q & DFSLCKD; Signals are all bit (TCQ ...
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80 views

How to read hexadecimal data from text file and write in into memory in verilog?

I have a text file named "Hex_data.txt". I want to load content of hex_data.txt into a variable name RAM in verilog. The content of "hex_data.txt" : ...
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1answer
81 views

How to understand the timing report after synthesis?

After synthesis of my verilog code. I am getting the below timing report. I think it showing any mistake in my code. Timing Summary: Speed Grade: -2 Minimum period: 2.334ns ...
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67 views

Does the order of wires to assign matter?

In Verilog, given wires a and b, is there a difference between: assign a = b; And ...
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1answer
44 views

How do I understand report published in console tab after simulation in Xlinx?

The report is : Started : "Simulate Behavioral Model". Number of CPUs detected in this system: 2 Turning on mult-threading, number of parallel sub-compilation jobs: 4 ...
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Ethernet packet dump in FPGA memory getting corrupted

I am a beginner at Verilog and FPGA programming. My background is C/C++ software development. I am developing a FPGA module which would basically read Ethernet network packets and then interact with ...
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2answers
98 views

Unused select line combination in 3x1 MUX?

While designing a 3:1 mux we require 2 select lines, but one combination is not useful, say 2'b11. If this combination occurs the output becomes 0 irrespective of the value of input lines. Is not the ...
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2answers
128 views

Why does my ALU design delay outputting the results for two clock cycles since input of valid data?

Hello EE StackExchange! I have been trying to design a simple 8-bit CPU for several months now. However, I am experiencing a problem: The ALU outputs the result of the operation two clock cycles ...
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1answer
48 views

State based vs State-less design (in verilog)

Recently, I have been carrying out some beginner to lower moderate level designs, from starting to all the way to HDL coding in verilog. I thought that FSM based design, either Mealy or Moore is the ...
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56 views

why use sum of product and not product of sum in programmable logic array and programmable array logic [duplicate]

I am confused why only SOP(sum of product) are used in PLA and PAL and not POS(product of sum)
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2answers
75 views

How to find high fanout nets?

In the timing report of a synthesis with Synopsys VCS, a warning states: Warning: Design contains 8 high-fanout nets. A fanout number of 1000 will be used for delay calculations involving these ...
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3answers
75 views

Having trouble implementing a 1Hz blinking light on a Spartan 6 FPGA

I currently have a Spartan-6 FPGA in a Digilent Nexus 3 board. I am using Xilinx 14.6 Project Navigator to write the code and program the FPGA. My code for the top (and only) module is the following: ...
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1answer
56 views

Tips on linking SW and HW simulation.

I am total layman about this topic and I would appreciate experienced users to give me some useful tips and hints. I develop some code for arm cortex m0 which I want to simulate in ...
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34 views

Results analysis of the sequential filter and strength-reduced filter in frequency domain

I realized two low-pass filters by Verilog. The filter can be represented as following equation: 1. Sequential filter with 32 stages. For saving the multipliers, I only use one multiplier and do ...
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141 views

A simple FIFO buffer in verilog

I have decided to implement a FIFO buffer in verilog (for fun). Here is my primary prototype you can say : It will consist of a register bank or memory. Each register will be of size N and there ...
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32 views

Cursor (waveform) reading not the same with transcript window

I have run a simulation of a Verilog code testbench. I ran it in ModelSim, but why the reading I got from just using the cursor on the waveform is different from the one in transcript window. While ...
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1answer
56 views

Why does iSim give a different result than hardware

I am working on a MIPS CPU for an FPGA - this is mostly a personal project to understand FPGA's. I have a 5 stage pipeline CPU implementation working correctly when run on iSim, however when I run it ...
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1answer
74 views

Can someone explain a couple of lines of Verilog to me?

I'm a student trying to learn Verilog on my own with a dev board. This is just a simple and short module. I just need some clarifications. ...
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2answers
54 views

bit shifting using verilog

Im using verilog language for my program using ISE 14.5, when I give input for example x=0.707 and simulate it in test bench, it gives me wrong output because it consider 0.707 as 1. my question is ...
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1answer
26 views

Error Loading Design Unresolved Reference

Please help! DUT: AND gate module ANDgate(a, b, c); input a; input b; output c; assign c = a & b; endmodule TESTBENCH: Without task ...
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25 views

How to check input data and out data match using Verilog-A

I am trying to check data on an input and output of a circuit using verilog-a. So far I have tried bitwise comparison and masking, ex: ...
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1answer
118 views

UART to Bluetooth

I seem to find only partial explanations regarding this question, I've used Bluetooth in previous projects but I plan to use it on an FPGA project. Currently The FPGA is connecting using a UART ...
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1answer
49 views

where should I instantiate the DUT object? In the testbench file or in the task?

I am making a testbench in Verilog where it will call different test cases from different modules, each module, one test case/task. I am a beginner in making testbench, can I know where should I ...
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1answer
113 views

Finite State Machine, Verilog Code

I have everything right now, but the output I desire should be 00 00 11 00 00 00 00 10 00 00 00 when the clock is 1(z1z0). Can someone tell me what is wrong with my code? I've checked my Kmap numerous ...
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81 views

Having FPGA to output sound on “line out” pin using verilog

I am trying to write a verilog code for FPGA which will output sound from the embedded "line out" pin. I use Quartus II and Altera DE1. I am new to hardware programming, therefore it just takes too ...
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4answers
169 views

Generate an 40MHz Clock on an FPGA with 100Mhz clock

I'm trying to generate an 40MHz clock on an 100Mhz FPGA kind of strugle with the Verilog CODE, I rediredted the Clock to a pin to check the 100Mhz: ...
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1answer
52 views

Need help converting 8 bit input into 3, 4 bit outputs

I have a midterm coming up on digital system design. My professor developed an ASM chart for a problem and I decided that I would try to fill out the code for practice. The simulation runs, it just ...
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1answer
62 views

Designing of a 2:1 multiplexer for 64 bit input and output [closed]

How to design a 2:1 mux for a 64 bit input and output using Verilog code?
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2answers
119 views

Using GPIO in Altera

I'm trying to test the GPIO functionality of Altera (DE1, Cyclone II) with this simple program. If the GPIO_0[0] gets a high (1) signal, LEDG[0] will light up. If it receives a low (0) signal, ...
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1answer
220 views

Do If else have priority in verilog?

I have some query about the priority of if else in verilog. For example. If (a) b else if c d else if e f else g At here, those a,b,c...g are ...
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80 views

How to simulate and initialise Block Memory ROM created using Xilinix CORE generator?

I created the ROM correctly using the CORE generator and the correct .coe file. There is supposed to be instruction words inside the memory (32*256). But the data bus out of the memory is always set ...
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1answer
98 views

What are LUT (look up table)? [duplicate]

I am learner in verilog with less knowledge and trying to develop more understanding.I wrote a simple verilog code and synthesize and implement it. I do not have understanding of Look up tables. When ...
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2answers
79 views

Verilog Assignment

I'm designing a Fahrenheit to Celsius converter using algorithmic state machines. I'm trying to get the following code to run, but all I get for output is 0. ...
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1answer
53 views

How to check output after FPGA Implementation?

I have 10 numbers saved in RAM. I sorted it using Verilog code and saved output in another RAM. I did simulation and it was doing correct sorting. I synthesized it and generate bit file. Now i want ...
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2answers
112 views

Finite State Machine in Verilog

So I am trying to make a basic FSM in verilog to turn on 3 different LEDs. I've looked at examples and other people's work, but I can't understand why mine wont work. Maybe someone can help me spot a ...