Tagged Questions

2
votes
3answers
102 views

View more than 100 worst-case paths in Quartus II

I am using Quartus II to compile Verilog for my FPGA project. For debug, I use SignalTap, which introduces a lot of timing warnings. When I go to the TimeQuest report, and look at the worst-case ...
-1
votes
2answers
269 views

Learn CPLD from zero [closed]

a) Should I learn VHDL or Verilog? Is one excel in some area while the other better fit another area? For simple "glue logic", says, 5 to 30 TTL chips equivalant, which is better? b) First ...
2
votes
1answer
168 views

My design is not meeting timing. What can I do?

I am using the Altera Quartus II software to compile Verilog for a Cyclone IV FPGA. In my case, the FPGA is fixed; I cannot get a faster one. Now one isolated module in my design, which deals with ...
4
votes
3answers
1k views

What is clock skew, and why can it be negative?

My HDL compiler (Quartus II) generates timing reports. In it, the nodes have "clock skew" column. The only definition of clock skew I found is in the TimeQuest documentation (see page 7-24): To ...
4
votes
4answers
1k views

Using both edges of a clock

I am programming an Altera Cyclone IV using Verilog and Quartus II. In my design, I would like to use both edges of a clock so that I can do clock division by an odd factor with a 50% duty cycle. Here ...
2
votes
2answers
198 views

Merge a differential pair into one signal

I have an LVDS ADC connecting to an Altera Cyclone IV FPGA. The data pins come in 7 differential pair channels, for a total of 14 pins. Although each differential pair is physically 2 pins, my ...
4
votes
3answers
332 views

Altera optimisation: “Stuck at GND due to stuck port data_in”

I am compiling Verilog code with the Quartus II compiler, and it seems that almost all my code is being optimised away. The "compilation report" says that many of my registers are being removed during ...
1
vote
1answer
127 views

Altera Cyclone IV memory block Verilog module

This document explains the various characteristics of the Altera Cyclone IV memory blocks (known as "M9K"). However, there is no mention as to how these modules should be instantiated in Verilog. ...
3
votes
1answer
214 views

Cyclone II FPGA Starter Kit Configuration Seems to be Giving Bogus Results

I've been trying to get my Cyclone II FPGA (from the Starter Kit, EP2C20) to work. I've gotten the Quartus II software to work on my Ubuntu setup and it' ALMOST working - I can write some Verilog, ...
1
vote
0answers
176 views

Any good tutorials for Altera DE2 with cyclone II? [closed]

Is there any good tutorials for verilog and the university board of altera DE2, I found this list, but are they any good video tutorials? or printed as well?
1
vote
2answers
256 views

Quartus - Export Verilog as Gate Level (FPGA)

I've got a project in Altera's Quartus II software which is written in Verilog. I'm curious if anyone here has figured out how to export the Verilog as a gate level netlist. I'd like to simulate the ...
3
votes
2answers
742 views

Verilog: Check for two negedges in always block

i try to do something like this: always @ (negedge speed_dec or negedge speed_inc) begin do something end This doesn't work as checking for 2 negative edges ...
1
vote
2answers
621 views

UART core Altera De2

I have to implement a rs232 receiver for my project. Does any one have any idea on how do I start learning / implementing this. Do i have to use the nios ii software or just implement it using verilog ...
2
votes
1answer
472 views

Trying to program an FPGA. (Altera Cyclone II)

I have got FPGA development board (Cyclone II EP2C20F484C7) and am trying to implement a simple counter program as shown below (and maybe link it to the LEDs). ...