Tagged Questions
0
votes
2answers
297 views
Inferring BUFGMUX in Xilinx FPGAs for Clock Multiplexing
I have a VHDL memory core which requires me to multiplex between two clocks. The Write clock operates at 200 Mhz and Read clock operates at 100 Mhz. I think this can be done using ...
4
votes
3answers
1k views
What is clock skew, and why can it be negative?
My HDL compiler (Quartus II) generates timing reports. In it, the nodes have "clock skew" column. The only definition of clock skew I found is in the TimeQuest documentation (see page 7-24):
To ...
4
votes
3answers
312 views
Help wanted explaining signals coming with higher frequency than clock and how to handle them
I am getting my hands on Verilog and FPGA programming. So I wrote a simple module that handles two inputs - button signal and a clock. Initially, it lights up two LEDs and when the user presses and ...
0
votes
1answer
417 views
Working with Spartan-6 LX9 clock
I am a novice in digital design and are learning things using "Advanced Digital Design with the Verilog HDL" along with a Spartan-6 LX9 board by Xilinx. So far I have managed to blink few leds on the ...
