Tagged Questions
-7
votes
1answer
46 views
3-phase lock loop in verilog
I want to implement a phase lock loop in verilog hdl. The input is the source voltage (which is a sine wave) and the output is theta(in terms of sin and cos).
-4
votes
0answers
89 views
Ideas for a project combining arduino and FPGA [closed]
I would like some suggestions for my project. I need to implement ARDUINO and FPGA, nothing too complex nothing too easy. Just something Simple! where I can show that I have knowledge of these ...
1
vote
2answers
77 views
Post synthesis level simulation xilinx xst
I have written a verilog code and it is working fine at behavioral simulation level. After this I went for synthesizing the design using XST tool in Xilinx ISE 13.2. Running the post simulation level ...
2
votes
2answers
127 views
Difference between RTL and Behavioral verilog
Can someone tell me what is the difference between RTL and behavioral Verilog code? Is there any clear cut demarcation between designs at these two levels?
0
votes
1answer
162 views
What is backdoor memory access?
There is a term in HDL simulation/verification called
"backdoor memory access".
I've heard this a lot of times though I'm
not sure how is this implemented.
Also, there are a few references for this ...
1
vote
2answers
96 views
Automating test vector in Verilog HDL
This is my first attempt at learning Verilog HDL testbench for an AND gate:
...
8
votes
4answers
2k views
Why are inferred latches bad?
My compiler complains about inferred latches in my combinatorial loops (always @(*), in Verilog). I was also told that inferred latches should preferably be ...
3
votes
2answers
726 views
Verilog: Check for two negedges in always block
i try to do something like this:
always @ (negedge speed_dec or negedge speed_inc)
begin
do something
end
This doesn't work as checking for 2 negative edges ...
0
votes
2answers
1k views
How to assign value to bidirectional port in verilog?
I'm trying to use a bidirectional port in Verilog so I can send a receive data through it. My problem is that when I try to assign a value to the port inside a task, but I keep getting an error.
...
3
votes
1answer
109 views
What was the motivation for making behavioral descriptions such a big part of Verilog?
I don't use Verilog for anything serious, but I use it in my classes, and I'm starting to think I must be missing something about the appeal of behavioral hardware description.
When I write Verilog I ...
22
votes
9answers
5k views
VHDL or Verilog?
VHDL and Verilog are the HDLs of the day. What are the advantages of either for someone who has no experience with HDLs at all?
0
votes
1answer
327 views
recommandation webpage/book to learn asmd chart over using verilog
I have searched so many website to take background about how asm chart is used in verilog code.However, I could not find any web cite with sufficient examples to learn asm chart. Can anyone give or ...
3
votes
2answers
953 views
how to write output of the monitor to a file
I have a testbench and a verilog modules. I want to write ouput of the testbench to a file anmed as output.txt. While doing this job, I want to use $monitor.
Is it possible ? If yes, can you give me ...
1
vote
1answer
132 views
What language is Cadence's Emanger *.ecom files written in?
I know this is a long shot but I thought I would ask while I am waiting for the FAE to get back to me. This is related to Cadence Verilog simulations and regressions.
I am trying to debug an *.ecom ...
4
votes
4answers
1k views
Exercise based book to learn Verilog/vhdl?
I was planning on learn an HDL (preferably verilog as I have to take a course in it in subsequent semesters). My initial plan was to first learn the syntax and then implement all the digital systems I ...
17
votes
7answers
1k views
How do I learn HDL
I have a course in Digital Design in this semester and just love it. Now I know that most of the work in embedded system and digital design is done on computer simulators first and then implemented ...
