Tagged Questions

votes

6answers

947 views

Readable and educational implementations of a CPU in a HDL

Can you recommend a readable and educational implementation of a CPU in VHDL or Verilog? Preferably something well documented. P.S. I know I can look at opencores, ...

community wiki

4 revs, 4 users 100%
Eli Bendersky

newest verilog softcore questions feed

Technology			Life / Arts	Culture / Recreation	Science	Other
Stack Overflow Server Fault Super User Web Applications Ask Ubuntu Webmasters Game Development TeX - LaTeX	Programmers Unix & Linux Ask Different (Apple) WordPress Answers Geographic Information Systems Electrical Engineering Android Enthusiasts IT Security	Database Administrators Drupal Answers SharePoint User Experience Mathematica more (14)	Photography Science Fiction & Fantasy Seasoned Advice (cooking) Home Improvement more (13)	English Language & Usage Skeptics Mi Yodeya (Judaism) Travel Arqade (gaming) Bicycles Role-playing Games more (22)	Mathematics Cross Validated (stats) Theoretical Computer Science Physics more (7)	Stack Apps Meta Stack Overflow Area 51 Stack Overflow Careers

rev 2013.5.24.702

Electrical Engineering Stack Exchange works best with JavaScript enabled

Tagged Questions

Readable and educational implementations of a CPU in a HDL

Related Tags