Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips.
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1answer
176 views
Synthesis error for generated IP express single port RAM with shift register design
I have generated single port RAM (DP8KC primitive) from IP express using Lattice tool and then I am instantiating with 48 bit shift register, which is at input side. The output of shift register is ...
0
votes
2answers
498 views
De2 Board reading sensor reading
I wish to operate a LVMAX Sonar EZ1 sonar rangefinder.
They say
With 2.5V - 5.5V power the LV-MaxSonar EZ1 provides very short to long-range detection and ranging, in an incredibly small package. ...
4
votes
5answers
306 views
Stress testing an FPGA's power supply
I have an FPGA (Xilinx Spartan 6) for which I want to stress test the power supply in "steps" (e.g. the FPGA runs in loops of 1 seconds: full steam for 900 ms, halted for 100 ms) to check that the ...
25
votes
9answers
6k views
VHDL or Verilog?
VHDL and Verilog are the HDLs of the day. What are the advantages of either for someone who has no experience with HDLs at all?
17
votes
7answers
1k views
How do I learn HDL
I have a course in Digital Design in this semester and just love it. Now I know that most of the work in embedded system and digital design is done on computer simulators first and then implemented ...
14
votes
2answers
671 views
How is ASIC design different from FPGA HDL synthesis?
I've had some experience with FPGA/HDL tool suites such as Xilinx ISE, Lattice Diamond, etc. The general workflow is writing Verilog/VHDL, simulation, testing and then programming the FPGA.
I've ...
3
votes
2answers
2k views
Implement serial port on fpga (verilog)
I don't know if this belongs here or stackoverflow. I assume here as although verilog looks like software it's actually describing hardware connections?
I have a Spartan-3AN evaluation board and I'm ...
1
vote
2answers
815 views
How can I generate a schematic block diagram image file from verilog?
I want to create a schematic of a specific verilog module hierarchy showing which blocks are connected to which other blocks. Much like Novas'/Springsoft's Debussy/Verdi nschema tool, or any of a ...
0
votes
2answers
229 views
Verilog: Data Transfer using inout ports
I have an EEPROM following I2C protocol. My write operation was fine. While a read operation, SDA being my inout pin, during data transfer from slave, I held the pin in high impedance (Z).I received ...
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votes
1answer
100 views
verilog_code_compilation problem [closed]
In this program, I am trying to call a task which is in another file (or folder called trial) using
`include "trial.v"
During compilation, it shows the following ...
14
votes
7answers
1k views
Can an FPGA design be mostly (or completely) asynchronous?
We had a very short FPGA/Verilog course at university (5 years ago), and we always used clocks everywhere.
I am now starting out with FPGAs again as a hobby, and I can't help but wonder about those ...
4
votes
3answers
1k views
What is clock skew, and why can it be negative?
My HDL compiler (Quartus II) generates timing reports. In it, the nodes have "clock skew" column. The only definition of clock skew I found is in the TimeQuest documentation (see page 7-24):
To ...
4
votes
2answers
3k views
How are Verilog “always” statements implemented in hardware?
The Verilog always statement, namely
always @(/* condition */)
/* block of code */
executes the ...
3
votes
1answer
130 views
What exactly do we write in a test vector?
My professor has asked me to write Test vectors for the controller shown in the circuit below:
We have not implemented the controller as of now. I want to understand what exactly we write in a ...
2
votes
2answers
354 views
MUX verilog code
Can anyone explain the difference between the two codes below. Both written in Verilog, Xilinx. If someone can explain how the second one works would much appreciate it.
...
2
votes
1answer
182 views
What FPGA chips support verilog-ams or verilog-a
I am having trouble finding explicit evidence on any FPGA vendors website that their chip supports the verilog-ams and/or verilog-a. Do all these chips support it, or is it only "mixed-signal" chips, ...
1
vote
1answer
144 views
Verilog output port is high impedance (Z) when driven by a sub module
I'm writing code for shifting 4-bit using carry flag for generating delay using instantiating but when I'm instantiating in top module output of top module temp1 ...
1
vote
0answers
187 views
Any good tutorials for Altera DE2 with cyclone II? [closed]
Is there any good tutorials for verilog and the university board of altera DE2,
I found this list, but are they any good video tutorials? or printed as well?
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votes
1answer
100 views
Error :4:1 multiplexer
I am getting compiling error while on 2'b100 as it says that Bounds of part-select into 'mux_out' are reversed. Is this the right way to do ?
...
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votes
0answers
67 views
Applications with kernels that can be accelerated in hardware [closed]
Could you give me a list of applications with kernels that can be accelerated in hardware?
Some examples would include FFT, AES, Motion Estimation, Viterbi Decoder. I'm just looking for others.
To ...
