VHDL (VHSIC hardware description language) is a hardware description language used in electronic design automation to describe and design digital systems such as field-programmable gate arrays and integrated circuits.

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The timing-driven placement phase encountered an error

Could someone explain inexperienced VHDL coder what this error message trying to tell me in simple words? I found a similar question here, but here was no answer to it: ...
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29 views

Timing/buffering issue with Digilent's EPP on Basys2?

I have a Digilent Basys2 FPGA, and I'm implementing the EPP interface described in http://www.digilentinc.com/Data/Products/ADEPT/DpimRef%20programmers%20manual.pdf. This allows a program called ...
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61 views

Using one channel from adc (pin connections)

For a heart rate calculator project by using Basys2 and VHDL, I am trying to connect ADC0808 in order to get 8bit digital output from my pulse sensor's output. However, although I designed the circuit ...
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61 views

Functional and Timing accuracy of an RTL Model

I am sometimes really confused by the abusive use of jargon in EDA/VLSI design articles and books. With no precise definitions, its upto the reader to make interpretation which is very ambiguous and ...
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57 views

FPGA based theremin , is possible?

I remember a while ago , i saw some Digital based Theremins circuits from glasgow university... http://www.theremin.info/-/viewpub/tid/10/pid/65 would it be possible to make a theremin by using an ...
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54 views

VHDL RS-232 Receiver

I have been trying to design an RS-232 receiver taking an FSM approach. I will admit that I do not have a very well-rounded understanding of VHDL, so I have been working on the code on the fly and ...
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40 views

vhdl code for thermometer using xilinx fpga [on hold]

I am new to VHDL coding and I have an FPGA. I am trying to build a digital thermometer using some a temp sensor and fpga. I have made some research and SPI interface seems to fit best my needs. But i ...
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40 views

Integer to std_logic type conversion

I want to assign the value of a generic that is an integer to a signal which is a std_logic type. My generic can take only two values, 0 and ...
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2answers
49 views

Why does this adder need two clock cycles (two pushes of the button) to display a result?

I'm implementing a simple adder with carry out in VHDL on a BASYS2 board. This is the code below: ...
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VHDL code of johnson counter [closed]

For every 11th clock pulse the output goes high , so design it using a johnson counter . Also write the VHDL code ?
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49 views

How to best synthesize a systolic circuit on FPGA?

I am developing a parameterized systolic circuit in VHDL, using generics. It exhibits regularity in 2 dimensions. I am about to synthesize it on Xilinx FPGA. I suspect it is worth informing the ...
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68 views

LFSR Using D Flip Flops

I am fairly new to the VHDL language and I will admit that I primarily use it for educational purposes. I have been attempting to design a data encryption circuit using D flip flops. Obviously, an ...
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82 views

LED PWM controller

I want to create Led PWM controller and I tought it is easy but one line in my code generates more warnings than all my previous little projects. Here is the code: ...
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1answer
41 views

Implementing a counter in VHLD with edge triggered clear

I'm still giving my first steps learning VHDL and after a couple of days I could not yet find a solution for this problem. What I'm trying to do is to implement an LCD controller on an Altera MAX II ...
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29 views

Balanced partitioning turned off?

I am programming with a CPLD of Lattice Semiconductors (ispMACH 4000ZE) and the program ispLEVER Project Navigator. I want to implement a quadriture counter. First I implemented the counter only for ...
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6answers
642 views

What is the difference between testing and verification?

Every textbook I've seen makes a big deal of the fact that testing and verification are two different concepts. Yet none of them provides a clear (or clear enough to me, at last) distinction. To ...
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2answers
127 views

UART Receiver glitches

I encounter problems with my UART receiver module. It is supposed to work at 9600 bauds without parity bit and only one stop bit. The problem is that my UART misses some characters (or to indicate ...
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2answers
80 views

Signal(s) form a combinatorial loop VHDL

I was trying to implement Dual-priority encoder but I get following warnings during synthesize: WARNING:Xst:2170 - Unit prEnc : the following signal(s) form a combinatorial loop: done, first<3>, ...
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1answer
73 views

VHDL delay mechanism

I have difficulty understanding how the delay (mainly inertial delay: AFTER) mechanism works in VHDL. I'll start with this: target <= waveform AFTER 3 NS; As ...
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27 views

Component instantiation in VHDL

I need some help with component instantiations (port maps) in VHDL. I have a 16 bit Full Adder which I want to import in my ALU, and it should trigger when the ...
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45 views

Using explicit registers in RTL designs

Is it a good practice to use explicit register IPs in RTL designs? For instance, having separate IPs for each type of register and instantiating them in the design instead of coding them on-the-fly. ...
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42 views

When to use process statement in VHDL

I was wondering when I am suppossed to use process statement in VHDL. I saw some examples in books but all of them could also be written within concurrent structure? I use VHDL to program FPGA.
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2answers
161 views

How does someone initially design a digital system for HDL?

So I have really been hitting the example code hard this week in an attempt to better understand some HDL design basics, specifically FPGAs with VHDL. The book I am using (if anyone is interested) is ...
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153 views

Is it possible for a VHDL component to have multiple architectures?

Just a thought I had: is it possible for a VHDL component to have multiple architectures if outputs are not modified by both? If so how can we select the one to use at synthesis time (like the C ...
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1answer
250 views

is 'Ok' important when sendin AT commands to modem

I'm currently using VHDL to program the FPGA Spartan 3AN Kit-set. The objective is create a programme to send an SMS to a mobile phone, using the Kit-set via the modem. I'm done with the transmit ...
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66 views

Can oscillations occur in VHDL with concurrent statements?

Imagine we had two concurrent statements that depend on each other: ...
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67 views

Doubt about counter implemented in VHDL

I'm trying to learn VHDL and I came across some example code for a counter that I find somewhat strange. I understand what it does but I'm not sure why it is written the way it is. The code is the ...
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63 views

register without clk

I'm designing a small system in VHDL using the datapath and contorller method. Is it okay if I design registers that don't have a clock input (load data on the rising edge of the load signal) as they ...
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72 views

How to reduce an ALU logic with the minimum logic possible? Its very challenging

Our professor wants us to reduce 8 function alu (8 outputs) to a 4 out ALU that has capability to implement all the 8 functions. We can use any gates(even aoi's), muxes, and can create our control ...
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428 views

What would make me choose Verilog or VHDL over schematic design on CPLDs or FPGAs?

I have absolutely no background in programmable logic, I use mostly microcontrollers in my projects but recently I needed to work with video and the microcontroller is just too slow for what I needed ...
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44 views

VHDL indexed part select

Is there a way to do indexed part select of an array in VHDL as in Verilog? I know that you can use an array but creating a new type seems overkill to me. Moreover it's possible to slice an array ...
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237 views

FPGA Test Equipment

I mostly have desktop software development background. Trying to learn hardware design. Question: The question is mostly for developers (mostly individual contractors) who develop for any expensive ...
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47 views

What CPUs use a skewed associative cache?

What CPUs use a skewed associative cache? I see several people imply that, with roughly the same hardware, a skewed-associative cache often has better performance than a traditional set-associative ...
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1answer
90 views

Difference in the datapath of Load Upper Immediate to Load Word in a 32 bit MIPS processor

For the MIPS insturction Load Word I have got the following Datapath: How does the datapath for the Instruction ...
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1answer
65 views

VHDL internal signal assignment

I am new to VHDL and tried to implement a simple example from a book, what represents a 2bit register and the testbench. Compiling the files works well, and signals the stimulate the register (reset, ...
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49 views

Delete or ignore I/O from a schematic block in Lattice?

I am programming with a Lattice ispMACH 4000ZE Pico DevKit and with the software ispLEVER Classic Project Navigator. I want to use in my schematic file the OSCTIMER block from the Lattice library, but ...
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1answer
91 views

VHDL USB UART Problem

I've just described an UART transmitter and receiver in VHDL. In simulation everything seems to be fine. In FPGA, the loopback interface works well: I push a button, the transmitter sends data, the ...
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2answers
54 views

Quartus FPGA migration issues

I have an FPGA design Quartus that compiles and works correctly for a cyclone IV EP4CE15F17C8 (42% used). I'm trying to migrate same design to a smaller FPGA EP4CE10F17C8, but when changing FPGA ...
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69 views

OLA adder and signed digit vhdl design problem

I have implemented the following online adder for signed digit using vhdl code and I have simulated my design according to the example table shown in the figure attached the problem is I am not ...
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78 views

Uploading C program to the ARM core for execution through ethernet!

I want to write a c code on my local PC and upload it to ARM core on Zed-board for execution. I know we can do it using JTAG, but for obvious reason I want to use Ethernet interface. I will be glad ...
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57 views

How to make valid harness port when generate sub-sheet from vhdl

I have an VHDL file (a block) with huge count of the different port that can't combined into the one bus because they have different names. These signals will be further connected to different parts ...
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61 views

VHDL test bench file not accepting all set of inputs

My VHDL test bench here is not accepting the third set of inputs and is looping back to the start of the process. Please help me. Code: (comp4bit.vhd) ...
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35 views

Trouble getting push button working in Nios II

To give you an idea of what I'm trying to accomplish, the 18 LEDs on the board are to scroll right to left, then back to the right, and keep looping as such. Where the push button comes into play is ...
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4answers
153 views

VHDL: Using '*' operator when implementing multipliers in design

Present day FPGAs have built in DSP blocks, the latest FPGAs even have built in IEEE-754 compliant floating point units. It is possible to create DSP entity/module using a GUI after selecting the ...
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2answers
169 views

VHDL FSM Moving Average

I'm trying to write a VHDL moving average (evenly weighted) module that uses FSMD(ata). From what I understand, the states needed would be something like fetch, divide, output. Below is the process I ...
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125 views

Understanding timing constraints

I don't want an introductory text on timing constraints, nor an application note, an user manual, a webinar. I read them all, already, many times. The concept behind timing constraints is very easy. ...
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140 views

counter that MSB toggles every 2 seconds [duplicate]

I want a counter that the Most significant bit toggles every 2 seconds, and gets values 0 and 1.So for example it will have 0 for 2 seconds and after 1 for another 2 seconds etc.. I need it like that ...
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1answer
113 views

rescale a binary number [closed]

How I can decode a 6 bit binary number(up to 32 in decimal) to a 7 bit binary number(up to 100)? I want to change scale from 32 to 100 scale. I am using VHDL-93. For example if the binary number is ...
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100 views

Modelsim error before simulating from Quartus

I have the latest Quartus II 14. Modelsim is setup in the EDA tool options. I have a very simple MUX as follows: ...
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98 views

Trying to understand vhdl led blinking code

I have a led blinking code for MachXO2 breakout board written in VHDL. Actually I am new to VHDL. I am not able to understand the meaning of these lines: ...