VHDL (VHSIC hardware description language) is a hardware description language used in electronic design automation to describe and design digital systems such as field-programmable gate arrays and integrated circuits.

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How to reduce an ALU logic with the minimum logic possible? Its very challenging

Our professor wants us to reduce 8 function alu (8 outputs) to a 4 out ALU that has capability to implement all the 8 functions. We can use any gates(even aoi's), muxes, and can create our control ...
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321 views

What would make me choose Verilog or VHDL over schematic design on CPLDs or FPGAs?

I have absolutely no background in programmable logic, I use mostly microcontrollers in my projects but recently I needed to work with video and the microcontroller is just too slow for what I needed ...
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31 views

VHDL indexed part select

Is there a way to do indexed part select of an array in VHDL as in Verilog? I know that you can use an array but creating a new type seems overkill to me. Moreover it's possible to slice an array ...
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2answers
210 views

FPGA Test Equipment

I mostly have desktop software development background. Trying to learn hardware design. Question: The question is mostly for developers (mostly individual contractors) who develop for any expensive ...
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39 views

What CPUs use a skewed associative cache?

What CPUs use a skewed associative cache? I see several people imply that, with roughly the same hardware, a skewed-associative cache often has better performance than a traditional set-associative ...
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39 views

Difference in the datapath of Load Upper Immediate to Load Word in a 32 bit MIPS processor

For the MIPS insturction Load Word I have got the following Datapath: How does the datapath for the Instruction ...
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1answer
49 views

VHDL internal signal assignment

I am new to VHDL and tried to implement a simple example from a book, what represents a 2bit register and the testbench. Compiling the files works well, and signals the stimulate the register (reset, ...
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42 views

Delete or ignore I/O from a schematic block in Lattice?

I am programming with a Lattice ispMACH 4000ZE Pico DevKit and with the software ispLEVER Classic Project Navigator. I want to use in my schematic file the OSCTIMER block from the Lattice library, but ...
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60 views

VHDL USB UART Problem

I've just described an UART transmitter and receiver in VHDL. In simulation everything seems to be fine. In FPGA, the loopback interface works well: I push a button, the transmitter sends data, the ...
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48 views

Quartus FPGA migration issues

I have an FPGA design Quartus that compiles and works correctly for a cyclone IV EP4CE15F17C8 (42% used). I'm trying to migrate same design to a smaller FPGA EP4CE10F17C8, but when changing FPGA ...
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61 views

OLA adder and signed digit vhdl design problem

I have implemented the following online adder for signed digit using vhdl code and I have simulated my design according to the example table shown in the figure attached the problem is I am not ...
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75 views

Uploading C program to the ARM core for execution through ethernet!

I want to write a c code on my local PC and upload it to ARM core on Zed-board for execution. I know we can do it using JTAG, but for obvious reason I want to use Ethernet interface. I will be glad ...
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51 views

How to make valid harness port when generate sub-sheet from vhdl

I have an VHDL file (a block) with huge count of the different port that can't combined into the one bus because they have different names. These signals will be further connected to different parts ...
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41 views

VHDL test bench file not accepting all set of inputs

My VHDL test bench here is not accepting the third set of inputs and is looping back to the start of the process. Please help me. Code: (comp4bit.vhd) ...
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30 views

Trouble getting push button working in Nios II

To give you an idea of what I'm trying to accomplish, the 18 LEDs on the board are to scroll right to left, then back to the right, and keep looping as such. Where the push button comes into play is ...
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4answers
115 views

VHDL: Using '*' operator when implementing multipliers in design

Present day FPGAs have built in DSP blocks, the latest FPGAs even have built in IEEE-754 compliant floating point units. It is possible to create DSP entity/module using a GUI after selecting the ...
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137 views

VHDL FSM Moving Average

I'm trying to write a VHDL moving average (evenly weighted) module that uses FSMD(ata). From what I understand, the states needed would be something like fetch, divide, output. Below is the process I ...
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102 views

Understanding timing constraints

I don't want an introductory text on timing constraints, nor an application note, an user manual, a webinar. I read them all, already, many times. The concept behind timing constraints is very easy. ...
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1answer
131 views

counter that MSB toggles every 2 seconds [duplicate]

I want a counter that the Most significant bit toggles every 2 seconds, and gets values 0 and 1.So for example it will have 0 for 2 seconds and after 1 for another 2 seconds etc.. I need it like that ...
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110 views

rescale a binary number [closed]

How I can decode a 6 bit binary number(up to 32 in decimal) to a 7 bit binary number(up to 100)? I want to change scale from 32 to 100 scale. I am using VHDL-93. For example if the binary number is ...
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67 views

Modelsim error before simulating from Quartus

I have the latest Quartus II 14. Modelsim is setup in the EDA tool options. I have a very simple MUX as follows: ...
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1answer
89 views

Trying to understand vhdl led blinking code

I have a led blinking code for MachXO2 breakout board written in VHDL. Actually I am new to VHDL. I am not able to understand the meaning of these lines: ...
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4answers
153 views

How to bring out internal signals of a lower module to a top module in VHDL?

How can I bring out the internal signals of my VHDL source code to my testbench so that I can view them as waveforms? I use Active HDL. I would like to know if there is any tool independent method of ...
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1answer
96 views

Configuring a 7-Series GTXE2 transceiver for Serial-ATA (Gen1/2/3)

Hello this will be an experts questions :) You should be familiar with the following topics Xilinx Multi-Gigabit-Transceivers (MGTs), especially the 7-Series GTX/GTH transceivers (GTXE2_CHANNEL) ...
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2answers
119 views

FPGA RAM / SRAM in VHDL

Today I ran out of gates on my Xylinx Spartan 3 (Basys2 by Digilent) FPGA. This was not a surprise to me as I had implemented an 8 bit x 2048 array for use as an FIFO buffer. Code: ...
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109 views

How do you set the time resolution in Synplify?

I am generating a 1khz pulse from a 32MHz clock, naturally via a counter. Not a difficult task, so you can imagine my surprise when the result runs at 992Hz... Simulating the behavioural model of ...
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26 views

Synopsys design compiler- view datapath extraction results

I am using Synopsys Design Compiler(SDC) for synthesis with compile_ultra. This option does advanced datapath extraction which basically tries to group(or chain) ...
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1answer
88 views

VHDL 'buffer' vs. 'out'

I was wondering about the 'buffer' i/o option for entities in the VHDL language. I have found that my code is much cleaner if I use the 'buffer' option instead of 'out' in any circumstance where I ...
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64 views

Single Die Roll Counter Wrap Around Nested Ternary Conditional

I have to emulate a single die roll, therefore it needs to wrap back to one at 6. `D1 and `D6 correspond to my 3-bit state ...
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64 views

In VHDL what is a data operator type “variable” when it is translated to circuit? [duplicate]

VHDL code is finally converted into hardware equivalent when it is synthesized. What happens to data operator type "variable" when it is synthesized?
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56 views

Can we declare output as “inout” to design a flip flop in VHDL?

I want to design a JK flip flop in VHDL. In this output depends on previous state. One method to implement this condition is by declaring a state as a signal inside the architecture. Another method ...
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1answer
64 views

Create delay shorter than a clock period in CPLD

I have several peripherals that connect to CPLD. They all have different propagation delays, and to compensate that I wish to introduce about 10-15ns delay into the CPLD logic. In detail, clkOUT ...
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48 views

Is the simulated clock cycle latency through an entity accurate?

If I write an entity that takes 10 clock cycles to produce output from input, is it safe to assume that this is the case when implemented in hw, or are there other factors to consider? Does the ...
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35 views

Generating a desired pulse train in Xilinx ISE software

Need some help with VHDL and FPGA since I am new to it. I have a Virtex-4 FPGA and I wish to generate a binary pulse train of 16 pulses from FPGA using VHDL programming. My desired pulse train will ...
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151 views

Is 'IF' statement necessary for the clock process?

I'm used to writing the following process that will react on the rising edge of the CLK (script 1): ...
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1answer
266 views

having distorted image in VGA with FPGA board

I'm using spartan 3E-100 CP132 fpga board to display a basic plus image on a monitor. I have tried using 800x600 72 hz and 640x480 60 Hz but I always get a distorted vertical lines. Is it because the ...
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1answer
74 views

USB mouse with a PS/2 adapter for FPGA PS/2 interface

I'm designing a PS/2 mouse interface for BASYS 2 FPGA board. As you might know to communicate with a PS/2 mouse you need a protocol, so if I write my VHDL program for the PS/2 protocol and then ...
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565 views

Why delays cannot be synthesized in Verilog?

I have always read that delays declared in RTL code can never be synthesized. They are meant only for simulation purpose and modern synthesis tools will just ignore delays declarations in the code. ...
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1answer
159 views

generating 40 mhz clock from 50 MHz

In VHDL how can I get a clock frequency of 40 MHz if my onboard clock is 50 MHz. I know how to divide the frequency by integers but this case is dividing by 1.25. I am using this for VGA so I think ...
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1answer
118 views

generating 40 MHz clock from 50 MHz in VHDL [duplicate]

In VHDL how can I get a clock frequency of 40 MHz if my onboard clock is 50 MHz. I know how to divide the frequency by integers but this case is dividing by 1.25. I am using this for VGA so I think ...
7
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1answer
147 views

How do I debug red signals in ModelSIM?

I have to design a state machine using only NAND gates for the combinatorial part and D flip flops for the sequential logic. Everything should run at a clock of 1ghz/53. Now before you assault me ...
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113 views

Serialize bits from input/output pin with VHDL

The code below reads 40 bits of data sent in serial from a DHT-11 temperature/humidity sensor and stores the data in a 5 byte array of RAM. The code is: ...
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51 views

Expression and gate not gate output

The expression I came up with this circuit is A'B + A'CD + C, would the output change to AB' + AC'D' + C' since it is inverted? I'm assuming the D input compliments and cancels out? What would the ...
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50 views

What does “no design unit detected in this file” mean?

I got this error then I tried to add a source file. Can anyone tell me what this means? What should I do to correct it?
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46 views

Debugging simulation error in Xlinx for VHDL

I used Xilinx to simulated Logic And Gate, and it worked fine. I followed same procedure to simulate Half-Subtractor, but got stuck in between. When I checked Xilinx window for two codes I found ...
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2answers
100 views

Short ISE FPGA Workflow Tutorial

I'd be much obliged if somebody could point me to a short ISE workflow tutorial that shows how to implement a simple circuit using VHDL. As indicated, the tutorial should be short as I'm not ...
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1answer
89 views

Fixing 1 failing timing constraint in Xilinx

In the end of my project I have a timing constraint failure as follows : clk_in is the 100 Mhz system clock on ML507 I don't know why it is not meeting the ...
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1answer
62 views

Xilinx Design Summary

My project is finished and Xilinx gives lots of statistics in the summary like : How shall I evaluate these values, what can I say about them? What means what? Is this report good or bad? With ...
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232 views

Generate State Diagram from VHDL Code?

Is there a tool which generates State Diagrams from VHDL code? Also is there an easy way to indent VHDL code like in Visual Studio if I press ctrl + i it indents.
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236 views

How does VHDL handle bitwise operations?

I'm having a problem in some VHDL code I'm writing. I want to drive a signal with two other signals AND'd together like this: mysignal <= "010" and '1'; The ...