VHDL (VHSIC hardware description language) is a hardware description language used in electronic design automation to describe and design digital systems such as field-programmable gate arrays and integrated circuits.

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Trivial Example of multiple architecture for a single entity in VHDL

It is possible to separate entity and architecture as well as function and body function in package? If yes it is possible to put a collection of entities in a file and the related architectures in ...
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43 views

Crossing a single-cycle spike signal from a fast clock domain to a slower one

I have a 1-bit signal coming from a part of my circuit that is running on a 40 MHz clock. The signal is mostly 0, except it is 1 for a single 40 MHz-cycle every ~million cycles. Another part of my ...
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39 views

Verilog #parameter

What is equivalent VHDL code of these verilog lines: dfslckd_q <= #TCQ DFSLCKD; dfslckd_rising <=#TCQ !dfslckd_q & DFSLCKD; Signals are all bit (TCQ ...
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37 views

Test bench with IO file vhdl

Is the following test bench correct? I tried to use a text file with the content 00 01 10 11 to test an architecture of an and port. ...
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25 views

Nesting entities in VHDL (Altera Quartus)

I want to ask a question. I'm trying to simulate a cpu. I did my schema and basically there are two logical parts of the CPU. The first part is composed of a FIFO buffer, Cache memory for ...
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38 views

Using different compilers in same vhdl project

I am currently working on a mips microprocessor for one of my class using modelsim's tools. I want to be able to work on the same projet whether I'm at home on my windows pc or on the go with my ...
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40 views

Soft ECC or Built-In ECC for Single Port RAM?

I have to implement Hamming Code ECC to Single Port RAM and True Dual Port RAM. At the moment 128 bit HC ECC has been implemented but takes more resources. I know that there is Built-In ECC and Soft ...
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1answer
24 views

VHDL: What does STD_INPUT and STD_OUTPUT appearing in std.textio mean?

The package contains the following lines: file INPUT: TEXT is in “STD_INPUT”; file OUTPUT: TEXT is out “STD_OUTPUT”; For some reason these remind me of the standard input and output streams from my ...
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1answer
57 views

Benefits of using Altera IP in FPGA designs?

I've just started using Quartus to synthesize a VHDL design that I created a while ago. Inside of this design are things like DFFs, decoders, etc. I noticed that Altera has IP of its own with the same ...
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1answer
39 views

Is it normal that a clock divider made with ring johnson counter has a momentary rising when the period changes?

I have made a clk divider using a ring johnson counter with D flip flop in VHDL. The point is that the signal output makes a momentary and unexpected rise during a change of period. As you can see in ...
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1answer
42 views

How to load std_logic_vector array from text file at start of simulation

I am trying to model a memory which shall store instructions for a processor design. These instructions are stored in a text file as 32 bit binary words. At start of simulation all values must be ...
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40 views

Concatenation in port mapping

Using Vivado 2015.2, VHDL. Got a warning "[Synth 8-1565] actual for formal port b is neither a static name nor a globally static expression" ...
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13 views

Debugging timing issues with Quartus/ModelSim

I've just started doing VHDL design for FPGAs using Altera Quartus II and Altera ModelSim. As a starter project, I wrote a clock divider: ...
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52 views

Is it normal that a clock divider made with ring johnson counter has output Undefined if clk starts high?

I'm making a frequency divider and the easiest way is to use a johnon's counter with D flip flop. The point is that if I make the clk start high, the counter has undefined output, while if I make the ...
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1answer
96 views

fpga clock muxing

We are using an fpga with limited resources, the IGLOO Nano, so to implement all our functionality, we need to share a FIFO between two different vhdl components, which are using different clocks. The ...
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55 views

why use sum of product and not product of sum in programmable logic array and programmable array logic [duplicate]

I am confused why only SOP(sum of product) are used in PLA and PAL and not POS(product of sum)
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1answer
34 views

VHDL parallel execution of statements using variables

If a, b, c and d are variables, then this does not execute in parallel: a := b; c := a; But what about the following: ...
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1answer
57 views

Where can I find VHDL libraries? Is there a library for a PLL?

I heard in the following link that a V4 library about this topic exists, but I'm not able to find it anywere and to understand how to use it: Look at the last reply at this link
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36 views

Why can't ISE map the BTNRST pin of the Atlys board?

I want to use the Reset button of Digilent's Atlys board, but ISE can't map the pin because the site type is not an IOB (it's an IOBS, see section 6 of this question). As far as I can see there is no ...
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89 views

How to build a digital frequence multiplier?

I have to build a digital frequence multiplier (2*N). I have some idea about how to build a frequence divider (using flip flop d in sequence) but I have no idea about how to build a DIGITAL frequence ...
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2answers
66 views

How do I implement a tri-state buffer for a vector in VHDL?

I want to implement a tri-state buffer for a input vector, triggered by an enable vector, where every bit of the enable vector enables the corresponding bit of the input vector. Something like this ...
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1answer
50 views

VHDL 4-display counter on a Nexys 3 (0000 to 9999)

I'm triyng to implement a 4 display counter (0 to 9999) on a Nexys 3. However, when I load the bit file, all displays remain at 0. It seems like variables a,b,c,d; which control individual digits, ...
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28 views

VHDL TESTBENCH ERROR

I have to write a testbench code for a block having two inputs which were "X" and "Y" with output "A". The behaviour of the block is addition of two input signals, added value to be stored in "A". Two ...
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1answer
61 views

Does a package exist to carry out intense string manipulation in VHDL?

I am writing a VHDL code for a MIPS32. My idea is that for simulation purpose the testbench shall replace the instruction memory with a behavioral model which will read the program instructions from ...
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22 views

Unable to open XPS from PlanAhead(Xilinx ISE 14.3)

I am unable to open Xilinx Platform Studio(XPS) from PlanAhead. It shows me following error messages: I have not opened multiple sessions of it. I have also removed the write protection for that ...
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1answer
57 views

VHDL: value isn't assigned immediately

I asked a similar question here. I thought that that answer would be applicable to this code but I have the same problem. I have a ROM that runs at twice the speed of my CPU (left out all the ...
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1answer
45 views

VHDL delayed assignment problem

I want output to equal "11111111" on the first rising edge of the clock but it only happens on the second rising edge when I test the code with ModelSim. The code might look weird as a simplification ...
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1answer
33 views

VHDL “casting” a constant into a signal?

Is there a way to cast a constant value into a signal in order to send it into a function's parameter ? Let's say I have this function: ...
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33 views

VHDL multiple constant drivers

I'm trying to initialize all elements in an array to zero, but I also need to save values to this array after operations like an addition. ...
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1answer
102 views

Fpga Crossing signals between related clock domains

I have an fpga design with two clocks, one is 54MHz and the other is a divide-by-4 clock of the 54MHz, this is 13.5MHz clock. The 13.5MHz clock is generated by dividing the 54MHz clock in vhdl, and ...
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1answer
80 views

Is it possible to detect high impedance at FPGA input?

I am using a FPGA development board which have neither pull-up nor pull-down resister at the input side. VHDL code that I am developing has to detect either logic zero or logic one and to do ...
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2answers
76 views

How to trigger at both edges in VHDL?

In Verilog if we use always@(clock) we can trigger a module at both rising edge and falling edge. Is there any method to do the same in VHDL.
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51 views

Process statement in vhdl

I have a very basic question here. When I learnt Processes it was said the statements occur sequentially.This is what I believed in. In the NCO process image file,there is proof for it. fword is ...
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1answer
32 views

Type bit does not match with the integer literal while converting integer into bit_vector

In VHDL, is there any way to convert an integer into bit_vector of length of 14? Currently, I am first converting the ...
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1answer
28 views

VHDL signal assignement

Is there any difference between : Type word is STD_logic_vector(15 downto 0) And Signal word:STD_logic_vector(15 downto 0) ...
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1answer
35 views

What is the difference in assigning output before end process and after end process in VHDL

I have written a code to check the difference in assigning output before "end process" and after "end process" in VHDL. And the results of the simulation I have posted with it. What I found is ...
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46 views

Component Not Found VHDL XILINX ISE

i know this might be a very simple question . i have to simulate some delays for various adders in ISE Suite . ( i'm a little familiar with vhdl concepts but ISE Environment , not at all ! ) this ...
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1answer
78 views

Why rising_edge is only used to detect clock input?

In VHDL rising_edge is used to detect signal transition from logic zero to logic one. In almost every vhdl sample codes that I referred rising_edge is only used to detect logic zero to logic one ...
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37 views

VHDL using flow control vs minimization

I am currently designing a mips microcontroller for a class. I am now working on the control unit for the microprocessor and I am wondering if I should use minimization vs using flow control (if, ...
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1answer
55 views

VHDL code works well in ModelSim and strange behavior in Altera FPGA

I'm trying to understand a strange (for me) behavior of a simple VHDL code. I have realized a stupid code that works well in ModelSim and doesn't work in a real FPGA (Altera MAX 10). ...
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53 views

VHDL: couldn't implement registers for assignments on this clock edge

I'm getting the following errors: Error (10822): HDL error at pwm.vhd(15): couldn't implement registers for assignments on this clock edge Error (10822): HDL error at pwm.vhd(18): couldn't implement ...
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36 views

obtain the value stored in array

i am working with spartan 3 xc3s5000 and 14 bit adc(lt2255). I am giving a analog signal to adc which is connected to spartan . I want to store the values of samples(sample done by adc of given analog ...
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56 views

VHDL how to make a process with sensitivity list wait?

I'd like a process to listen to changes in a signal, but not before 20 ns. How can I achieve that? It doesn't seem possible to use wait statements in such a process, which makes sense since is has a ...
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1answer
37 views

PlanAhead 14.7 multiple runs issues

My project in PAhead 14.7 have 6 different synthesis run and 6 implementation runs. Each implementation run have her own parent synthesis run. The differences between synthesis runs are some generic ...
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34 views

VHDL Counter does not update when desired

For a project I am working on, I require a counter whose value increases as soon as the increment control goes high (i.e. on the rising edge). However, I have had trouble implementing this in VHDL. ...
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1answer
57 views

VHDL - Does signal ever get assigned in the same clk cycle?

This is my simulation I'm assigning different values to btnin my testbench ...
2
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2answers
255 views

What is the use of 'event in vhdl?

In vhdl code for synchronous counter, I replaced following part ...