VHDL (VHSIC hardware description language) is a hardware description language used in electronic design automation to describe and design digital systems such as field-programmable gate arrays and integrated circuits.

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Array of strings in VHDL

I would like to declare a type which is array of strings in VHDL like and made signals using the new type as: ...
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How to use an array type as parameter of a Procedure

I want to read input values from a file and store them in an array I have defined a custom array type in a package as : ...
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22 views

Write/read 2d data from DDram from the arm on the FPGA?

I having some problems with testing the example code, which the Vivado sdk has available for testing my FPGA implementation. The implementation can be viewed here : ...
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45 views

Memory Interface with a Multiplexed Address/Data Bus

I want to implement a memory interface in VHDL between an FPGA and a processor. The address/data bus is a 16-bit multiplexed bus with an ALE, write protect and BusWait. According to the NVIDIA Tegra 3 ...
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35 views

Moving a large dataset from the PS to PL on a zynq device?

I am at the moment trying to interface with DRAM on my Xilinx Zynq device such that I am capable of moving a large amount of data from the processing system (PS) side to the programmable logic (PL). ...
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22 views

VHDL - how to get signals from inside a uut in a testbench? [duplicate]

I am writing a testbench for a component I created. In order to debug it, I would like to write the value of some of the internal signals to a textfile. I know it is perfectly possible to write the ...
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3answers
227 views

Why would you want to write to a file when writing VHDL? [closed]

I have never so far been in the need to write to a file when making a testbench in vhdl. Seeing the signals being plotted has always been enough so far. Could someone please give me a case or the ...
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40 views

Model Sim Software with VHDL, What is Wrong?

I wrote the following VHDL Code: ...
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40 views

use of ISD4002 SPI with FPGA

I am trying to build a circuit that would be some kind of INTERCOM and will be controlled by FPGA (cyclon 2 by altera ) . Because I need to have multi voice channels I choose ISD4002 because in my ...
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34 views

Adder tree with 4:2 compressors. What to do with Cout?

I'm trying to build an adder tree using 4:2 compressors. I want to add together 16 bytes at total, so I figured that a possible architecture for that tree is the following: Each 4-Byte adder has 3 ...
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1answer
52 views

Pipelined Radix-2 DIF FFT SDF Architecture

I want to implement Radix-2 Single-path Delay Feedback (SDF) Decimation-In-Frequency FFT with Pipelining in VHDL. I am trying to understand the below architecture as described in this MIT ...
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1answer
56 views

What is VHDL used for?

I'm learning digital electronics and I met with VHDL. I know it's hardware description language, but once I learn syntax and how to write code, what can I do with that code? Essentialy, what is VHDL?
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70 views

simple counter in VHDL

I am trying to write a little counter in VHDL using the two process methodology. However it is not working. Could someone explain me why? ...
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42 views

vhdl code to do ramp-up & ramp-down for audio

I'm trying to learn more about VHDL and audio. I generated sine wave data using matlab. I want to generate three different type of audio output so I thought of doing ramp up and ramp down for my ...
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1answer
50 views

Why this concept in VHDL doesn't work?

I want to make a simple processing element for calculating the absolute difference between two 8-bit words. However, this element may be used as part of an array in order to speed up the AD ...
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1answer
45 views

Wrong RTL schematichs of adder tree

I write a VHDL code for an adder tree, with a parametrized number of vector. It's only for Learning purpouse, so I dind't implemented the carry between the block, I simple created a larger bus so I ...
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1answer
61 views

VHDL: A function to determine array length

SOLVED!!! I'll leeave the questions, see below for the solution. In a VHDL project, I want to initialized an array that have a certain dimension, and I want this dimension is derived by a function. ...
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1answer
36 views

Problem VHDL process maintaing a signal modified

I am writing a VHDL code of a simple counter which receives as an input a number and that is a time in ms, and a 50 MHz clock, for example if 200 is received it has to count 200 ms so 200* 50e3 ...
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43 views

VHDL - loop counter bug with SPI protocol

I want to write a simple reader from SPI data, to read 1 byte and transfer it to another block. I used the following code : ...
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2answers
68 views

VHDL loop not updating output

Why won't the value of output changes? It has been clocked and the inner loop should update? In the simulation, the output's value is always 9. Please help what I may be missing. I would like the code ...
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1answer
56 views

VHDL iterate over a “list” of external names

I'm using external names introduced in VHDL-2008 to access a bunch of signals (let's say 1000) in a design hierarchy with many levels. ...
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52 views

Procedures or structural architecture - which is preferable for synthesis in VHDL?

I'm writing VHDL code which I would like to implement on an FPGA. Currently I have written separate architectures for adders, multipliers etc and combined them all using a structural architecture in ...
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1answer
43 views

Synthesisable alternative to the wait statement in VHDL

I'm writing VHDL code for a filter which I want to implement on a Spartan 6 FPGA. When I tried running a testbench for my code, one of the processes entered an infinite loop, so I added a wait ...
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51 views

Xilinx ISE warns that a signal is trimmed since it has a constant value of 0, but the signal is used within my code

I have created the following VHDL module, which is used as an up/down counter. ...
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1answer
56 views

Clock port and any other port of a register should not be driven by the same signal source

I get this Warning from Altera Design Assistant for the below: Clock port and any other port of a register should not be driven by the same signal source Critical Warning (308012): Node ...
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2answers
81 views

VHDL port map: connect only some bits of a vector

My design has a entity for configuration which returns std_logic_vectors (length defined by generic - normally 32 bit) ...
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1answer
46 views

Altera Quartus Design Assistant Critical Warnings

I get a number of Critical Warnings with respect to lpm_ff and lpm_counter: Below are few: Rule A102: Register output should not drive its own control signal directly or through combinational ...
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76 views

can't solve latches

I would like to ask if someone could help me with some latches in my desing. I am working with an aes encrypt core taken from opencores and I have described in vhdl the surrounding system to ...
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40 views

How to generate IP cores with access to hardware in vivado

I am looking for some guide on how create an IP-Core in Vivado which make integrate the hardware. I want to create a IP-Core which should act as an driver for VGA port. The problem is how to create it ...
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101 views

Dual port RAM on Altera and Xilinx FPGA

I have always managed to synthesis a 256 x 32 bits dual-port RAM (not true dual port RAM) in Xilinx ISE with just 1 x 18K BRAM. The example code from here was used: ...
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1answer
95 views

FPGA Frequency Divider

I need to design frequency divider from 50MHz to 200Hz using FPGA. I'm using Xilinx and the language that I used is VHDL language. I got stuck because I can't get the output. So, anyone can help me? ...
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1answer
28 views

non static error in Precision RTL

I'm writing a VHDL code for an integer to float converter using variables. I have simulated it and the results match expectations. However, when looking to compile and synthesize using Precision RTL ...
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38 views

Failure: (vsim-3808) Incompatible modes for port

I am attempting use modelsim to simulate a peak detector and am having trouble with the simulation of the handshaking protocol between two modules: dataGen and dataConsume. I am certain that the code ...
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1answer
27 views

Select output from Generate in VHDL

I have a component, which is added several times by a generate command: ...
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2answers
111 views

Simple binary adder works only partially

LATER EDIT: 1. I've also investigated visually the Kintex7 device after implementation (i.e. interconnections, etc.) and everything looks OK - no connections that would indicate things would not be ...
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Event Debug Mode error when performing mixed Verilog/VHDL simulation in VCS

I am getting the following error: ...
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1answer
67 views

shift register problem in VHDL

I'm designing a 56 bit shift register to store the bits coming in. In my system, 8 bit data is keep coming in from a generator and I need to output the maximum value detected with 3 bytes either side ...
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1answer
44 views

vhdl - convert a signal to integer

I have looked around on SE but couldn t find anything that worked properly for me. I am looking for a way to convert a 4 bit signal_vector to an integer. However I do calculations on signals as well. ...
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1answer
65 views

signed maximum detector vhdl [closed]

Sorry I've asked a similar question but I didn't get a answer so I posted this question I'm currently designing a maximum detector in VHDL which is part of my homework. The whole system consists of ...
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36 views

VHDL - difference between concurrent statements and sequential statements [duplicate]

I'm fairly new to programming an FPGA using VHDL and I have a doubt. I understand that concurrent statements (the ones written outside the process) are executed simultaneously and sequential ...
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1answer
87 views

Replacing if-­‐statements with a case statement

I would like to know how to replace an if statement with a case statement. The if statement ...
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41 views

Read file in hex vhdl

I'm designing an ALU that does several logic operations. I created a testbench and all the function works fine. Now I want to make the testbench read from a text file and write the value in a ...
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2answers
107 views

VGA driver not working

I am at the moment trying to make an vga driver for my FPGA, but something isn't going right, and I can't seem to find out what is going wrong... The code is based on this code example: Example VGA ...
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1answer
148 views

How to generate sound in VHDL

I'm new to FPGA and VHDL. I'm working on lab practical and for the practical we were already given file that has an I2C codec and the basics for the codec registers were already done but I found the ...
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1answer
54 views

Design of carry chain on Cyclone IV

I am trying to implement carry chain with Cyclone IV FPGA. I will use carry chain as delay line so here is quick explanation of my program: When input signal "cin" goes high, signal starts to ...
3
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1answer
46 views

Modelsim - Weird verification problem with DDR and Xilinx UNISIM

I am doing verification of VHDL component using OVM and ran into serious problems. I have found that problem is in one specific component and created environment specifically for it. It's a RGMII to ...
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1answer
52 views

Design of carry chain — Problems with clock's in design

I am trying to implement carry chain on FPGA and i want that resault from each block is written in register. Each block is 10 bit adder with following code: ...
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45 views

Error in use of COMPONENT (VHDL)

I've designed a simple adder using "FOR GENERATE" in VHDL. It returns this error: " main is not an architecture body for full_adder in library WORK." I've defined a COMPONENT named FA to be a ...