VHDL (VHSIC hardware description language) is a hardware description language used in electronic design automation to describe and design digital systems such as field-programmable gate arrays and integrated circuits.

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FPGA - Routing Diagram - what are the physical parts

In Xilinx ISE I've generated a very simple piece of hardware and when looking at the routed design I'm unsure what some of the parts are and require some clarification on what some of these parts are. ...
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23 views

How to Update/Change EDID of BITEC DVI DAUGHTER CARD

I am using Cyclone 3 Dev Kit with BITEC HSMC Digital Video Daughter Card. I want to use 1440x900 as resolution but the EDID on the daughter card is limited to 1280 X 1024@75 Hz and 1920 X 1080@60 Hz, ...
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64 views

VHDL - address comparison yields wrong result

I am developing TS-CAN1 emulator on Atmel's ATF1508AS. One part of an application is an address decoder implemented as follows (only interesting parts are left): ...
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2answers
65 views

Read decimal value of a 4-bit binary input

I am quite a rookie in the VHDL world, but I seem to have hold of the basics. Atm I am working on a project, which involves me to take a 4-bit binary input (switches), read this value and convert it ...
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107 views
+50

How to convert an array of pixels to jpg or png?

I am doing image processing project in VHDL. And as output am getting array of pixels (32 bit each). I want test this output data visually, for that it must be converted to image either png or jpg or ...
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34 views

cdma implimentation in vhdl

I'm novice in vhdl coding. I'm implementing CDMA. The transmitter part has the eight bit input data corresponding to a particular user is converted into serial form by an eight bit PISO. The PISO ...
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2answers
92 views

VHDL Plus operator `+` and Downto syntax

Considering variable a and b as STD_LOGIC_VECTOR (31 DOWNTO 0) we have ...
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2answers
61 views

PN sequence generator using linear feedback shift register in VHDL

I got a code for PN sequence generator using linear feedback shift register in VHDL. I am using 1010 as a initial seed but in the output all the four PN sequences ...
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52 views

VHDL: How to convert Bit_Vector to Std_Logic_Vector?

I want to move data from a "Bit_vector" to "Std_logic_Vector". For that, I want to convert Bit_Vector into Std_Logic_Vector. Please help me for the same.
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178 views

Conversion from VHDL to sysgen block diagram

I made my own custom board that contains a clock oscillator to drive an FPGA. I wrote some VHDL code. The script simply re-routs a 10-bit input (SIGIN) to the 10-bit output (SIGOUT) on the rising edge ...
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1answer
56 views

VHDL process causes errors

I'm new to VHDL so I just have a question to ask about why this produces an error. I have an ALU defined in VHDL: ...
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118 views

Proper clock generation for VHDL testbenches

In many test benches I see the following pattern for clock generation: ...
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1answer
84 views

How to use IO Buffer with defined location in VHDL?

I am tring to program the ADF4158 PLL Synthesizer with SPARTAN 6 FPGA using Microboard LX9. I studied VHDL for a semster 4 years earlier, and no practical use after that. So I need some experts ...
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42 views

xilinx create schematic of top modul with lower level moduls

I have a top modul VHDL source file, which has a few instances of lower-level modules (VHDL) and signals which connects these lower-level modules. How can I generate a schematic for this? I mean, I ...
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1answer
77 views

cannot fix: warning signal clk IBUF has no load please help!

I have been trying to design a simple Hardware design to controll another board that powers a set of LEDs for a stage drum lighting system. I cannot for the life of me figure out why I am recieving ...
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1answer
44 views

What is the definition of unsigned() function in VHDL?

I am unable to find the function signature of unsigned() function in vhdl. what types does it accept as an argument?
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1answer
58 views

Problem getting VHDL syntax correct

I am trying to learn VHDL prior to returning to school. I have been using the text Digital Design with CPLD Applications and VHDL ISBN-13: 978-1401840303 Other references are: ...
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1answer
58 views

Design up counter in VHDL using generate statement

I need to design an 8 bit up counter in VHDL using T flip flop and generate statement. I know how the counter works, but I am not able to design it in VHDL. The main problem is "using generate ...
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1answer
52 views

What is the difference between a static and non-static expression in vhdl?

suppose if I have two signal declarations as follows signal x:std_logic_vector(1 downto 0) := (others => '0'); signal y:std_logic_vector(1 downto 0); does ...
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81 views

VHDL code and unintended latches

I am working on coding a Regsiter a1 with input signals b1,rst and wra1 the register ...
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1answer
89 views

Shift Register Vs Multiplexer

I am not sure about an implementation. I've a multiplexer 8 input, 1 output and 3 select signal. One of these selects signal sequentialy acquires all value of a bit vector. Now I can choose 2 way. ...
2
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1answer
81 views

VHDL How to Design a Screen (Frame) Buffer

I am trying to use a screen buffer to store, change and output the bits of a video data to the DVI transmit interface. I am using Altera Cyclone III development kit. I will be using 1440x900@60Hz ...
2
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1answer
44 views

VHDL - Quartus II inferring latches on circuit

My circuit is based on a state-machine. I checked it and it's working fine, the only issue is that it's inferring one latch per flip-flop (The state machine has 11 states and the circuit is one-hot so ...
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50 views

VHDL - Flip Flop inferring on a signal

I have to design a circuit to count up to a number and return to zero. It must have a carry signal (which I named a_o in my circuit) as flag to show that the ...
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1answer
62 views

Using a Counter to Determine next MSB position in polynomial division

I am working on implementing a polynomial divider the operation is as follows: Check MSB of Numerator: if 1 XOR with Denom then shift Denom right if 0 Num is the same and Denom also shift right When ...
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50 views

Binary/Polynomial division on FPGA implementation

I am beginning the implementation of the polynomial binary division algorithm now as I understood i will be checking the MSB bit if 1 to XOR and shift the sum if 0 I will only shift. What I am not ...
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1answer
92 views

Signed Addition of two std logic vectors while looking for overflow and carry

I have what I think to be a working implentation for finding the sum of two signed 32 bit (std_logic_vector) vectors in which I chose to expand the result to always have 33 bits so as to preserve the ...
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2answers
56 views

What does delta stands for in ModelSIM?

I ran a simulation for a combinational logic circuit with 8 inputs, 4 outputs inside MODELSIM. When I view the simulated waveform everything looks fine, however when I export result to a list file ...
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VHDL: Simulating Delay for ISE UNISIM components

I have extracted VHDL source of my design from Xilinx ISE. It uses UNISIM library to model Look-Up Tables and Flip-Flops and other components. When I simulate my VHDL design (a combinational circuit) ...
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2answers
62 views

Races in sequential circuits VHDL

Do I need to be aware of races while writing code for sequential circuits in VHDL ( I use ISE Design Suite ) ? If I do not, what is the matter that solves the races issue instead of me ?
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85 views

quartus signaltap not accurate?

I am using Quartus SignalTap to debug my FPGA design: I always been persuaded SignalTap is not accurate !! This is what i found: I monitor the reset signal with SignalTap :Reset toggles around, ...
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1answer
92 views

The timing-driven placement phase encountered an error

Could someone explain inexperienced VHDL coder what this error message trying to tell me in simple words? I found a similar question here, but here was no answer to it: ...
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1answer
46 views

Timing/buffering issue with Digilent's EPP on Basys2?

I have a Digilent Basys2 FPGA, and I'm implementing the EPP interface described in http://www.digilentinc.com/Data/Products/ADEPT/DpimRef%20programmers%20manual.pdf. This allows a program called ...
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72 views

Using one channel from adc (pin connections) [closed]

For a heart rate calculator project by using Basys2 and VHDL, I am trying to connect ADC0808 in order to get 8bit digital output from my pulse sensor's output. However, although I designed the circuit ...
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1answer
71 views

Functional and Timing accuracy of an RTL Model

I am sometimes really confused by the abusive use of jargon in EDA/VLSI design articles and books. With no precise definitions, its upto the reader to make interpretation which is very ambiguous and ...
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66 views

FPGA based theremin , is possible?

I remember a while ago , i saw some Digital based Theremins circuits from glasgow university... http://www.theremin.info/-/viewpub/tid/10/pid/65 would it be possible to make a theremin by using an ...
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1answer
71 views

VHDL RS-232 Receiver

I have been trying to design an RS-232 receiver taking an FSM approach. I will admit that I do not have a very well-rounded understanding of VHDL, so I have been working on the code on the fly and ...
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1answer
53 views

Integer to std_logic type conversion

I want to assign the value of a generic that is an integer to a signal which is a std_logic type. My generic can take only two values, 0 and ...
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56 views

Why does this adder need two clock cycles (two pushes of the button) to display a result?

I'm implementing a simple adder with carry out in VHDL on a BASYS2 board. This is the code below: ...
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2answers
71 views

How to best synthesize a systolic circuit on FPGA?

I am developing a parameterized systolic circuit in VHDL, using generics. It exhibits regularity in 2 dimensions. I am about to synthesize it on Xilinx FPGA. I suspect it is worth informing the ...
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1answer
102 views

LFSR Using D Flip Flops

I am fairly new to the VHDL language and I will admit that I primarily use it for educational purposes. I have been attempting to design a data encryption circuit using D flip flops. Obviously, an ...
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1answer
100 views

LED PWM controller

I want to create Led PWM controller and I tought it is easy but one line in my code generates more warnings than all my previous little projects. Here is the code: ...
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1answer
56 views

Implementing a counter in VHLD with edge triggered clear

I'm still giving my first steps learning VHDL and after a couple of days I could not yet find a solution for this problem. What I'm trying to do is to implement an LCD controller on an Altera MAX II ...
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45 views

Balanced partitioning turned off?

I am programming with a CPLD of Lattice Semiconductors (ispMACH 4000ZE) and the program ispLEVER Project Navigator. I want to implement a quadriture counter. First I implemented the counter only for ...
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6answers
692 views

What is the difference between testing and verification?

Every textbook I've seen makes a big deal of the fact that testing and verification are two different concepts. Yet none of them provides a clear (or clear enough to me, at last) distinction. To ...
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2answers
181 views

UART Receiver glitches

I encounter problems with my UART receiver module. It is supposed to work at 9600 bauds without parity bit and only one stop bit. The problem is that my UART misses some characters (or to indicate ...
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2answers
110 views

Signal(s) form a combinatorial loop VHDL

I was trying to implement Dual-priority encoder but I get following warnings during synthesize: WARNING:Xst:2170 - Unit prEnc : the following signal(s) form a combinatorial loop: done, first<3>, ...
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1answer
104 views

VHDL delay mechanism

I have difficulty understanding how the delay (mainly inertial delay: AFTER) mechanism works in VHDL. I'll start with this: target <= waveform AFTER 3 NS; As ...
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1answer
39 views

Component instantiation in VHDL

I need some help with component instantiations (port maps) in VHDL. I have a 16 bit Full Adder which I want to import in my ALU, and it should trigger when the ...
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47 views

Using explicit registers in RTL designs

Is it a good practice to use explicit register IPs in RTL designs? For instance, having separate IPs for each type of register and instantiating them in the design instead of coding them on-the-fly. ...