VHDL (VHSIC hardware description language) is a hardware description language used in electronic design automation to describe and design digital systems such as field-programmable gate arrays and integrated circuits.

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22 views

Histogram Graph in ModelSim Simulator

I have a Memory (Register Bank), this bank has 255 registers that each register contains a 16 bit number, type of registers is STD_LOGIC_VECTOR but there is no problem if I should convert them to ...
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37 views

Open a picture and read its Pixel Values

I want to calculate the Histogram of an Image is grayscale color mode I have designed a memory and a Calculator of Histogram value, now I want to get Pixel values and put them in Calculator as Input ...
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33 views

LMS (Least Mean Square) Algorithm

We are designing LMS algorithm in vhdl. We want to know how each value of X(n) comes. We have been told that X(n) is a complex number, which is the input to equalizer which comes AFTER TRAVELLING ...
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51 views

future VHDL standard [on hold]

When VHDL-2008 was available many people were wondering how to convert records to vectors. While there is no automatic solution, there were pointers to a new standard revision. However, when looking ...
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37 views

VHDL If-Else Condition Equivalency Confusion from ISim

Hello I am using a modified version of the VHDL I2C Master from the EEWiki page. In my logic controller block I am looking for a particular data byte to be read back from a slave device and transition ...
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2answers
63 views

VHDL:CLOCK DIVIDER with duty cycle

I want to generate a 15MHz clock from a 60 MHz clock. The 60 MHz clock has a duty cycle of 50%. The output clock of 15 MHz must have 25% duty cycle. How the following code needs to be modified to vary ...
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2answers
45 views

Quartus 2 VHDL Clock Frequency Divider: can't determine definition of operator “+”

I'm extremely new to VHDL and trying to make some easy projects such that I learn the basics and syntax. I use Quartus 2 at home and ISE 10.1 at the school computer. I wrote exactly the same code in ...
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3answers
55 views

Decoding in VHDL - Bit masking

I'm searching for the optimal way to do this in VHDL: ...
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1answer
44 views

VHDL - Issue with simulation of testbench - Modelsim PE Student 10.4

I'm very new to VHDL and got an issue with the simulation time in Modelsim PE Student Edition 10.4. I wrote some files for a RTL-model such as multiplexer, demultiplexer and register. To test my ...
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1answer
55 views

Loop for two binary values in VHDL

I'm trying to write a loop for two binary values that repeat periodically at a specific amount of time that goes indefinitely or until a certain condition is met. Here is what I have wrote (below), ...
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1answer
48 views

Non constant real valued expression not supported

We are implementing Least Mean Squares (LMS) algorithm. If we add line 5 and line 6 (as indicated by comments below), we are getting an error right from line 1 (as indicated by comments) that non ...
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18 views

VHDL - QUARTUS compilation problems - Warning (332068): No clocks defined in design

I'm having some trouble compiling a design I made in quartus. When trying to compile I'm getting the following warning messages: I can see that this indicates on a problem with the 2 inputs of the ...
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48 views

quartus can't find my clock

quartus just can't seem to find a clock in my design. all google's searches came up empty. here is my top level: ...
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2answers
79 views

How to read a text file using vhdl

I am working with altera QuartusII version 13.I want to write a program that reads data from a text file and outputs this data serially at every positive clk edge. I have tried writing a code,but it ...
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46 views

Syntax Errors in VHDL-AMS

The following code results in the error under determined model and the simulation breaks off. How should I remove the error. I have coded in Hamster Vhdl. I would appreciate any help. ...
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0answers
90 views

Is there a 2D simulator for digital logic circuit like this? [closed]

To add my question because it might not be clear to some readers, what I would like to have is the 2D animation represented by components like gates, multiplexer, etc. that some tools are already ...
0
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0answers
41 views

VHDL: Updating global variables of entity from the sub componets

I am trying to implement a cipher in VHDL. I am beginner to VHDL. In my design there is a main entity and several components that are called from this entity. Is there any way by which I can refer ...
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2answers
41 views

VHDL: Getting a part of the actual input in a variable

I am writing a VHDL code for implementing a cipher on FPGA. I am passing a hexdecimal value to a signal as an input input : in STD_LOGIC_VECTOR (63 downto 0); ...
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1answer
28 views

VHDL Compile Error saying "Type of VARIABLE is incompatible with

I am pretty new to the world of VHDL programming. In a simple code, I am trying to make a simple BCD adder. I assigned/declared variable as following ...
3
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3answers
75 views

How to speed up Modelsim simulation

How can I get Modelsim to run faster for simulation rather than something in the picosecond range (time interval)? Are there any other methods for speeding up simulation? It takes 45 minutes to get ...
3
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1answer
68 views

VHDL - assigning array signal in a loop generates side effects

I do not understand why the following vhdl code does not simulate as I think it should. test_pipe_1(0) is assigned at process pr1, but the simulation (both Aldec and GHDL) shows test_pipe_1(0) being '...
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0answers
37 views

STD_LOGIC addition in vhdl arithmetic

Having 11 inputs of type STD_LOGIC in a circuit(c0,c1,c2,...,c10) , I need to calculate Σcin. It can be calculated using a custom design but I want it to be architecturally independent. so how can ...
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2answers
52 views

GUI for writing HDL and viewing simulation? [closed]

I am a software developer and I'd like to code for FPGAs. Prior to buying an FPGA I thought it might be better to obtain a simulator where I could practice my HDL and see whether I can get the hang of ...
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2answers
48 views

VHDL if generate in the preamble, is it possible?

Is it possible to generate different set of constants in a vhdl preamble using a kind of "if generate statement"? For example I was trying: library ieee; use ieee.std_logic_1164.all; ...
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26 views

Altera Quartus - structural architecture

I am relatively new to VHDL and I am supposed to use structural architecture and Altera Quartus on my assignments. But, I have noticed that the Unisim library is not compatible with Altera Quartus, so ...
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1answer
43 views

Increment counter by pressing a button with output to leds

I have this simple code which doesn't behave as it should and can't figure out why. ...
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1answer
65 views

Is it possible to see how much logic an IP core uses?

Is it possible to see how much logic an IP core uses in Vivado? I just found out that one of my variable might create a giant mux. I want to know how much logic this mux uses, so I could document it ...
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23 views

Assign bits of std_logic to output leds

I want to read the bits of an std_logic variable and assign each bit to an output, such as an led. How can I achieve this? Perhaps ...
0
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1answer
32 views

Problem with WHEN - ELSE

I am new in VHDL. The code below doesn't work for some reason. The D0 and D1 are switches and when I added the D1 it stopped working. clk_Centi is pointing to an LED. ...
0
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1answer
61 views

does this ensure i am reading from the ram?

I at the moment trying to reverse engineer something i made a long time ago but never understood why it is running so slowly. I have a Zybo board, with an Zynq 7010s chip ons which has dual cortex-...
0
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1answer
54 views

Write to reserved registers in I2C

I'm trying to get a MPU-9150 motion sensor running with my FPGA-Board. The problem is that my I2C-master library doesn't support writing single bits. According to the Register Map there a for example ...
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2answers
50 views

Unconnected port warning on reset port in asynchronous register in Vivado

I've been trying to synthesis this register model. Its simulation in ModelSim is correctly fine. However, when synthesis, it always yields warnings: [synth 8-3331] design register1 has unconnected ...
0
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2answers
57 views

CASE plus WAIT statements

I'm developing a simulation model of a component that I need in my design. To make it fast and simple I decided to only create it in a behavioral manner (eg not synthesizable). To do so I'm using a ...
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1answer
57 views

Asynchronous JK Flip-Flop in VHDL

and thanks for your help. I wrote the code for an Asynchronous JK Flip Flop in VHDL, the code is the following: ...
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1answer
56 views

found '0' definitions of operator “*”

I'm tryinig to implementan IIR filter like: y(n) = 2*y(n-1)-y(n-2)+x(n)-2*x(n-6)+x(n-12); My vhdl code is: ...
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2answers
32 views

VHDL - displaying 4 digits on 7-segment display

I wrote a vhdl code, that would display 4 digits on cpld 7-segment displays. I used a state machine to select the display, and with ... select instruction to select a set of bits given to the current ...
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0answers
37 views

What does a conversion imply in VHDL

For few days I've been wondering why an std_logic_vector type can't get an unsigned/signed type. My question is : does this constraint only comes from VHDL syntax and though this is implicitly needed ...
0
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1answer
35 views

Issues with combining counters for traffic light

I am trying to implement something as simple as the controller for one single traffic light by using two counters (one for green/red and one for yellow), but I don't seem to be getting the timing ...
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3answers
109 views

Are there any standard FPGA internal buses?

Are there any standard FPGA internal buses? I've always used some sort of bidirectional bus between my internal blocks, but is there a standard way of doing this?
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1answer
55 views

VHDL blink leds for changing bits in vector signal

Suppose there's two SDT_LOGIC_VECTOR signals A_READ and A_OUT, both 8 bits wide. A_READ is updated by some process at random intervals. A_OUT is connected to 8 LED's. I want to blink a LED for each ...
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44 views

VHDL optimization: shift register with reconfigurable outputs

I am looking for some advice to optimize my beginner's design. Logic needs to be implemented on a CPLD that is able to : receive data from 4 parallel in/serial out shift registers through 4 serial ...
0
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1answer
43 views

ModelSim simulation won't advance

I am trying to simulate a testbench on ModelSim, but when I run the simulation, it never advances in time. The delta does not increase, either. Are there any useful tips for debugging in a situation ...
0
votes
1answer
48 views

Why the output signal from the counter seems to be not driven?

I've written a memory module for an application. In order to address each memory location a simple 6-bit counter is used. I have tested most of the components (including the counter) and they seem to ...
0
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0answers
23 views

Flashing NIOS II with SPI at boot

I have a Altera FPGA, which is configured (programmed/flashed) at startup by SPI from a processor runing embedded linux. If I put a NIOS processor in the fpga, is it possible to flash the NIOS ...
0
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2answers
92 views

What the FPGA dev board to choose: Xilinx or Altera? [closed]

I'm very new to programmable logic world and have never worked with any HDL languages, but I certainly want to get started with FPGA. At the moment the goal is to develop/simulate simple 8bit CPU and ...
0
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1answer
79 views

VHDL - 10% Duty Cycle

I need to generate 500Hz from 50MHz clock frequency. I already got it. My problem here is how should the code to be adjusted if I want to change the duty cycle to 10%? Thank you. ...
0
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0answers
67 views

Array of strings in VHDL

I would like to declare a type which is array of strings in VHDL like and made signals using the new type as: ...