VHDL (VHSIC hardware description language) is a hardware description language used in electronic design automation to describe and design digital systems such as field-programmable gate arrays and integrated circuits.

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blinking a display using trigger

I've been banging my head over this for a while now, basically I have this display driver that in normal conditions would update a seven segment display continuously. What I would like to do, and I'm ...
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91 views

Sexism in hardware engineering [on hold]

Documentation about sexism in the STEM field (Science, Technology, Engineering and Mathematics) is largely documented and readily available through Google. Furthermore, sexism specific to IT, ...
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1answer
41 views

ise complaining index out of range, but it seems to be in range?

I'm righting a vhdl module that calculates the LPCs from incoming DT samples. My ise editor is complaining that my index is out of range. Is there any reason anyone can see that it should be ...
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37 views

8 Bit Register in VHDL

I am new to VHDL programming and am currently designing an 8-bit register as shown in the picture below: Below is my VHDL code for the design: ...
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19 views

turn on led using external light dependent resistor (LDR) with nios ii and qsys design

I want to use qsys and nios ii to design a system that uses an external ldr to turn on led on an altera fpga.how can i go about this, what are the components i need in my qsys design and how to ...
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29 views

Using signed() conversion in VHDL

I was wondering why I am unable to use this in my logic Y<= '1' when (signed(A) < signed (B)) else '0'; Y, A, and B are all std_logic_vectors. I am using ...
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1answer
54 views

What are some things that can be done in VHDL but not in verilog and vice versa?

VHDL and Verilog are quite similar but do not have the same features, there is certainly a massive overlap though. What are some things which are easier to do in VHDL but not so easy or even ...
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1answer
58 views

SystemC vs HDLs

I am currently involved in a university project to implementing a processor of an existing instruction set. The idea is that by the end of the project I should be able to synthesise this design and ...
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1answer
83 views

Convert C to FPGA

I'm new to programming for FPGAs so I was recommended to use some available C/C++ to VHDL translator. Problem is, there are tons of information out there and almost all good programs need an ...
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3answers
108 views

How can I view, debug, or analyze data being input to my FPGA?

I'm working with a Xilinx Spartan6 on Digilent's Nexys3 board. I've also purchased their PmodMIC so I can try to get some audio data onto my board to perform some signal processing. The ...
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68 views

7 Segment display driver issues

I have this code for driving a seven segment display for hex. From my understanding its logically correct, but when I try and run it on my Nexsys 3 board I never get the correct output, it seems that ...
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4answers
599 views

How is this simple counter implemented on an FPGA without a clock?

As part of an assignment, I must create these blocks that tie in to a larger top level module. (there are more blocks not pictured). I have everything working fine, except this UP/DOWN counter ...
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57 views

VHDL code Process

Question: change z <= y AFTER 30 ns to z <= y after 15 ns why after the change above ,the value of w never ...
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2answers
256 views

Unexpected results when multiplying in VHDL

I'm trying to make a simple BCD --> binary conversion operation work in an ALU I'm coding. All the other operations work perfectly fine, just this last operation doesn't work for some reason. I've ...
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1answer
53 views

FPGA - Routing Diagram - what are the physical parts

In Xilinx ISE I've generated a very simple piece of hardware and when looking at the routed design I'm unsure what some of the parts are and require some clarification on what some of these parts are. ...
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1answer
74 views

VHDL - address comparison yields wrong result

I am developing TS-CAN1 emulator on Atmel's ATF1508AS. One part of an application is an address decoder implemented as follows (only interesting parts are left): ...
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2answers
78 views

Read decimal value of a 4-bit binary input

I am quite a rookie in the VHDL world, but I seem to have hold of the basics. Atm I am working on a project, which involves me to take a 4-bit binary input (switches), read this value and convert it ...
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5answers
311 views

How to convert an array of pixels to jpg or png?

I am doing image processing project in VHDL. And as output am getting array of pixels (32 bit each). I want test this output data visually, for that it must be converted to image either png or jpg or ...
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42 views

cdma implimentation in vhdl

I'm novice in vhdl coding. I'm implementing CDMA. The transmitter part has the eight bit input data corresponding to a particular user is converted into serial form by an eight bit PISO. The PISO ...
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2answers
101 views

VHDL Plus operator `+` and Downto syntax

Considering variable a and b as STD_LOGIC_VECTOR (31 DOWNTO 0) we have ...
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2answers
72 views

PN sequence generator using linear feedback shift register in VHDL

I got a code for PN sequence generator using linear feedback shift register in VHDL. I am using 1010 as a initial seed but in the output all the four PN sequences ...
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1answer
63 views

VHDL: How to convert Bit_Vector to Std_Logic_Vector?

I want to move data from a "Bit_vector" to "Std_logic_Vector". For that, I want to convert Bit_Vector into Std_Logic_Vector. Please help me for the same.
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1answer
200 views

Conversion from VHDL to sysgen block diagram

I made my own custom board that contains a clock oscillator to drive an FPGA. I wrote some VHDL code. The script simply re-routs a 10-bit input (SIGIN) to the 10-bit output (SIGOUT) on the rising edge ...
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1answer
67 views

VHDL process causes errors

I'm new to VHDL so I just have a question to ask about why this produces an error. I have an ALU defined in VHDL: ...
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1answer
143 views

Proper clock generation for VHDL testbenches

In many test benches I see the following pattern for clock generation: ...
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1answer
93 views

How to use IO Buffer with defined location in VHDL?

I am tring to program the ADF4158 PLL Synthesizer with SPARTAN 6 FPGA using Microboard LX9. I studied VHDL for a semster 4 years earlier, and no practical use after that. So I need some experts ...
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1answer
47 views

xilinx create schematic of top modul with lower level moduls

I have a top modul VHDL source file, which has a few instances of lower-level modules (VHDL) and signals which connects these lower-level modules. How can I generate a schematic for this? I mean, I ...
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1answer
103 views

cannot fix: warning signal clk IBUF has no load please help!

I have been trying to design a simple Hardware design to controll another board that powers a set of LEDs for a stage drum lighting system. I cannot for the life of me figure out why I am recieving ...
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1answer
46 views

What is the definition of unsigned() function in VHDL?

I am unable to find the function signature of unsigned() function in vhdl. what types does it accept as an argument?
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1answer
59 views

Problem getting VHDL syntax correct

I am trying to learn VHDL prior to returning to school. I have been using the text Digital Design with CPLD Applications and VHDL ISBN-13: 978-1401840303 Other references are: ...
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1answer
73 views

Design up counter in VHDL using generate statement

I need to design an 8 bit up counter in VHDL using T flip flop and generate statement. I know how the counter works, but I am not able to design it in VHDL. The main problem is "using generate ...
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1answer
59 views

What is the difference between a static and non-static expression in vhdl?

suppose if I have two signal declarations as follows signal x:std_logic_vector(1 downto 0) := (others => '0'); signal y:std_logic_vector(1 downto 0); does ...
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1answer
90 views

VHDL code and unintended latches

I am working on coding a Regsiter a1 with input signals b1,rst and wra1 the register ...
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1answer
96 views

Shift Register Vs Multiplexer

I am not sure about an implementation. I've a multiplexer 8 input, 1 output and 3 select signal. One of these selects signal sequentialy acquires all value of a bit vector. Now I can choose 2 way. ...
2
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1answer
109 views

VHDL How to Design a Screen (Frame) Buffer

I am trying to use a screen buffer to store, change and output the bits of a video data to the DVI transmit interface. I am using Altera Cyclone III development kit. I will be using 1440x900@60Hz ...
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1answer
44 views

VHDL - Quartus II inferring latches on circuit

My circuit is based on a state-machine. I checked it and it's working fine, the only issue is that it's inferring one latch per flip-flop (The state machine has 11 states and the circuit is one-hot so ...
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2answers
53 views

VHDL - Flip Flop inferring on a signal

I have to design a circuit to count up to a number and return to zero. It must have a carry signal (which I named a_o in my circuit) as flag to show that the ...
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1answer
67 views

Using a Counter to Determine next MSB position in polynomial division

I am working on implementing a polynomial divider the operation is as follows: Check MSB of Numerator: if 1 XOR with Denom then shift Denom right if 0 Num is the same and Denom also shift right When ...
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0answers
76 views

Binary/Polynomial division on FPGA implementation

I am beginning the implementation of the polynomial binary division algorithm now as I understood i will be checking the MSB bit if 1 to XOR and shift the sum if 0 I will only shift. What I am not ...
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1answer
157 views

Signed Addition of two std logic vectors while looking for overflow and carry

I have what I think to be a working implentation for finding the sum of two signed 32 bit (std_logic_vector) vectors in which I chose to expand the result to always have 33 bits so as to preserve the ...
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2answers
62 views

What does delta stands for in ModelSIM?

I ran a simulation for a combinational logic circuit with 8 inputs, 4 outputs inside MODELSIM. When I view the simulated waveform everything looks fine, however when I export result to a list file ...
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3answers
49 views

VHDL: Simulating Delay for ISE UNISIM components

I have extracted VHDL source of my design from Xilinx ISE. It uses UNISIM library to model Look-Up Tables and Flip-Flops and other components. When I simulate my VHDL design (a combinational circuit) ...
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2answers
66 views

Races in sequential circuits VHDL

Do I need to be aware of races while writing code for sequential circuits in VHDL ( I use ISE Design Suite ) ? If I do not, what is the matter that solves the races issue instead of me ?
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2answers
98 views

quartus signaltap not accurate?

I am using Quartus SignalTap to debug my FPGA design: I always been persuaded SignalTap is not accurate !! This is what i found: I monitor the reset signal with SignalTap :Reset toggles around, ...
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1answer
128 views

The timing-driven placement phase encountered an error

Could someone explain inexperienced VHDL coder what this error message trying to tell me in simple words? I found a similar question here, but here was no answer to it: ...
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1answer
50 views

Timing/buffering issue with Digilent's EPP on Basys2?

I have a Digilent Basys2 FPGA, and I'm implementing the EPP interface described in http://www.digilentinc.com/Data/Products/ADEPT/DpimRef%20programmers%20manual.pdf. This allows a program called ...
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1answer
74 views

Using one channel from adc (pin connections) [closed]

For a heart rate calculator project by using Basys2 and VHDL, I am trying to connect ADC0808 in order to get 8bit digital output from my pulse sensor's output. However, although I designed the circuit ...
2
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1answer
74 views

Functional and Timing accuracy of an RTL Model

I am sometimes really confused by the abusive use of jargon in EDA/VLSI design articles and books. With no precise definitions, its upto the reader to make interpretation which is very ambiguous and ...
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1answer
70 views

FPGA based theremin , is possible?

I remember a while ago , i saw some Digital based Theremins circuits from glasgow university... http://www.theremin.info/-/viewpub/tid/10/pid/65 would it be possible to make a theremin by using an ...
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1answer
74 views

VHDL RS-232 Receiver

I have been trying to design an RS-232 receiver taking an FSM approach. I will admit that I do not have a very well-rounded understanding of VHDL, so I have been working on the code on the fly and ...