VHDL (VHSIC hardware description language) is a hardware description language used in electronic design automation to describe and design digital systems such as field-programmable gate arrays and integrated circuits.

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27 views

Sata iii phy chip but not with PCI/PCIe interface [on hold]

I am looking for a Sata iii PHY chip to connect to my FPGA board, but not with PCI/PCIe interface. There are many Sata PHYs in market but all have PCI/PCIe interface and my fpga does not has one. Is ...
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9 views

Synopsys design compiler- view datapath extraction results

I am using Synopsys Design Compiler(SDC) for synthesis with compile_ultra. This option does advanced datapath extraction which basically tries to group(or chain) ...
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1answer
53 views

VHDL 'buffer' vs. 'out'

I was wondering about the 'buffer' i/o option for entities in the VHDL language. I have found that my code is much cleaner if I use the 'buffer' option instead of 'out' in any circumstance where I ...
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1answer
51 views

Single Die Roll Counter Wrap Around Nested Ternary Conditional

I have to emulate a single die roll, therefore it needs to wrap back to one at 6. `D1 and `D6 correspond to my 3-bit state ...
1
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1answer
45 views

In VHDL what is a data operator type “variable” when it is translated to circuit? [duplicate]

VHDL code is finally converted into hardware equivalent when it is synthesized. What happens to data operator type "variable" when it is synthesized?
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2answers
43 views

Can we declare output as “inout” to design a flip flop in VHDL?

I want to design a JK flip flop in VHDL. In this output depends on previous state. One method to implement this condition is by declaring a state as a signal inside the architecture. Another method ...
1
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1answer
47 views

Create delay shorter than a clock period in CPLD

I have several peripherals that connect to CPLD. They all have different propagation delays, and to compensate that I wish to introduce about 10-15ns delay into the CPLD logic. In detail, clkOUT ...
0
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1answer
35 views

Is the simulated clock cycle latency through an entity accurate?

If I write an entity that takes 10 clock cycles to produce output from input, is it safe to assume that this is the case when implemented in hw, or are there other factors to consider? Does the ...
0
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1answer
29 views

Generating a desired pulse train in Xilinx ISE software

Need some help with VHDL and FPGA since I am new to it. I have a Virtex-4 FPGA and I wish to generate a binary pulse train of 16 pulses from FPGA using VHDL programming. My desired pulse train will ...
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1answer
124 views

Is 'IF' statement necessary for the clock process?

I'm used to writing the following process that will react on the rising edge of the CLK (script 1): ...
3
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1answer
224 views

having distorted image in VGA with FPGA board

I'm using spartan 3E-100 CP132 fpga board to display a basic plus image on a monitor. I have tried using 800x600 72 hz and 640x480 60 Hz but I always get a distorted vertical lines. Is it because the ...
2
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1answer
45 views

USB mouse with a PS/2 adapter for FPGA PS/2 interface

I'm designing a PS/2 mouse interface for BASYS 2 FPGA board. As you might know to communicate with a PS/2 mouse you need a protocol, so if I write my VHDL program for the PS/2 protocol and then ...
7
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3answers
495 views

Why cannot delays be synthesized in Verilog?

I have always read that delays declared in RTL code can never be synthesized. They are meant only for simulation purpose and modern synthesis tools will just ignore delays declarations in the code. ...
0
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1answer
116 views

generating 40 mhz clock from 50 MHz

In VHDL how can I get a clock frequency of 40 MHz if my onboard clock is 50 MHz. I know how to divide the frequency by integers but this case is dividing by 1.25. I am using this for VGA so I think ...
0
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1answer
50 views

generating 40 MHz clock from 50 MHz in VHDL [duplicate]

In VHDL how can I get a clock frequency of 40 MHz if my onboard clock is 50 MHz. I know how to divide the frequency by integers but this case is dividing by 1.25. I am using this for VGA so I think ...
7
votes
1answer
111 views

How do I debug red signals in ModelSIM?

I have to design a state machine using only NAND gates for the combinatorial part and D flip flops for the sequential logic. Everything should run at a clock of 1ghz/53. Now before you assault me ...
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0answers
57 views

Writing and reading from external RAM on Nexys2

I am a newbie, and learning VHDL on Nexys2, i want to program the board's RAM, i.e. MT45W8MW16BGX Micron chip. The idea of my program is to write 8 bit values through a counter on the memory locations ...
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2answers
60 views

Serialize bits from input/output pin with VHDL

The code below reads 40 bits of data sent in serial from a DHT-11 temperature/humidity sensor and stores the data in a 5 byte array of RAM. The code is: ...
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2answers
42 views

Expression and gate not gate output

The expression I came up with this circuit is A'B + A'CD + C, would the output change to AB' + AC'D' + C' since it is inverted? I'm assuming the D input compliments and cancels out? What would the ...
0
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1answer
39 views

What does “no design unit detected in this file” mean?

I got this error then I tried to add a source file. Can anyone tell me what this means? What should I do to correct it?
0
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2answers
41 views

Debugging simulation error in Xlinx for VHDL

I used Xilinx to simulated Logic And Gate, and it worked fine. I followed same procedure to simulate Half-Subtractor, but got stuck in between. When I checked Xilinx window for two codes I found ...
0
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2answers
85 views

Short ISE FPGA Workflow Tutorial

I'd be much obliged if somebody could point me to a short ISE workflow tutorial that shows how to implement a simple circuit using VHDL. As indicated, the tutorial should be short as I'm not ...
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1answer
61 views

Fixing 1 failing timing constraint in Xilinx

In the end of my project I have a timing constraint failure as follows : clk_in is the 100 Mhz system clock on ML507 I don't know why it is not meeting the ...
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0answers
47 views

Xilinx Design Summary

My project is finished and Xilinx gives lots of statistics in the summary like : How shall I evaluate these values, what can I say about them? What means what? Is this report good or bad? With ...
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2answers
97 views

Generate State Diagram from VHDL Code?

Is there a tool which generates State Diagrams from VHDL code? Also is there an easy way to indent VHDL code like in Visual Studio if I press ctrl + i it indents.
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3answers
121 views

How does VHDL handle bitwise operations?

I'm having a problem in some VHDL code I'm writing. I want to drive a signal with two other signals AND'd together like this: mysignal <= "010" and '1'; The ...
0
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1answer
45 views

Removing warning FF/Latch trimming

I have a 16 bit signal, for me only the last 4 bits are important and the first 12 bits are always "0", so I'm doing nothing with the first 12 bits and in the end it goes out of my component to next ...
2
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0answers
47 views

Troubleshooting audio output on Nexys 2 (FPGA)

I've recently purchased the PMOD AMP1 module from digilent for use with my Nexys 2. When I program the demo project and plug headphones or speakers on the headphone output I can hear a barely ...
0
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1answer
68 views

Key press/Key release

I'm designing a keypad in VHDL and for protection purposes I disable pressing a second or more keys while one key is being pressed. Example while I'm pressing "7" a press of "2","3","5","4","1","0" ...
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2answers
109 views
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0answers
73 views

VHDL - RC4 implementation

I want to write an RC4 implementation in VHDL. I have a problem with this part of code. Firstly I know my if is wrong. It should be like ...
7
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3answers
184 views

Pressing same key rows at the same time

I am designing a keypad in VHDL. Everything works fine when only a single key is pressed. I'm scanning each column for a key press in a state machine and when no key is pressed, which is the condition ...
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0answers
47 views

Görtzel in VHDL?

I would like to detect dtmf signals with görtzel in VHDL. I couldn't find any examples written with VHDL, would you give me some tips? Where shall I start looking for, is there already an existing one ...
2
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2answers
91 views

When is the concurrent signal assignment executed?

Having the next code: ...
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2answers
62 views

Is it possible to move VHDL code from the top level of a design to a subcomponent, without changing the underlying logic?

Suppose I have a component, called Top_Level, that has a bunch of registers that it uses. There are some subcomponents that perform some combinational logic using the registers. There is also a ...
1
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3answers
74 views

Return from idle state

I have 5 states : idle, state1, state2, state3, state4. I sometimes need to go to idle according to my design, and when I return from idle, I don't want to start from beginning, I want to start from ...
2
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1answer
77 views

Computational complexity of current netlist matching algorithms

I understand that the problem of matching two netlists could be reduced to the graph isomorphism problem which is NP-intermediate. Apart from that what are the complexity results of some of the ...
1
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3answers
135 views

Set a constant high signal to low

I have a keypad circuit, when I press and hold a key, the signal "key_pressed" is always high, as long as I keep the key pressed, which is normal, when I leave it, it gets low again. But I don't want ...
0
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1answer
108 views

State switches in FSM

I have a simple board with 6 buttons, consisting of 3 columns and 2 rows I would like to detect the pressed button. My code below works with this fsm: ...
2
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1answer
68 views

VHDL latch for Xilinx Spartan 3E

I am coding a display control for the Spartan 3E. It has 8 LEDs. When the ALU's state signal (from other block) is "00" the MSBs and LSBs are time-multiplexed for one second each byte. When state is ...
2
votes
1answer
85 views

Using generic packages with protected type in Modelsim 10.xy

I am trying to use generic packages with a protected type in Modelsim 10.0a. The technote vhdl2008.note states: a basic generic package and its instantiation with some noteworthy ...
1
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1answer
52 views

A simple VHDL circuit won't display initial value

Here is my code and it's pretty simple. I'm to cycle through the first 8 letters of the alphabet on a Altera Cyclone II board. ...
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0answers
53 views

Learning FPGA Design (Books, Resources, VHDL/Verilog) [closed]

I used to use FPGA's back in college and I really enjoyed it. Years have passed though and I haven't had much time to play with it since then. I have realized I have forgotten some stuff (quite a bit ...
2
votes
2answers
64 views

VHDL: Looping through a module asynchronously

I have a VHDL module that applies a shuffle algorithm to a 64 bit input and outputs the 64bit result. I need to loop this output back through the module exactly 4 times, i was wondering if there was ...
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2answers
61 views

Usage of Next state and Clock Divider?

I have a clock divider and state machine like this: ...
1
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0answers
35 views

Create State machine and implement on CPLD [duplicate]

I have this conditions for traffic controller. I excuted this on table. Now I want to implement this to state machine. Then after I will use this state machine to create VHDL and implement it in CPLD. ...
0
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1answer
60 views

Signal Generation with duration in VHDL?

Im writing a signal generator in VHDL and I would like to set the duration of the signal generated to 75ms, it is an out signal and my clock is 100 MHz, I would be glad if you can help!
0
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1answer
93 views

Enable clock for a state machine?

I have 100Mhz system clock and I would like to have a 200Hz Enable signal for enabling the state machine. I need a clock divider for this process and thought about this : ...
0
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1answer
63 views

Warning while synthesing VHDL code

I'm Getting warnings while synthesing the below code. Tried many ways but in vain. Can anyone please suggest what might have gone wrong with my code. The code is to latch the data as and when the ...
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votes
3answers
138 views

How to increase the number of inputs on Spartan 3E XCS5003, FG320 FPGA Kit [closed]

How can I interface extra switches or buttons for inputs to a Spartan 3E FPGA board? I am using a Spartan 3E XCS500E device in a FG320 package (speed -4). Original title and question: HOW TO ...