VHDL (VHSIC hardware description language) is a hardware description language used in electronic design automation to describe and design digital systems such as field-programmable gate arrays and integrated circuits.

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Syntax error in VHDL code

I'm trying to implement controller module as a FSM using VHDL, below is the code ...
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How can I specify “don't care” signals in VHDL?

Frequently there are cases where the value that a signal is assigned doesn't really matter. Is there a way in VHDL to specify this in order to allow the synthesis tool to optimize these specific ...
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Can you interface a Modelsim testbench with an external stimuli

I am working on a team that is doing both driver software and FPGA development. The FPGA simulation is being done in Modelsim and driver software is written in C. To minimize integration risk, I ...
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147 views

How are state machines used in electronics?

It seems to me the use of state machines is just in logic circuits, is that correct? If not do they have other uses, such as say in microcontroller programming? I'm quite new to the subject and wonder ...
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How to implement different encodings for subsets some enumeration in VHDL?

When trying to decode/encode a large number of distinct 'things' in VHDL, I stumbled across the following technique, which I find quite intriguing: ...
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61 views

Implimentation of BZFAD using VHDL

I'm novice to vhdl coding. I'm implementing BZFAD which is a low power multiplier. In the Block diagram as shown below I have a transistor block(M1) whose input are driven from the ring counter. I'm ...
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105 views

Pattern Recogniser on FPGA

I am trying to code a simon Game on my FPGA, and I am a bit stuck at how i should create a pattern and detect it. simon Game : http://www.freesimon.org/ My idea until now is, I create 99 states (99 ...
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51 views

32 x 8 Register file using generate statement for D-flip flops

My circuit has a grid of 32 x 8 D flip flops. each row should be producing a 32 bit vectors that contain the Q values from the D-ff's - which are then sent to a 8x1 MUX. The following code is me ...
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54 views

Finite state machine FSM model of FIR filter in VHDL for FPGA

I want to make a FSM model of FIR, for that I need to write FIR calculation code line in FSM implementation. Here is the actual and correct code for FIR ...
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41 views

Getting rid of latches in VHDL

I am building a simple debouncer with decrementing counter. The syntitizer is yelling that there are latches. I don't need latches. I just need flipflops. WHich part in the following code is creating ...
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60 views

Bidirectional bus in vhdl

I need to understand the concept of bidirectional bus. What i want to do is connect a memory with ports din and dout to a inout port named data. So along with memory i use a tristate buffer as ...
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How do I transmit an FM signal from the VGA_R port on the DE2-115?

The best reference for my question would be this youtube video: https://www.youtube.com/watch?v=4VW017qPT6Y I'm trying to do exactly what they did with the following resources: Matlab 2013a with ...
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generate a VHDL process with clock signal at a frequency of 10mhz

Im struggling to see how my lecturer got 100nanosecs a clock period(50nanosecs up, 50nanosecs down) the clocks at 10mhz so I did: 1/ 10x10^6 => 1x10^-7 microSeconds convert to nano seconds ...
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66 views

Xilinx and VHDL · Why is this INOUT port undefined?

I'm using Xilinx ISE 13.1 x64 WebPack for a college assignment and I'm implementing a BCT for the sake of it. It's a Binary Coded Ternary. Like a BCD, but with only three digits (0, 1 and 2), to ...
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57 views

How to Implement this special selector?

Is it possible to write a module with 3 wires a,b,c that would output either : z (disconnected) if a=b=c=z a if a=(0 or 1) and b=c=z b if b=(0 or 1) and a=c=z c if c=(0 or 1) and a=b=z x (dont care) ...
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113 views

Why is my simple counter VHDL not working? Where did my signals go?

I'm a complete beginner with VHDL and an almost beginner with digital logic and I'm having a problem working through a book I'm reading. In particular, an exercise asks to build a counter with an ...
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66 views

VHDL Fpga debouncing

I had some troubles with debouncing on one button, so i searched on Google to find a solution for my debouncing problem. I found this code: ...
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Variable delay element [closed]

This code if compiled has an error appear with (k) symbol. I need to implement this simple block. k (that represents the amount of delay) will come to my block from the previous block. ...
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72 views

Differences in VHDL syntax

I'm reading a VHDL design and I came across the syntax in the architecture that looks like: ...
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Integrating third-party IP core using Xilinx command line tools

I am trying to integrate a third-party IP core, which is given in form of an .ngc netlist file and a corresponding .vhd file with only the entity declaration, into my design. The IP core was ...
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How to scale output of FIR filter implemented in VHDL

For a DSP school project we need to implement sound effects in a SPARTAN 6 FPGA using VHDL. We tried to keep it simple and start off with a simple (100Tab) FIR filter. As coefficients we used those ...
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Do design of a VHDL module as APB Master has any practical difficulty?

I went across VHDL codes for memory architectures, which contains modules designed as AHB masters, AHB slaves, Bridge, and APB slaves. But no APB slaves. Is there is any specific reason for excluding ...
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How data movement from large register to small register works in VHDL?

I went through a VHDL sample code for memory management. In that data from a 32 bit register was directly moved into a 8 bit register. My doubt it is how this data movement can happen? Is there is any ...
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Creating large counters / timers

I often need to create a large counter in my projects, mostly to do some timing stuff, which could be to blink an LED every second ect. I have done this by creating a large counter, as shown in the ...
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80 views

Johnson Counter VHDL

I have a problem given to me that states: Design a 4-bit Johnson counter and decoding for all eight states using just four flip-flops and eight gates. Your counter needs not be ...
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Ring counter vhdl

UPDATE: CODE IS FIXED AND CORRECT (AT LEAST I THINK) I am trying to design an 8-bit self correcting ring counter whose states are 11111110, 11111101,.......,01111111. This includes reset and enable ...
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CPU Cache implementation in VHDL

I have been assigned a project of designing a cache memory with some advanced features (using efficient cache algorithms) and implementing it in VHDL. I know the required theory for carrying out this ...
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Analog Design to VLSI Layout Tool/Software

I want to implement an 555 timer. I am looking for tools preferably FREE ones. I looked at certain tools which have GUI where I can select and drop transistors which I find tedious. Is there any ...
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VHDL up/down counter explanation?

I've basically got a test soon and I was looking at a past paper and can't make sense of one of the questions. It's asking to make a up/down bit slice counter with async clear using VHDL. Why is ...
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VHDL: How to double read a register bank?

We have been tasked with creating a register bank that can dual read, but only single write. At the moment I've got it all working apart from the dual read. Could someone point me in the right ...
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How to shift left/right a STD_LOGIC_VECTOR value within a WHEN statement?

I'm attempting to create a parametrizable ALU which handles N-Bit signed data. However the methods I know of shifting left/right, either won't work because the values are defined as STD_LOGIC_VECTOR: ...
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136 views

Writing and Reading From FLASH ROM on Nexys 2 Spartan 3-E FPGA

I am a newbie to VHDL and FPGA platform. I have a Nexys-2 Spartan 3E FPGA board which is provided with a 16 MB Flash ROM.I want to preload first 10-20 memory locations of this ROM,each location with ...
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VHDL Assignment Statement

In my ASIC book they are developing a state machine, and they have a statement like: Shift <= '1' when State = S else '0'; However in my project I have ...
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Using the PS/2 port of the Papilio One FPGA from VHDL

I'm trying to receive data from a keyboard via the PS/2 port on the Papilio One Arcade Megawing. Eventually I'll want to implement this from scratch, but I thought I'd get some public code working ...
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First attempt at DFF VHDL

I'm fairly new to VHDL and was wondering if anyone could have a look at the code I constructed for a DFF. I haven't added the reset or preset on as of yet. Just the basic function. Also don't have the ...
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fpga internal metastability

I have an issue which I think maybe related to internal timing issues. I know that crossing clock domains can cause metastability, because setup and hold timing not being kept. But I was thinking ...
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Output timing is odd in VHDL

Alright I've been creating some cool stuff in VHDL but I've run into a quirky problem. I'm creating an ALU, and attempting to write a test-bench for it, but for some reason the timing is off and my ...
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Set STD_LOGIC_VECTOR with constant integer

Is it possible to set a STD_LOGIC_VECTOR(6 DOWNTO 0) with a constant like so: ...
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How to write VHDL program to send command to PS2 device [closed]

I'm using Quartus II 13.0sp1, DE1 Board for testing, and Cyclone II FPGA EP2C20F484C7N. I need to write program in VHDL that sends command to device. I have already created entity and architecture ...
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VHDL logical operation on integer

I have some VHDL code that has the following signal definition: signal hcount : integer range 0 to 235; This is used as a counter throughout my system (so I ...
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How to implement memory mapped IO

I am describing a system in VHDL. This system already contains a processor, a DDR SDRAM controller and a VGA controller. VGA reads pixels from SDRAM (already validated and proven in FPGA). Although ...
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How can I simulate contamination delay in VHDL?

Propagation delay is simple to implement: Out <= '1' after 3ns; I tried to add contamination delay as such: ...
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cross clock domain databus

I asked a question some time ago about crossing clock domains Design practice crossing clock domains and async signals. One of the "rules" is to never synchronize multi-bit signal bit-by-bit, ...
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526 views

Clock divider VHDL

I created a clock divider with the code below. i followed steps in prof chu's book. ...
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55 views

Novice question: what are attributes in VHDL?

What is the difference between constants and attributes in VHDL? I know that both can be declared and later assigned value ...
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How is debugging build implemented in VHDL?

I come from C background and am being introduced to VHDL. I read about the syntax and the concurrency/consecutiveness of actions. Now I am getting to wonder how are development-only features ...
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Tsmc synthesislibraries

Be gentleman I am new in VHDL I have a VHDL code for an ALU, I want to synthesis this code and try for this work under 140nm(or under 0.18u). I can't find any library for this work, can you help me ...
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157 views

VHDL--counter for 7 segment display

I am writing a code that when the key(0) is pressed, the letter shown on the 7-segment display changes from the one to the next, like a to b, b to c. It starts from A. When the letter reaches H, it ...
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Design practice crossing clock domains and async signals

I have been designing a few projects on different FPGA's in VHDL, and it seems my most common source of "hard to find errors" is when I forget to synchronize an async signal, or forgets to resync a ...
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difference between using reset logic vs initial values on signals

Let's say I have a signal, I can either assign a initial value of zero OR I can set it to zero upon RESET. I've seen my co-workers using the two method interchangeably. I just want to see others ...