VHDL (VHSIC hardware description language) is a hardware description language used in electronic design automation to describe and design digital systems such as field-programmable gate arrays and integrated circuits.

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17 views

Altera Quartus - structural architecture

I am relatively new to VHDL and I am supposed to use structural architecture and Altera Quartus on my assignments. But, I have noticed that the Unisim library is not compatible with Altera Quartus, so ...
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1answer
34 views

Increment counter by pressing a button with output to leds

I have this simple code which doesn't behave as it should and can't figure out why. ...
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1answer
50 views

Is it possible to see how much logic an IP core uses?

Is it possible to see how much logic an IP core uses in Vivado? I just found out that one of my variable might create a giant mux. I want to know how much logic this mux uses, so I could document it ...
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18 views

Assign bits of std_logic to output leds

I want to read the bits of an std_logic variable and assign each bit to an output, such as an led. How can I achieve this? Perhaps ...
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1answer
29 views

Problem with WHEN - ELSE

I am new in VHDL. The code below doesn't work for some reason. The D0 and D1 are switches and when I added the D1 it stopped working. clk_Centi is pointing to an LED. ...
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1answer
48 views

does this ensure i am reading from the ram?

I at the moment trying to reverse engineer something i made a long time ago but never understood why it is running so slowly. I have a Zybo board, with an Zynq 7010s chip ons which has dual ...
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1answer
45 views

Write to reserved registers in I2C

I'm trying to get a MPU-9150 motion sensor running with my FPGA-Board. The problem is that my I2C-master library doesn't support writing single bits. According to the Register Map there a for example ...
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24 views

Could you recommend a beginner VHDL book for simulation? [on hold]

I am very new to VHDL and honestly my ride so far with VHDL has been so bumpy. after trying multiple book I reached a conclusion that it is better for me now to start learning VHDL as a simulation ...
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2answers
33 views

Unconnected port warning on reset port in asynchronous register in Vivado

I've been trying to synthesis this register model. Its simulation in ModelSim is correctly fine. However, when synthesis, it always yields warnings: [synth 8-3331] design register1 has unconnected ...
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1answer
39 views

CASE plus WAIT statements

I'm developing a simulation model of a component that I need in my design. To make it fast and simple I decided to only create it in a behavioral manner (eg not synthesizable). To do so I'm using a ...
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46 views

Vhdl to C learning t, d, jk, and sr flip flops [closed]

lengththy question but been a VHDL student and looking to C wanted to know how to describe or explicite the above. I maybe able to find them individually but wanted too know how they are all in one. ...
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1answer
46 views

Asynchronous JK Flip-Flop in VHDL

and thanks for your help. I wrote the code for an Asynchronous JK Flip Flop in VHDL, the code is the following: ...
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1answer
40 views

found '0' definitions of operator “*”

I'm tryinig to implementan IIR filter like: y(n) = 2*y(n-1)-y(n-2)+x(n)-2*x(n-6)+x(n-12); My vhdl code is: ...
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2answers
27 views

VHDL - displaying 4 digits on 7-segment display

I wrote a vhdl code, that would display 4 digits on cpld 7-segment displays. I used a state machine to select the display, and with ... select instruction to select a set of bits given to the current ...
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0answers
36 views

What does a conversion imply in VHDL

For few days I've been wondering why an std_logic_vector type can't get an unsigned/signed type. My question is : does this constraint only comes from VHDL syntax and though this is implicitly needed ...
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94 views

Structural Model for 1-Bit ALU, VDHL code

Recently I've been trying to study VDHL code. I saw the following picture on a website: I was wondering how to create a structural model for this ALU using VHDL statements. ...
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1answer
33 views

Issues with combining counters for traffic light

I am trying to implement something as simple as the controller for one single traffic light by using two counters (one for green/red and one for yellow), but I don't seem to be getting the timing ...
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3answers
97 views

Are there any standard FPGA internal buses?

Are there any standard FPGA internal buses? I've always used some sort of bidirectional bus between my internal blocks, but is there a standard way of doing this?
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1answer
47 views

VHDL blink leds for changing bits in vector signal

Suppose there's two SDT_LOGIC_VECTOR signals A_READ and A_OUT, both 8 bits wide. A_READ is updated by some process at random intervals. A_OUT is connected to 8 LED's. I want to blink a LED for each ...
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40 views

VHDL optimization: shift register with reconfigurable outputs

I am looking for some advice to optimize my beginner's design. Logic needs to be implemented on a CPLD that is able to : receive data from 4 parallel in/serial out shift registers through 4 serial ...
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1answer
39 views

ModelSim simulation won't advance

I am trying to simulate a testbench on ModelSim, but when I run the simulation, it never advances in time. The delta does not increase, either. Are there any useful tips for debugging in a situation ...
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1answer
47 views

Why the output signal from the counter seems to be not driven?

I've written a memory module for an application. In order to address each memory location a simple 6-bit counter is used. I have tested most of the components (including the counter) and they seem to ...
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19 views

Flashing NIOS II with SPI at boot

I have a Altera FPGA, which is configured (programmed/flashed) at startup by SPI from a processor runing embedded linux. If I put a NIOS processor in the fpga, is it possible to flash the NIOS ...
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2answers
78 views

What the FPGA dev board to choose: Xilinx or Altera? [closed]

I'm very new to programmable logic world and have never worked with any HDL languages, but I certainly want to get started with FPGA. At the moment the goal is to develop/simulate simple 8bit CPU and ...
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1answer
72 views

VHDL - 10% Duty Cycle

I need to generate 500Hz from 50MHz clock frequency. I already got it. My problem here is how should the code to be adjusted if I want to change the duty cycle to 10%? Thank you. ...
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49 views

Array of strings in VHDL

I would like to declare a type which is array of strings in VHDL like and made signals using the new type as: ...
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26 views

How to use an array type as parameter of a Procedure

I want to read input values from a file and store them in an array I have defined a custom array type in a package as : ...
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27 views

Write/read 2d data from DDram from the arm on the FPGA?

I having some problems with testing the example code, which the Vivado sdk has available for testing my FPGA implementation. The implementation can be viewed here : ...
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61 views

Memory Interface with a Multiplexed Address/Data Bus

I want to implement a memory interface in VHDL between an FPGA and a processor. The address/data bus is a 16-bit multiplexed bus with an ALE, write protect and BusWait. According to the NVIDIA Tegra 3 ...
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1answer
42 views

Moving a large dataset from the PS to PL on a zynq device?

I am at the moment trying to interface with DRAM on my Xilinx Zynq device such that I am capable of moving a large amount of data from the processing system (PS) side to the programmable logic (PL). ...
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3answers
239 views

Why would you want to write to a file when writing VHDL? [closed]

I have never so far been in the need to write to a file when making a testbench in vhdl. Seeing the signals being plotted has always been enough so far. Could someone please give me a case or the ...
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0answers
42 views

use of ISD4002 SPI with FPGA

I am trying to build a circuit that would be some kind of INTERCOM and will be controlled by FPGA (cyclon 2 by altera ) . Because I need to have multi voice channels I choose ISD4002 because in my ...
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1answer
41 views

Adder tree with 4:2 compressors. What to do with Cout?

I'm trying to build an adder tree using 4:2 compressors. I want to add together 16 bytes at total, so I figured that a possible architecture for that tree is the following: Each 4-Byte adder has 3 ...
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1answer
58 views

Pipelined Radix-2 DIF FFT SDF Architecture

I want to implement Radix-2 Single-path Delay Feedback (SDF) Decimation-In-Frequency FFT with Pipelining in VHDL. I am trying to understand the below architecture as described in this MIT ...
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1answer
60 views

What is VHDL used for?

I'm learning digital electronics and I met with VHDL. I know it's hardware description language, but once I learn syntax and how to write code, what can I do with that code? Essentialy, what is VHDL?
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2answers
76 views

simple counter in VHDL

I am trying to write a little counter in VHDL using the two process methodology. However it is not working. Could someone explain me why? ...
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0answers
48 views

vhdl code to do ramp-up & ramp-down for audio

I'm trying to learn more about VHDL and audio. I generated sine wave data using matlab. I want to generate three different type of audio output so I thought of doing ramp up and ramp down for my ...
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1answer
50 views

Why this concept in VHDL doesn't work?

I want to make a simple processing element for calculating the absolute difference between two 8-bit words. However, this element may be used as part of an array in order to speed up the AD ...
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1answer
47 views

Wrong RTL schematichs of adder tree

I write a VHDL code for an adder tree, with a parametrized number of vector. It's only for Learning purpouse, so I dind't implemented the carry between the block, I simple created a larger bus so I ...
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1answer
68 views

VHDL: A function to determine array length

SOLVED!!! I'll leeave the questions, see below for the solution. In a VHDL project, I want to initialized an array that have a certain dimension, and I want this dimension is derived by a function. ...
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1answer
36 views

Problem VHDL process maintaing a signal modified

I am writing a VHDL code of a simple counter which receives as an input a number and that is a time in ms, and a 50 MHz clock, for example if 200 is received it has to count 200 ms so 200* 50e3 ...
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44 views

VHDL - loop counter bug with SPI protocol

I want to write a simple reader from SPI data, to read 1 byte and transfer it to another block. I used the following code : ...
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2answers
69 views

VHDL loop not updating output

Why won't the value of output changes? It has been clocked and the inner loop should update? In the simulation, the output's value is always 9. Please help what I may be missing. I would like the code ...
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1answer
61 views

VHDL iterate over a “list” of external names

I'm using external names introduced in VHDL-2008 to access a bunch of signals (let's say 1000) in a design hierarchy with many levels. ...
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53 views

Procedures or structural architecture - which is preferable for synthesis in VHDL?

I'm writing VHDL code which I would like to implement on an FPGA. Currently I have written separate architectures for adders, multipliers etc and combined them all using a structural architecture in ...
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1answer
43 views

Synthesisable alternative to the wait statement in VHDL

I'm writing VHDL code for a filter which I want to implement on a Spartan 6 FPGA. When I tried running a testbench for my code, one of the processes entered an infinite loop, so I added a wait ...
3
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1answer
52 views

Xilinx ISE warns that a signal is trimmed since it has a constant value of 0, but the signal is used within my code

I have created the following VHDL module, which is used as an up/down counter. ...
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1answer
59 views

Clock port and any other port of a register should not be driven by the same signal source

I get this Warning from Altera Design Assistant for the below: Clock port and any other port of a register should not be driven by the same signal source Critical Warning (308012): Node ...
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2answers
134 views

VHDL port map: connect only some bits of a vector

My design has a entity for configuration which returns std_logic_vectors (length defined by generic - normally 32 bit) ...