VHDL (VHSIC hardware description language) is a hardware description language used in electronic design automation to describe and design digital systems such as field-programmable gate arrays and integrated circuits.

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VHDL TESTBENCH ERROR

I have to write a testbench code for a block having two inputs which were "X" and "Y" with output "A". The behaviour of the block is addition of two input signals, added value to be stored in "A". Two ...
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60 views

Does a package exist to carry out intense string manipulation in VHDL?

I am writing a VHDL code for a MIPS32. My idea is that for simulation purpose the testbench shall replace the instruction memory with a behavioral model which will read the program instructions from ...
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17 views

Unable to open XPS from PlanAhead(Xilinx ISE 14.3)

I am unable to open Xilinx Platform Studio(XPS) from PlanAhead. It shows me following error messages: I have not opened multiple sessions of it. I have also removed the write protection for that ...
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49 views

VHDL: value isn't assigned immediately

I asked a similar question here. I thought that that answer would be applicable to this code but I have the same problem. I have a ROM that runs at twice the speed of my CPU (left out all the ...
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1answer
39 views

VHDL delayed assignment problem

I want output to equal "11111111" on the first rising edge of the clock but it only happens on the second rising edge when I test the code with ModelSim. The code might look weird as a simplification ...
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30 views

VHDL “casting” a constant into a signal?

Is there a way to cast a constant value into a signal in order to send it into a function's parameter ? Let's say I have this function: ...
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29 views

VHDL multiple constant drivers

I'm trying to initialize all elements in an array to zero, but I also need to save values to this array after operations like an addition. ...
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91 views

Fpga Crossing signals between related clock domains

I have an fpga design with two clocks, one is 54MHz and the other is a divide-by-4 clock of the 54MHz, this is 13.5MHz clock. The 13.5MHz clock is generated by dividing the 54MHz clock in vhdl, and ...
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72 views

Is it possible to detect high impedance at FPGA input?

I am using a FPGA development board which have neither pull-up nor pull-down resister at the input side. VHDL code that I am developing has to detect either logic zero or logic one and to do ...
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2answers
65 views

How to trigger at both edges in VHDL?

In Verilog if we use always@(clock) we can trigger a module at both rising edge and falling edge. Is there any method to do the same in VHDL.
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FPGA- ETHERNET-VHDL [closed]

I have a PCI card.The card contains SRAM and Ethernet Interface. I need to send my data from SRAM to client PC through Ethernet. I have to write vhdl code for SRAM and ethernet interface. but i ...
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49 views

Process statement in vhdl

I have a very basic question here. When I learnt Processes it was said the statements occur sequentially.This is what I believed in. In the NCO process image file,there is proof for it. fword is ...
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25 views

Type bit does not match with the integer literal while converting integer into bit_vector

In VHDL, is there any way to convert an integer into bit_vector of length of 14? Currently, I am first converting the ...
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28 views

VHDL signal assignement

Is there any difference between : Type word is STD_logic_vector(15 downto 0) And Signal word:STD_logic_vector(15 downto 0) ...
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1answer
32 views

What is the difference in assigning output before end process and after end process in VHDL

I have written a code to check the difference in assigning output before "end process" and after "end process" in VHDL. And the results of the simulation I have posted with it. What I found is ...
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2answers
43 views

Component Not Found VHDL XILINX ISE

i know this might be a very simple question . i have to simulate some delays for various adders in ISE Suite . ( i'm a little familiar with vhdl concepts but ISE Environment , not at all ! ) this ...
2
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1answer
71 views

Why rising_edge is only used to detect clock input?

In VHDL rising_edge is used to detect signal transition from logic zero to logic one. In almost every vhdl sample codes that I referred rising_edge is only used to detect logic zero to logic one ...
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2answers
35 views

VHDL using flow control vs minimization

I am currently designing a mips microcontroller for a class. I am now working on the control unit for the microprocessor and I am wondering if I should use minimization vs using flow control (if, ...
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52 views

VHDL code works well in ModelSim and strange behavior in Altera FPGA

I'm trying to understand a strange (for me) behavior of a simple VHDL code. I have realized a stupid code that works well in ModelSim and doesn't work in a real FPGA (Altera MAX 10). ...
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37 views

VHDL: couldn't implement registers for assignments on this clock edge

I'm getting the following errors: Error (10822): HDL error at pwm.vhd(15): couldn't implement registers for assignments on this clock edge Error (10822): HDL error at pwm.vhd(18): couldn't implement ...
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33 views

obtain the value stored in array

i am working with spartan 3 xc3s5000 and 14 bit adc(lt2255). I am giving a analog signal to adc which is connected to spartan . I want to store the values of samples(sample done by adc of given analog ...
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2answers
48 views

VHDL how to make a process with sensitivity list wait?

I'd like a process to listen to changes in a signal, but not before 20 ns. How can I achieve that? It doesn't seem possible to use wait statements in such a process, which makes sense since is has a ...
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output is wrong when running the ALU test bench but individual component gives the correct result

Rotate_left is called through the ALU main code. ALU is fine as other operations like MUL,DIV,ADD and SUB are working fine. Please someone check and help me figure out the issue. we are getting the ...
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27 views

PlanAhead 14.7 multiple runs issues

My project in PAhead 14.7 have 6 different synthesis run and 6 implementation runs. Each implementation run have her own parent synthesis run. The differences between synthesis runs are some generic ...
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27 views

VHDL Counter does not update when desired

For a project I am working on, I require a counter whose value increases as soon as the increment control goes high (i.e. on the rising edge). However, I have had trouble implementing this in VHDL. ...
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timing constraint on enable signal

I'm using the Igloo Nano FPGA, and have a question, which generally relates to FPGA design. For test purpose I've written the "dummy" code below. In my VHDL test bench, I have set the "en" signal to ...
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47 views

VHDL - Does signal ever get assigned in the same clk cycle?

This is my simulation I'm assigning different values to btnin my testbench ...
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247 views

What is the use of 'event in vhdl?

In vhdl code for synchronous counter, I replaced following part ...
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Problem while linking flip flop D in VHDL

I have defined a single Dflipflop with the following code (and I suppose It works): ...
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1answer
66 views

Multicycle : Is it possible?

I've to constraints an Lattice Semiconductor FPGA and I've some doubts about the multicycle constraint described here. I've the following RTL : Basically it is a counter that is driven by a rising ...
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2answers
51 views

Single input for consecutive state transitions in an FSM: preventing fall-through

Consider the following state diagram where the inputs are c and v. The system is also receiving a high frequency clock ...
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1answer
36 views

Lattice Diamond 3.4. template/schematic generation

I'm following this tutorial: Lattice Diamond Hierarchical Design Test Bench Tutorial However i am using Lattice Diamond ver. 3.4.1, and some details are different. The Problem i am facing is with the ...
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42 views

How to make library and compile with vhdl code in verdi and in ncvhdl?

I don't know where to start from. I want to compile VHDL codes by ncvhdl. But I have met some error messages like this when I have compiled like this. ...
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1answer
73 views

Improving a processor design in VHDL

For a project at my university we have to improve the design of a processor (more specifically, the Plasma CPU. The design is generated based on a description written in VHDL. We have to identify ...
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70 views

How to simulate an 8x4 memory using VHDL?

Why does this code: ...
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57 views

Implementing a FSM using JK flip flops in VHDL

This is yet another semester project I'm stuck on. I need to implement a state machine starting from the following diagram: What I've managed to do so far is write this state table, although I'm ...
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1answer
80 views

VHDL SPI xilinx spartan 3E

I have nearly non previous experience with VHDL and the most of the code here is given to me by the teacher. I'm trying to communicate with a ADXL362 accelerometer using SPI on a Xilinx Sparten 3E. ...
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69 views

std logic conversion into float in vhdl

I am new in this field. I have a problem with conversion of std logic input into real values. I have been using to_float function but it always showed error. When I ...
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2answers
120 views

How is VHDL used?

I'm new to hobby electronics/robotics and am trying to understand the use case for VHDL. The syntax is easy enough to understand, but I'm not seeing the "forest through the trees" on a few items. For ...
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50 views

VHDL - Can't see why these two architectures produce a different RTL

I have the following examples: ...
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64 views

How to solve routing issues in Artix7?

I am working with Artix 7 (xc7a15tftg256). When the time of Run Implementation,shows the following error message: [Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub ...
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1answer
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4
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246 views

Do open source libraries exist for VHDL the way they do for C++ or python?

When I'm approaching a problem in C++ or python, there are many libraries that exist which do the heavy lifting of my code. I'm thinking about GNU GSL, BOOST, or FFTW for C++, and NumPy or SciPy for ...
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61 views

How the change the frequency of a clock in Quartus II?

I have a clock in VHDL: ... process(clock) begin if rising_edge(clock) then ... When I check the timequest analyzer, it sets this clock to a default 1 GHz ...
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2answers
84 views

VHDL Block RAM Inference

I am storing a 16k constant sine table of 14 bit signed vectors in a package. I use this package in my module to read out the array in a clocked process But I get this warning during synthesis and ...
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1answer
53 views

Store consecutive UART inputs to register

I have implemented a UART receiver/transmitter (8-bits) in VHDL for use on a Digilent Nexys 3 FPGA. So far I have managed to read inputs in a FIFO, process each byte individually and write the output ...
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2answers
91 views

VHDL JK Flip-Flop with logic gates

I am trying to make a JK flip-flop in ActiveHDL environment. I want to make it with logic gates. It should look like this: This is my code: ...
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VHDL JK Flip-Flop with logic gates [duplicate]

I am trying to make a JK flip-flop in ActiveHDL environment. I want to make it with logic gates. It should look like this: This is my code: ...
2
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1answer
49 views

Using the ROM megafunction in VHDL code

I have created a ROM megafunction using the MegaWizard plug-in Manager. This created a new file which I named rom.vhd. My code: ...