VHDL (VHSIC hardware description language) is a hardware description language used in electronic design automation to describe and design digital systems such as field-programmable gate arrays and integrated circuits.

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VHDL how to make a redundant case statement simpler?

I'm using case statements to check the bits of a word. Is there any way to write this more compact since it uses a lot of space (I have other signals on which I want to do this aswell). ...
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VHDL coding of a FSM not compiling?

What is wrong with my coding? I have used the following code for a state machine that consist of 3 states: s0,s1,s2. At reset it comes to ...
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29 views

VHDL Use of variables vs signals inside a process

I'm implementing the double dabble method (https://en.wikipedia.org/wiki/Double_dabble). Every cycle if a BCD(binary coded decimal) digit is > 4 then add 3 to it. Regardless of the addition there is a ...
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Difference between Blocking and Non-Blocking assignment in VHDL

I started reading about Blocking and Non-bocking assignment with reference to verilog. But when I switched to VHDL its confusing. What I felt is, in VHDL other than to visually differentiate ...
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32 views

Help with resolving warning “inferring latch(es) for signal or variable ”..“, which holds its previous value in one or more paths through the process”

Below is the code for my branch unit implementation. This unit calculates the jump destination address and writes it into the PC register. There are a few different types of jumps, etc, standard ...
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37 views

Loading hex and binary data at the same time from text file into std_logic_vector

I'm trying to create a simple cache to use in simulation with my processor design. I want to populate the cache with instructions that are stored in a file, .bin or .txt. The file has no more than ...
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68 views

ADC conversion using a Datasheet

Is it possible to find a corresponding digital value for an analog current value(Amps) using the ADC component datasheet? If yes, what are the parameters I should consider? Thank you!
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56 views

FSM with Counter

I have a state diagram that is consisted of 3 states and in reset it comes to state s0 then if an event happen on start signal goes to state 2 and statye there for 15 clock sycle and then after that ...
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+50

Quartus/SignalTap: Is there an equivalent to Xilinx's ICON, VIO, ILA IP-Cores in Altera's SignalTap?

Xilinx offers an Integrated Logic Analyzer (ILA) / called ChipScope. Altera's Quartus II comes with SignalTap - an equivalent solution. As an advance user\$^1\$, I'm using ChipScope as pre-compiled ...
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1answer
33 views

How to programm a Lattice board?

I wrote a few lines in VHDL and I declared pins into a lpf file for my Lattice MarchX03 board. But now I want to flash the board and honestly the documentation is very unclear. So I got Diamond ...
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32 views

Mealy Machine and registered outputs and delay increase

I am implementing an absolute value block containing a bit-serial Subtractor, the output connected to an 8-bit shift register which in turn connects to a two's complement block at the output there is ...
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36 views

Lattice FPGA - declare pin

I am learning VHDL and I am using the Lattice boards. I want to know how to declare a GPIO. I found the following block of code in the diamond software folder example. It is ".lpf" file and I guess it ...
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34 views

Trouble running picoblaze code

I am running a simple picoblaze code where I am using two addresses and sending a high strobe on both the addresses, the assembly code has no loop, so technically my code should run ONLY once but the ...
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42 views

Clock Forwarding Won't Work

I am trying to forward a global clock signal to an output pin. I am using a Spartan SP601 evaluation board, LX16CSG324. Refer to the end of this segment of code. I am using a 2.5 V LVDS differential ...
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41 views

NCO synthesis with VHDL

I'm trying to build a function generator with an FPGA. I can generate different waves at different frequencies but the problem is that I have a lot of jitter. I think the problem is the overflow of ...
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31 views

Altera Megafunction generics

I am using the Altera Megafunction LPM_ROM in one of my designs using the block diagram editor in Quartus. I want the ROM to have a configurable initialization file. For example for my component X ...
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77 views

X-Ray tube Current Control based on PWM

I want a control module to be implemented in FPGA(Altera Cyclone IV running on NIOS2) using VHDL which controls current flow to a X-Ray tube. The scenario is I have the expected current value say ...
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1answer
22 views

Clock Generation in modelsim

I am trying to verify a block I created using Modelsim but am having a little trouble with the clock generation. I would like the testbench to produce a 5ns (200MHz) clock using the code below... ...
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1answer
73 views

Simplest way to send data to and from FPGA

I've got a Basys2 board and need to transfer data between the FPGA and my PC(linux, transfer in both directions). It doesn't have to be fast, but it should be easy to implement and not take up to ...
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1answer
91 views

CDC Synchonisation primitives for an Altera FPGA

I am working on my first non-trival FPGA design and finally have a need for Clock Domain Crossing (CDC). There are multiple resources (amongst others) which discuss various architectures for CDC and ...
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32 views

How a vhdl netlist is used to synthesize a real circuit? [duplicate]

after a vhdl code is synthetized how the netlist is used to get real circuit? I mean... which tool, which process etc... It is just a curiosity.
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VHDL - Wrong result changing MSB of R2 input

I'm implementing a shifter using a similar strategy of T2 shifter. My implementation is in structural way but I have a problem. My code of Shifter is: ...
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VHDL - Structural strategy, is it possible to reuse components?

I implemented 5 Muxes that generate a mask, called mask00. My target is generating other mask using the same Muxes. My code is ...
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1answer
32 views

Standard integer width function in VHDL

I find my self using a function which returns the number of bits necessary to represent an integer value a lot in my designs. I define this function in each of my modules: ...
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57 views

Floating point multiplication

I'm trying to understand how to implement a floating point multiplier. In order to do that i've looked up at three books where basically the issue is threated in the same way (i.e. not handling of the ...
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29 views

How does T2 shifter work?

I would like to implement in VHDL a similar T2 shifter: In a book I read that the behavior of T2 shifter is based mainly in 3 stages: Let's suppose we have as inputs: R1 (64 bits, value to shift), R2 ...
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1answer
48 views

VESA CVT Standard - How to calculate video timings?

Most video resolutions like VGA (640x480), UXGA (1600x1200) or HD720 (1280x720) are defined by VESAs Coordinated Video Timing (CVT) standard. (It can be freely downloaded from VESA.org). The download ...
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1answer
42 views

VHDL: port map in process error

I'm designing an ALU in VHDL. In another file called adder16bit I've designed my adder and I want to use it in different ways e.g if the ALU_OP is ADD, I want it to do addition, if it is SUB, I want ...
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1answer
27 views

Restricting set of logged signals in GHDL

I have a large VHDL design with hundreds of internal signals. I need to run a simulation of it for a long time in GHDL, and based on a short test run, the resulting VCD dump would be ~50GB for the ...
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3answers
58 views

VHDL: Can a signal be used as an index for an aggregate?

Is it legal to use an integer signal in place of an integer literal as an index in a named association? I want to do so in order to create a decoder, like this: ...
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1answer
65 views

Cheapest FPGA PCIe board for Software Acceleration [closed]

This question is somewhat related to an earlier question: Cheapest FPGA's. I have been searching for a cheap FPGA board with PCI express 2.0 or 3.x support. Such boards can be plugged in one of the ...
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70 views

Is it possible to describe an unstable circuit in VHDL?

i was reading this (VHDL: Signal assignment question) post and i got curious about an issue that i wander if it could arise writing VHDL code. Is it possible to write the code for an unstable ...
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51 views

VHDL testbench variable clock/wave generation

A testbench for one sub-entity in my system currently defines a helper process to generate a clock-like waveform at the command of the main stimulus process. A simplified version of it is: ...
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2answers
66 views

Crossing a single-cycle spike signal from a fast clock domain to a slower one

I have a 1-bit signal coming from a part of my circuit that is running on a 40 MHz clock. The signal is mostly 0, except it is 1 for a single 40 MHz-cycle every ~million cycles. Another part of my ...
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1answer
46 views

Verilog #parameter

What is equivalent VHDL code of these verilog lines: dfslckd_q <= #TCQ DFSLCKD; dfslckd_rising <=#TCQ !dfslckd_q & DFSLCKD; Signals are all bit (TCQ ...
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Test bench with IO file vhdl

Is the following test bench correct? I tried to use a text file with the content 00 01 10 11 to test an architecture of an and port. ...
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1answer
29 views

Nesting entities in VHDL (Altera Quartus)

I want to ask a question. I'm trying to simulate a cpu. I did my schema and basically there are two logical parts of the CPU. The first part is composed of a FIFO buffer, Cache memory for ...
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40 views

Using different compilers in same vhdl project

I am currently working on a mips microprocessor for one of my class using modelsim's tools. I want to be able to work on the same projet whether I'm at home on my windows pc or on the go with my ...
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43 views

Soft ECC or Built-In ECC for Single Port RAM?

I have to implement Hamming Code ECC to Single Port RAM and True Dual Port RAM. At the moment 128 bit HC ECC has been implemented but takes more resources. I know that there is Built-In ECC and Soft ...
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1answer
28 views

VHDL: What does STD_INPUT and STD_OUTPUT appearing in std.textio mean?

The package contains the following lines: file INPUT: TEXT is in “STD_INPUT”; file OUTPUT: TEXT is out “STD_OUTPUT”; For some reason these remind me of the standard input and output streams from my ...
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1answer
69 views

Benefits of using Altera IP in FPGA designs?

I've just started using Quartus to synthesize a VHDL design that I created a while ago. Inside of this design are things like DFFs, decoders, etc. I noticed that Altera has IP of its own with the same ...
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1answer
45 views

Is it normal that a clock divider made with ring johnson counter has a momentary rising when the period changes?

I have made a clk divider using a ring johnson counter with D flip flop in VHDL. The point is that the signal output makes a momentary and unexpected rise during a change of period. As you can see in ...
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1answer
54 views

How to load std_logic_vector array from text file at start of simulation

I am trying to model a memory which shall store instructions for a processor design. These instructions are stored in a text file as 32 bit binary words. At start of simulation all values must be ...
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53 views

Concatenation in port mapping

Using Vivado 2015.2, VHDL. Got a warning "[Synth 8-1565] actual for formal port b is neither a static name nor a globally static expression" ...