VHDL (VHSIC hardware description language) is a hardware description language used in electronic design automation to describe and design digital systems such as field-programmable gate arrays and integrated circuits.

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how to design a pattern detector state machine in vhdl

How can I use vhdl to design a sequence detector to find a 32bit sequence with 15 zeros followed by 17 ones by using 2 counters to count ones and zeros that have enable and reset signals. Can anybody ...
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2answers
48 views

Access NEON coprocessor from programmable logic in Zynq

For the past few days I've been thinking about the neon coprocessor in the Zynq SoC and I have a question, is it possible to send instructions to the neon from the PL side of the SoC? Imagine I have ...
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1answer
40 views

for Loop Through String in VHDL

I'm trying to write a loop in VHDL that will print a certain message on an LCD screen. I have predefined the following: ...
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38 views

VHDL Code for 4x4 Mult: SYNTAX OK BUT ERROR:HDLCompiler:1029

Hello this is my first post here, I have some code that I've written that I'm having trouble with. I was hoping I can get some help. I'm having some issues with my VHDL code for a 4x4 multiplier. ...
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35 views

for loop iteration error

i am an amateur in vhdl and i have a big problem with it's for loop i'm trying to write an elevator program which would be for a four floor apartment! the problem that i have is i don't know why my ...
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2answers
55 views

VHDL timing question

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14 views

Pin Assignment in ispLEVER Classic

I have an ispGAL22LV10C that I'm trying to program. I wrote and synthesized the VHDL in ispLEVER Classic, but I cannot seem to figure out how to create pin assignments. Documentation on this is kind ...
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4answers
94 views

Are FPGAs more intuitive to learn than microprocessors for doing DSP

I want to learn to make DSP hardware I have never done any DSP and only a little bit of programming, but I have been making analog circuits for 15 years. I like the idea of learning FPGAs because it ...
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1answer
58 views

Why is my VHDL clock signal so far off from what I thought it would be?

I'm new to FPGA and VHDL. The following code was supposed to be 5MHz but I'm getting 4.167MHz on my scope. The FPGA board I ...
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51 views

Some question about RTL Design and VHDL

I have some question almost uncorrelated, so I'll enureamted it, hope you can help me: 1) I'm studing RTL Design, and the question is at level of data path, arithmetic unit ecc. I don't understand ...
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2answers
305 views

How does a structural architecture know which entity to use?

So I'm following this tutorial in which they explain some basic VHDL by using a four bit adder as an example: ...
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0answers
34 views

static variables in vhdl

Is there such thing as a static variable in VHDL? I'm tasked with using behavioural VHDL in creating a median filter for 3 8-bit inputs and want to keep track of the number of inputs. If they exist, ...
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32 views

Displaying signals in testbench from counter VHDL

Say I have a count signal in a counter VHDL file and want to display this in my simulation output, what would I have to do to my testbench to output such data?
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41 views

Implementing clock divider VHDL

I have written a FSM using a clock divider with the source frequency being 5MHz and trying to take it down to 3 for simulation sake but the clocks come as U in the simulation like so : I am ...
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46 views

Cycles lost on clock domain crossing

I have a MAC (VHDL) connected to the PHY through RGMII (so the clock for this communication is 125 MHz). The MAC outputs every byte at a rate of 200 MHz, so there is some clock domain crossing here. ...
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25 views

Using on board SPI of Basys 3 to store custom data

I have a Basys 3 board which has an on board SPI flash memory. Configuration bitstream of the implemented logic can be written to this memory through vivado. Reference manual of the board says that ...
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1answer
40 views

Test cases for a calculator test bench in VHDL

I just wrote down a calculator core with VHDL which actually does a multiplication, additon, an Xor operation and an AND operation and I have to write a test bench which should simulate all four ...
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2answers
79 views

How to convert data before sending it to FIFO [Xillybus - VHDL]

I connected my own FIFO to xillydemo. More precisely, xillydemo receives some data, it has to convert the data and the forward the data to FIFO. in turn the FIFO should send data back to xillydemo. ...
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0answers
30 views

Program does not output when number of element into FIFO are less than FIFO depth & FIFO fills only one element [Xillybus - VHDL] [duplicate]

In my program I created a FIFO (STD_FIFO) which is connected to xillybus. Here xillydemo.vhd ...
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72 views

VHDL program does not fill array of STD_LOGIC_VECTOR [Xillybus]

I have developed a VHDL application with xillybus that forwards the input data to STD_FIFO. The STD_FIFO.vhd instantiates Memory, that is an array of ...
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2answers
60 views

Reading image, sound, binary file from nonvolatile memory for FPGA

For applications that require design on FPGA which shall make use of several image files, sound files or other forms of files, can they be simply included in the FPGA design configuration file? In any ...
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1answer
118 views

Boost performance buffer application [Xillybus - VHDL]

In this previous question link I had developed an application that sequentially did: get and store 8 input values (8 characters) swap upper to lower (or vice versa) case only the first char output ...
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3answers
92 views

Meaning of strong and weak drive in VHDL?

What is the meaning and effect of "strong" and "weak" drive shown by (0,1) and (L,H) in VHDL's package ieee.std_logic_1164?
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93 views

VHDL simulation shows 'X' for input

I'm new to VHDL and I'm trying to simulate an array multiplier.(I have used verilog before). However in the simulation results it shows 'X' for inputs which used to be '1'.Here is the result: And this ...
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29 views

VHDL: Is alias only used to refer to subset of std_logic_vector?

I have seen alias declared to control subset of a big std_logic_vector. What are other applications of it?
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2answers
111 views

Copy data into read_device_file after EOF from input text [Xillybus - VHDL]

I have developed an application that is able to: 1. get and store 8 input values (8 characters) 2. swap upper to lower (or vice versa) case only the first char 3. output the eight characters ...
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2answers
93 views

Understand VHDL Code

I've been learning VHDL coding for the past two weeks to be able to understand the VHDL code of what I'll be working on. In other words, I'm still a beginner and I need help understanding some codes ...
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1answer
47 views

VHDL to Verilog conversion for Parking Sensor

I am trying to do parking sensor with verilog and I have its vhdl code and trying to translate it to verilog can you please help me to find out what is my problem. There is no error the error is only ...
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2answers
94 views

Why does VHDL function declaration not accept bounds for the return type, e.g. std_logic_vector?

I know that in VHDL each function call is instantiated as a separate combinational circuit. I am writing a function that takes in a 4 bit value and returns a 7 bit value from a look up table. The ...
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68 views

Benefit of using RAM, or some form of internal memory on a FPGA

I am at moment trying to store an image onto an FPGA. I calculated the space required by it to be 19200 kb, and are therefor wondering whether i should store it some other way than a 2d array?.. Or ...
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1answer
76 views

How to give analog input from 3.5 mm jack to FPGA (Spartan 3e)

I am working on a voice transmission project by using Spartan 3e. My code works just fine. My problem is that I give analogue input to adc side by using a potentiometer and see the changes (as ...
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2answers
44 views

VHDL: How does one assign custom values to identifiers of an enumerated type?

For a design with seven segment displays, it will be easier in modelsim simulation if one can see the actual display value going into the seven segment display e.g hexadecimal D which is "1000010" in ...
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1answer
44 views

Converting Bin-to-BCD code from VHDL to Verilog

Hello guys I am trying to translate following VHDL code to Verilog, however it does not work even if they look like pretty same. I get no errors however it is not working with Verilog one but works ...
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25 views

P&R using Sfixed signals in Xilinx ISE

In my filter design , I am using fixed point arithmetic and using sfixed for signals. The design synthesizes with all timing met but my functional simulation and post synth/P&R simulation do not ...
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1answer
59 views

Artix 7 Block RAM instantiation in Vivado 2015.2

Ok I'm trying to create a Block RAM instantiation in true dual port type. I have used the IP catalog and block memory generator in Vivado, which has given me a giant file that I now need to strip down ...
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6answers
237 views

What determines the number of pixels in front porch and back porch of VGA display?

Besides this, is pixel clock dependant on the VGA resolution and referesh rate or independant of them? What does one know what duration each pixel should have?
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67 views

Multi-driver net found

I have been putting together a project for work in Vivado 2015.2 When I try and implement the design I get these errors. The project is pretty large that's why I haven't included it in the post. Is ...
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1answer
104 views

swapping char VHDL FPGA [closed]

I want to develop an application that is able to get and store two input values, swap from lower case to upper case only the first value and finally output the two stored values. E.g.: if the input ...
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1answer
244 views

Storing values on variable fpga vhdl

I want to develop an application that is able to get and store two input values and then output the two stored values. E.g.: The input string is "John". The application should get "J" from ...
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2answers
105 views

if else statements

I am trying to understand how if else statements and clock work. My application accepts chars as input (), and for each char the application should go into the if else statement. Here the code: ...
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2answers
140 views

clock in testbench VHDL

I'm using GHDL. After various update of this thread, under advice, I try to do the simpliest configuration of a testbench with only clock signal. The code compiles correctly, but when I run it ...
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1answer
17 views

Xilinx Coregen FIFO as ZeroDelay model

My VHDL design contains a FIFO generated by Coregen from Vivado 15.3. I try to debug the design with a ZeroDelay simulation. But the core is not Zerodelay and makes short changes (much shorter that a ...
4
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1answer
269 views

Pulse on edge of different clock

I have a clock coming from a pin (GMI_CLK). It passes through a PLL and a new clock with 4 times the frequency is generated (Sys_CLK). Now I need a pulse each time a rising edge of the original clock ...
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2answers
55 views

VHDL - using PORT MAP in CASE?

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2answers
36 views

Signal becomes undefined when used in process

I'm having problems with this VHDL code where the value of new_state isn't being transferred onto the signal state_cnt and is instead becoming undefined. What do I need to change in-order to get ...
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1answer
57 views

Buggy VHDL UART receiver

I'm trying to get a simple UART receiver working and am close but I'm receiving slightly off values (some bits are shifted a couple places from where they should be). Based on this answer I tried ...
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1answer
51 views

How to assign an input to a switch? [closed]

I'm currently working on an 8-bit adder that instantiates a full adder. I have to assign 17 switches as inputs a , b and Cin. How can I do that?
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1answer
49 views

VHDL To verilog translation query

I am trying to convert highly parametrized VHDL code to verilog. This VHDL code uses good amount of packages and records and I couldn't find the substitute for those in verilog. Also I am just 3 days ...
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57 views

VHDL: TextIO, End of Line, Hread

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3answers
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When to use State Machines - FPGA

I've read a lot about FSMs (Finite State Machines) when doing VHDL tutorials. They are easy and I've used them a lot but I still don't understand something and can't find the answer online: When ...