VHDL (VHSIC hardware description language) is a hardware description language used in electronic design automation to describe and design digital systems such as field-programmable gate arrays and integrated circuits.

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Shift Register Vs Multiplexer

I am not sure about an implementation. I've a multiplexer 8 input, 1 output and 3 select signal. One of these selects signal sequentialy acquires all value of a bit vector. Now I can choose 2 way. ...
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48 views

VHDL How to Design a Screen (Frame) Buffer

I am trying to use a screen buffer to store, change and output the bits of a video data to the DVI transmit interface. I am using Altera Cyclone III development kit. I will be using 1440x900@60Hz ...
2
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36 views

VHDL - Quartus II inferring latches on circuit

My circuit is based on a state-machine. I checked it and it's working fine, the only issue is that it's inferring one latch per flip-flop (The state machine has 11 states and the circuit is one-hot so ...
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36 views

VHDL - Flip Flop inferring on a signal

I have to design a circuit to count up to a number and return to zero. It must have a carry signal (which I named a_o in my circuit) as flag to show that the ...
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1answer
57 views

Using a Counter to Determine next MSB position in polynomial division

I am working on implementing a polynomial divider the operation is as follows: Check MSB of Numerator: if 1 XOR with Denom then shift Denom right if 0 Num is the same and Denom also shift right When ...
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33 views

Binary/Polynomial division on FPGA implementation

I am beginning the implementation of the polynomial binary division algorithm now as I understood i will be checking the MSB bit if 1 to XOR and shift the sum if 0 I will only shift. What I am not ...
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1answer
51 views

Signed Addition of two std logic vectors while looking for overflow and carry

I have what I think to be a working implentation for finding the sum of two signed 32 bit (std_logic_vector) vectors in which I chose to expand the result to always have 33 bits so as to preserve the ...
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2answers
49 views

What does delta stands for in ModelSIM?

I ran a simulation for a combinational logic circuit with 8 inputs, 4 outputs inside MODELSIM. When I view the simulated waveform everything looks fine, however when I export result to a list file ...
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26 views

VHDL: Simulating Delay for ISE UNISIM components

I have extracted VHDL source of my design from Xilinx ISE. It uses UNISIM library to model Look-Up Tables and Flip-Flops and other components. When I simulate my VHDL design (a combinational circuit) ...
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56 views

Races in sequential circuits VHDL

Do I need to be aware of races while writing code for sequential circuits in VHDL ( I use ISE Design Suite ) ? If I do not, what is the matter that solves the races issue instead of me ?
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75 views

quartus signaltap not accurate?

I am using Quartus SignalTap to debug my FPGA design: I always been persuaded SignalTap is not accurate !! This is what i found: I monitor the reset signal with SignalTap :Reset toggles around, ...
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1answer
64 views

The timing-driven placement phase encountered an error

Could someone explain inexperienced VHDL coder what this error message trying to tell me in simple words? I found a similar question here, but here was no answer to it: ...
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39 views

Timing/buffering issue with Digilent's EPP on Basys2?

I have a Digilent Basys2 FPGA, and I'm implementing the EPP interface described in http://www.digilentinc.com/Data/Products/ADEPT/DpimRef%20programmers%20manual.pdf. This allows a program called ...
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69 views

Using one channel from adc (pin connections) [closed]

For a heart rate calculator project by using Basys2 and VHDL, I am trying to connect ADC0808 in order to get 8bit digital output from my pulse sensor's output. However, although I designed the circuit ...
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1answer
69 views

Functional and Timing accuracy of an RTL Model

I am sometimes really confused by the abusive use of jargon in EDA/VLSI design articles and books. With no precise definitions, its upto the reader to make interpretation which is very ambiguous and ...
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1answer
63 views

FPGA based theremin , is possible?

I remember a while ago , i saw some Digital based Theremins circuits from glasgow university... http://www.theremin.info/-/viewpub/tid/10/pid/65 would it be possible to make a theremin by using an ...
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1answer
65 views

VHDL RS-232 Receiver

I have been trying to design an RS-232 receiver taking an FSM approach. I will admit that I do not have a very well-rounded understanding of VHDL, so I have been working on the code on the fly and ...
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1answer
44 views

Integer to std_logic type conversion

I want to assign the value of a generic that is an integer to a signal which is a std_logic type. My generic can take only two values, 0 and ...
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2answers
52 views

Why does this adder need two clock cycles (two pushes of the button) to display a result?

I'm implementing a simple adder with carry out in VHDL on a BASYS2 board. This is the code below: ...
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2answers
64 views

How to best synthesize a systolic circuit on FPGA?

I am developing a parameterized systolic circuit in VHDL, using generics. It exhibits regularity in 2 dimensions. I am about to synthesize it on Xilinx FPGA. I suspect it is worth informing the ...
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81 views

LFSR Using D Flip Flops

I am fairly new to the VHDL language and I will admit that I primarily use it for educational purposes. I have been attempting to design a data encryption circuit using D flip flops. Obviously, an ...
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1answer
92 views

LED PWM controller

I want to create Led PWM controller and I tought it is easy but one line in my code generates more warnings than all my previous little projects. Here is the code: ...
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1answer
48 views

Implementing a counter in VHLD with edge triggered clear

I'm still giving my first steps learning VHDL and after a couple of days I could not yet find a solution for this problem. What I'm trying to do is to implement an LCD controller on an Altera MAX II ...
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37 views

Balanced partitioning turned off?

I am programming with a CPLD of Lattice Semiconductors (ispMACH 4000ZE) and the program ispLEVER Project Navigator. I want to implement a quadriture counter. First I implemented the counter only for ...
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6answers
664 views

What is the difference between testing and verification?

Every textbook I've seen makes a big deal of the fact that testing and verification are two different concepts. Yet none of them provides a clear (or clear enough to me, at last) distinction. To ...
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2answers
154 views

UART Receiver glitches

I encounter problems with my UART receiver module. It is supposed to work at 9600 bauds without parity bit and only one stop bit. The problem is that my UART misses some characters (or to indicate ...
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90 views

Signal(s) form a combinatorial loop VHDL

I was trying to implement Dual-priority encoder but I get following warnings during synthesize: WARNING:Xst:2170 - Unit prEnc : the following signal(s) form a combinatorial loop: done, first<3>, ...
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88 views

VHDL delay mechanism

I have difficulty understanding how the delay (mainly inertial delay: AFTER) mechanism works in VHDL. I'll start with this: target <= waveform AFTER 3 NS; As ...
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30 views

Component instantiation in VHDL

I need some help with component instantiations (port maps) in VHDL. I have a 16 bit Full Adder which I want to import in my ALU, and it should trigger when the ...
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46 views

Using explicit registers in RTL designs

Is it a good practice to use explicit register IPs in RTL designs? For instance, having separate IPs for each type of register and instantiating them in the design instead of coding them on-the-fly. ...
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2answers
168 views

How does someone initially design a digital system for HDL?

So I have really been hitting the example code hard this week in an attempt to better understand some HDL design basics, specifically FPGAs with VHDL. The book I am using (if anyone is interested) is ...
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174 views

Is it possible for a VHDL component to have multiple architectures?

Just a thought I had: is it possible for a VHDL component to have multiple architectures if outputs are not modified by both? If so how can we select the one to use at synthesis time (like the C ...
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1answer
254 views

is 'Ok' important when sendin AT commands to modem

I'm currently using VHDL to program the FPGA Spartan 3AN Kit-set. The objective is create a programme to send an SMS to a mobile phone, using the Kit-set via the modem. I'm done with the transmit ...
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1answer
67 views

Can oscillations occur in VHDL with concurrent statements?

Imagine we had two concurrent statements that depend on each other: ...
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69 views

Doubt about counter implemented in VHDL

I'm trying to learn VHDL and I came across some example code for a counter that I find somewhat strange. I understand what it does but I'm not sure why it is written the way it is. The code is the ...
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2answers
65 views

register without clk

I'm designing a small system in VHDL using the datapath and contorller method. Is it okay if I design registers that don't have a clock input (load data on the rising edge of the load signal) as they ...
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1answer
75 views

How to reduce an ALU logic with the minimum logic possible? Its very challenging

Our professor wants us to reduce 8 function alu (8 outputs) to a 4 out ALU that has capability to implement all the 8 functions. We can use any gates(even aoi's), muxes, and can create our control ...
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3answers
452 views

What would make me choose Verilog or VHDL over schematic design on CPLDs or FPGAs?

I have absolutely no background in programmable logic, I use mostly microcontrollers in my projects but recently I needed to work with video and the microcontroller is just too slow for what I needed ...
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48 views

VHDL indexed part select

Is there a way to do indexed part select of an array in VHDL as in Verilog? I know that you can use an array but creating a new type seems overkill to me. Moreover it's possible to slice an array ...
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241 views

FPGA Test Equipment

I mostly have desktop software development background. Trying to learn hardware design. Question: The question is mostly for developers (mostly individual contractors) who develop for any expensive ...
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51 views

What CPUs use a skewed associative cache?

What CPUs use a skewed associative cache? I see several people imply that, with roughly the same hardware, a skewed-associative cache often has better performance than a traditional set-associative ...
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1answer
118 views

Difference in the datapath of Load Upper Immediate to Load Word in a 32 bit MIPS processor

For the MIPS insturction Load Word I have got the following Datapath: How does the datapath for the Instruction ...
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1answer
74 views

VHDL internal signal assignment

I am new to VHDL and tried to implement a simple example from a book, what represents a 2bit register and the testbench. Compiling the files works well, and signals the stimulate the register (reset, ...
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1answer
58 views

Delete or ignore I/O from a schematic block in Lattice?

I am programming with a Lattice ispMACH 4000ZE Pico DevKit and with the software ispLEVER Classic Project Navigator. I want to use in my schematic file the OSCTIMER block from the Lattice library, but ...
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1answer
108 views

VHDL USB UART Problem

I've just described an UART transmitter and receiver in VHDL. In simulation everything seems to be fine. In FPGA, the loopback interface works well: I push a button, the transmitter sends data, the ...
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2answers
60 views

Quartus FPGA migration issues

I have an FPGA design Quartus that compiles and works correctly for a cyclone IV EP4CE15F17C8 (42% used). I'm trying to migrate same design to a smaller FPGA EP4CE10F17C8, but when changing FPGA ...
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1answer
72 views

OLA adder and signed digit vhdl design problem

I have implemented the following online adder for signed digit using vhdl code and I have simulated my design according to the example table shown in the figure attached the problem is I am not ...
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2answers
78 views

Uploading C program to the ARM core for execution through ethernet!

I want to write a c code on my local PC and upload it to ARM core on Zed-board for execution. I know we can do it using JTAG, but for obvious reason I want to use Ethernet interface. I will be glad ...
0
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1answer
70 views

How to make valid harness port when generate sub-sheet from vhdl

I have an VHDL file (a block) with huge count of the different port that can't combined into the one bus because they have different names. These signals will be further connected to different parts ...
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69 views

VHDL test bench file not accepting all set of inputs

My VHDL test bench here is not accepting the third set of inputs and is looping back to the start of the process. Please help me. Code: (comp4bit.vhd) ...