VHDL (VHSIC hardware description language) is a hardware description language used in electronic design automation to describe and design digital systems such as field-programmable gate arrays and integrated circuits.

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Store consecutive UART inputs to register

I have implemented a UART receiver/transmitter (8-bits) in VHDL for use on a Digilent Nexys 3 FPGA. So far I have managed to read inputs in a FIFO, process each byte individually and write the output ...
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23 views

VHDL JK Flip-Flop with logic gates

I am trying to make a JK flip-flop in ActiveHDL environment. I want to make it with logic gates. It should look like this: This is my code: ...
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22 views

Using the ROM megafunction in VHDL code

I have created a ROM megafunction using the MegaWizard plug-in Manager. This created a new file which I named rom.vhd. My code: ...
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47 views

minimize fpga frequency clock [on hold]

who i want to add a second loop to this code to minimize more frequency of clock 50 mhz : ...
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47 views

Necessary tools/environment for writing VHDL RTL? [closed]

I decided to implement my own MIPS computer using Digital Design and Computer Architecture book. I decided to use VHDL since Peter Ashenden's "The VHDL Cookbook" I think is a great starting point. If ...
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1answer
32 views

VHDL - Why does frequency divider counter max at one less than half period?

In this tutorial on creating a frequency divider in VHDL, we transform a 50MHz input into a 200Hz output with a process that counts from 1 to 124999. The guide offers an explanation for why 124999 is ...
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3answers
46 views

How to define a clock in Quartus II?

I have this piece of code here: ...
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40 views

VHDL - does sequential component need to know whether input comes from clock?

If I have some component that represents a sequential circuit (or sub-circuit), e.g. an SR-latch within a D flip-flop, do I need to know which inputs are clock-based? Often sequential components seem ...
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51 views

FPGA SPI slave not working well

I'm tring to integrate a SPI Slave in VHDL (opencores) http://opencores.org/project,spi_master_slave the idea is to interface a Microcontroller and an FPGA I'm Using Quartus.. more info: ...
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46 views

VHDL synthesis doubt

Does the synthesis tool consider an initial value of a signal given before begin of the architecture. What happens when this value is not a constant but another signal. is it better to provide ...
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2answers
56 views

VHDL difference between component and subprogram

I've read different article (and book chapter too) about "component" and "subprogram". What i don't understand is what is the difference between the two... I mean, i know that the component make ...
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1answer
44 views

How to feed data into a PCIe hard IP?

I want to implement FPGA module which can communicate using PCIe. I am using Stratix IV GX which has PCIe Hard IP in it. How I can use this Hard IP module to communicate. To develop my module I ...
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40 views

VHDL: Read 4 bytes from 8 bit data bus

I have a module in VHDL that reads 32 bit at the time, the memory on the board however have a 8 bit databus and a 20 bit address bus. The memory have 10 ns (SRAM) access time, I was thinking that I ...
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69 views

Modelsim (vcom-1491) Empty source files

I am trying to compile a design in modelsim (which I am new to) and I keep getting the following error for one of the files... (vcom-1491) Empty source files. I ...
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23 views

Post Map simulation reliability

I'm designing a module in VHDL for an FPGA. My module is added to already existing design. It has a Wishbone slave interface. The IDE (Lattice Semiconductor Diamond 3.2 ) allows to do post map ...
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1answer
38 views

How to tell pin planner to not connect an IO signal

In my CycloneV design, I have a 64 bit GPIO port but I only want to connect 40 pins in my design. If I left it unconnected, Quartus will try to place it and will generate an error because of there ...
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2answers
58 views

VHDL Overmapping and Time Constaint issues in Xilinx-ISE

I have an issue with a module I use for rotation of a vector. I have two operations one uses 2 rotLeft modules and the other uses 2 rotRights. Originally I had occupied Slices overmapping issues which ...
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1answer
29 views

VHDL synthesizing a module doesn't work, but simulating it does. Error: Bad synchronouse description

I am wondering why synthesizing this code doesn't work, but simulating does. ONLY WHEN TRYING TO SYNTHESIZE I get the following error: Signal sig_enable cannot be synthesized, bad synchronous ...
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51 views

Turning on individual segments in 7-segment LED

I'm working on VHDL code that takes a BCD digit and outputs the Hex equivalent of the BCD digit on a seven-segment LED. I want to specify that, if the BCD input is not valid (i.e. it can't be ...
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51 views

Edge detector issue

I've a stupid problem and I don' figure out how I can solve it. In my design I'm using a rising edge detector. The problem is that ActiveHDL doesn't simulate it in the way that I expect. The VHDL code ...
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55 views

Can't run 460800 baude rate on Nexys2

I have Nexys2 Spartan 3E board and I am running Ken Chapman's UART IP core, I need to transmit data to another device at a baude rate of 460800. I was successful in sending data at 115200 and 9600 ...
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26 views

Reducing noise from an input using an FIR in VHDL

I have a non digital input I want to read in my VHDL file but it has sooo much noise that I would like to filter out using a digital filter that would sample the signal and allow pulse levels that ...
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1answer
68 views

Is there an easy way to physically implement a simple digital circuit?

I designed a digital circuit which, in total, has about 27-30 gates. Building that circuit in real life using a 74 series IC would mean using a lot of through hole/SMD chips, which wouldn't be ...
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49 views

serial adder written in vhdl code (structural behavior)

How to write a code in VHDL using structural behavior --i try to write the code for the structure but can't connect them to each other the design like this image exactly...with clk for each register ...
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2answers
58 views

How do I build and use my own VHDL library?

I am trying to create a components library in VHDL. I have many .vhd source files with different components. Ideally I would like to be able to instantiate them in a design using the same method as a ...
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1answer
39 views

Using Enable to switch between two Decoders

I am trying to put an enable input in a 4-to-16 decoder so I can select between two decoder. Here is a schematic: I am using two decoders to select two different addresses in a 16x16 SRAM. I am ...
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1answer
82 views

Need optimization advice

I'm developing an application with goal to achieve maximum throughput from device. By throughput i mean maximum amount of "cores" running at max frequency. So, we have: Virtex-6 XC6VLX240T, ISE 14.4 ...
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25 views

Digilent EPP handshaking problem

I intend to use my Spartan-6 board as an interface between my mic (which produces I2S data) and PC for live recording. Since UART is too slow, i planned on using Digilent's parallel interface with ...
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1answer
30 views

how to calculate Hermitian Toeplitz system of equations on fpga in vhdl

I'm trying to write vhdl code to solve the Hermitian Toeplitz system of equations (solving for the A's). ...
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1answer
72 views

How does System Generator for DSP actually works?

I'm developing control algorithms on FPGAs. By now, we use hand-written VHDL code for our fundamental entities we combine to more complex IPs, all done manually. In my opinion, this is not satisfying. ...
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2answers
92 views

How can I implement a simple, Q only, D-latch using VHDL?

I just started VHDL today and I'm the type of person that can only learn by doing stuff, so after I made some basic gates in VHDL, I tried making a simple D-latch(so no clock signal), however without ...
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68 views

display FPGA frequency on oscilloscope?

I used sparten 3e starter board.i want to DISPLAY the PWM frequency output on Oscilloscope?which output pin i have to used ?I used J1 and J2 .the signal is distorted .why? How ? please
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59 views

Gate-level design with a Smartfusion2

I am working with a SmartFusion2 FPGA, and I am trying to implement a fine delay line. For that, I would like to control exactly the content of some LUTs, to get cells with no logic properties but ...
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1answer
69 views

VHDL and how they work

I'm sorry if this has been asked before and I know its such a broad answer but i'm confused about some parts of VHDL. The part that is confusing me is does the VHDL go on the platform or is it merely ...
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46 views

Should I use a buffer or a simple output with a signal?

When I implement a clock divider, I often wonder whether I shold use a buffer or a regular output with a signal. Consider the following codes : Option 1 - Output with signal ...
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1answer
27 views

Assign result of comparison to std_logic

I'm trying to design an eight bit subtractor. The operands are declared as \$\mathtt{std\_logic\_vector}\$ and the borrow out is \$\mathtt{std\_logic}\$ type. Is there a way to directly assign the ...
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1answer
42 views

Wallace tree multiplication rules

I was looking at this wallace tree diagram for an 8x8 multiplier: and I'm confused about why the pairs of two (and the one pair of 3) are not added together in the initial reduction layer. My ...
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1answer
73 views

blinking a display using trigger

I've been banging my head over this for a while now, basically I have this display driver that in normal conditions would update a seven segment display continuously. What I would like to do, and I'm ...
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1answer
59 views

ise complaining index out of range, but it seems to be in range?

I'm righting a vhdl module that calculates the LPCs from incoming DT samples. My ise editor is complaining that my index is out of range. Is there any reason anyone can see that it should be ...
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60 views

8 Bit Register in VHDL

I am new to VHDL programming and am currently designing an 8-bit register as shown in the picture below: Below is my VHDL code for the design: ...
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29 views

turn on led using external light dependent resistor (LDR) with nios ii and qsys design

I want to use qsys and nios ii to design a system that uses an external ldr to turn on led on an altera fpga.how can i go about this, what are the components i need in my qsys design and how to ...
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33 views

Using signed() conversion in VHDL

I was wondering why I am unable to use this in my logic Y<= '1' when (signed(A) < signed (B)) else '0'; Y, A, and B are all std_logic_vectors. I am using ...
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1answer
108 views

What are some things that can be done in VHDL but not in verilog and vice versa?

VHDL and Verilog are quite similar but do not have the same features, there is certainly a massive overlap though. What are some things which are easier to do in VHDL but not so easy or even ...
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2answers
111 views

SystemC vs HDLs

I am currently involved in a university project to implementing a processor of an existing instruction set. The idea is that by the end of the project I should be able to synthesise this design and ...
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1answer
125 views

Convert C to FPGA

I'm new to programming for FPGAs so I was recommended to use some available C/C++ to VHDL translator. Problem is, there are tons of information out there and almost all good programs need an ...
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3answers
141 views

How can I view, debug, or analyze data being input to my FPGA?

I'm working with a Xilinx Spartan6 on Digilent's Nexys3 board. I've also purchased their PmodMIC so I can try to get some audio data onto my board to perform some signal processing. The ...
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89 views

7 Segment display driver issues

I have this code for driving a seven segment display for hex. From my understanding its logically correct, but when I try and run it on my Nexsys 3 board I never get the correct output, it seems that ...
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4answers
662 views

How is this simple counter implemented on an FPGA without a clock?

As part of an assignment, I must create these blocks that tie in to a larger top level module. (there are more blocks not pictured). I have everything working fine, except this UP/DOWN counter ...
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63 views

VHDL code Process

Question: change z <= y AFTER 30 ns to z <= y after 15 ns why after the change above ,the value of w never ...
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309 views

Unexpected results when multiplying in VHDL

I'm trying to make a simple BCD --> binary conversion operation work in an ALU I'm coding. All the other operations work perfectly fine, just this last operation doesn't work for some reason. I've ...