Tagged Questions
0
votes
2answers
132 views
Statemachine as a separate module in VHDL?
I would like to create a state machine as a separate unit with multiple inputs and one output. The output will be the state.
The states are defined by a syntax similar to ...
1
vote
2answers
148 views
State Machine using Case getting unexpected result
I am trying to write a very simple state machine that implements a combinational lock.
The code is: Switch1 -> Switch2 -> Switch3 -> Switch4
I realize that it is Switch 7, 6, 5, 4 accordingly in ...
1
vote
2answers
110 views
Signal assignment type
What is the meaning of "combinational assignment" and "registered assignment" to signals? In particular what are the differences between these two types of assignments?
-1
votes
1answer
195 views
FSM Using Excitation Equations and VHDL
I have been trying to create a FSM using the excitation equations I developed. I have not had much luck. The circuit has no output.
I DO NOT WANT TO USE 'TYPE' and custom state types. That is the ...
