A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices).

learn more… | top users | synonyms

1
vote
1answer
68 views

How to understand the timing report after synthesis?

After synthesis of my verilog code. I am getting the below timing report. I think it showing any mistake in my code. Timing Summary: Speed Grade: -2 Minimum period: 2.334ns ...
1
vote
1answer
42 views

How do I understand report published in console tab after simulation in Xlinx?

The report is : Started : "Simulate Behavioral Model". Number of CPUs detected in this system: 2 Turning on mult-threading, number of parallel sub-compilation jobs: 4 ...
1
vote
1answer
28 views

How should I translate old TIG statement from UCF to new Vivado XDC files?

I have a short UCF file with the following content: ...
0
votes
0answers
18 views

How can I use wildcard matching in Xilinx xdc files 'get_ports' TCL command?

I'm porting my Xilinx UCF files to the XDC format for a 7-Series device. The UCF file is looking like this: ...
0
votes
0answers
40 views

Soft ECC or Built-In ECC for Single Port RAM?

I have to implement Hamming Code ECC to Single Port RAM and True Dual Port RAM. At the moment 128 bit HC ECC has been implemented but takes more resources. I know that there is Built-In ECC and Soft ...
1
vote
1answer
39 views

how to interpret the RTL report after synthesis in Xilinx?

I did verilog code of a circuit. It was simulating well and giving output correct after Simulation. Now i did synthesis, the RTL schematic after synthesis showing some green and red box. Is it ...
0
votes
1answer
58 views

FPGA - Data transfer via Ethernet

I have a Verilog module that is able to make my FPGA blink its LEDs at frequencies according to certain variables/constants I've set within the code. However, I would like to change these variables ...
1
vote
0answers
41 views

Concatenation in port mapping

Using Vivado 2015.2, VHDL. Got a warning "[Synth 8-1565] actual for formal port b is neither a static name nor a globally static expression" ...
1
vote
0answers
48 views

Why won't the Xilinx block RAM in a Spartan-3E consistently return data in a single clock cycle?

I'm creating a design using Verilog on a Xilinx Spartan-3E (XC3S500E) that uses multiple dual-port block RAMs, all instantiated through Verilog primitives such as ...
1
vote
0answers
59 views

Why am I unable to use a pin marked as GCLK in the datasheet as a clock resource, when an identically-marked pin works, on a Spartan-3E?

I am trying to create a sequential circuit on a development board with a Xilinx Spartan3E XC3S500E in an FT256 package. The board has a 50MHz crystal oscillator connected to pin B8, which is marked as ...
0
votes
0answers
36 views

Connect Axi DMA to multiple inputs

I have a Vivado HLS block which accepts 5 input streams like so: ...
1
vote
1answer
37 views

Zedboard Linux Socket Application Error

After creating the linux boot image from the tutorial for the zedboard, I tried creating a socket application to talk to the computer. The Zedboard would be the server and the program in visual studio ...
0
votes
0answers
36 views

Why can't ISE map the BTNRST pin of the Atlys board?

I want to use the Reset button of Digilent's Atlys board, but ISE can't map the pin because the site type is not an IOB (it's an IOBS, see section 6 of this question). As far as I can see there is no ...
1
vote
1answer
81 views

This design does not fit into the number of slices available in this device

Below is the device utilization summary for the design(Zynq 7010) and the use of Slice LUTs exceeds the availabile number. Previously it was 82% and now it exceeds after adding a block of checksum ...
1
vote
1answer
55 views

Axi DMA correct parameters

I'm making my design with Vivado HLs and Vivado and I'm doing some somewhat big transfers between DDR and my custom IP block and vice-versa. Each transfer from DDR to custom IP is of 256x256x4=262144 ...
0
votes
1answer
22 views

Unable to open XPS from PlanAhead(Xilinx ISE 14.3)

I am unable to open Xilinx Platform Studio(XPS) from PlanAhead. It shows me following error messages: I have not opened multiple sessions of it. I have also removed the write protection for that ...
0
votes
1answer
55 views

PAR taking too long - Xilinx ISE

I am trying to compile a project and it takes a very long time to route. - ISE 14.3 In my main module, I am using a package where I have declared an array of constants. These constants use functions ...
0
votes
1answer
17 views

Coolrunner2 GSR Global Set/Reset

So the Coolrunner2 CPLDs have a feature called GSR or "Global Set/Reset". In the documentations I found lots of references to it but no chapter that tells me how the GSR exactly works and more ...
0
votes
1answer
27 views
0
votes
1answer
27 views

Change PL clock

I'm designing my project in Vivado and I had a WNS (Worst negative Slack) of -2.67 ns (my PL clock was 200Mhz). I had some problems when running my design since the results where good sometimes and ...
2
votes
2answers
80 views

How to analyse timing report for Xilinx FPGA

I'm trying to learn FPGA programming, my test project is a 5 stage pipelined MIPS CPU, which works. Up until now I have been optimising for area utilisation, however this has caused a very slow clock ...
1
vote
2answers
46 views

Component Not Found VHDL XILINX ISE

i know this might be a very simple question . i have to simulate some delays for various adders in ISE Suite . ( i'm a little familiar with vhdl concepts but ISE Environment , not at all ! ) this ...
0
votes
0answers
33 views

Axi DMA asynchronous

I was reading the Logicore of the AXI DMA and I saw this: Setting Enable Asynchronous Clocks enables asynchronous mode and creates four clock domains. This allows high-performance users to run the ...
0
votes
0answers
35 views

Design timing Summary - Xilinx

(Working with a Zedboard) I made a design in Vivado HLS, selecting a period of 200Mhz. In the synthesis report I can see that the estimated clock is 5.24ns with an uncertainty of 0.63. I decided to ...
1
vote
1answer
37 views

PlanAhead 14.7 multiple runs issues

My project in PAhead 14.7 have 6 different synthesis run and 6 implementation runs. Each implementation run have her own parent synthesis run. The differences between synthesis runs are some generic ...
0
votes
0answers
38 views

Axi DMA maximum velocity and DCache clarification

This is a 2 question in one thread. I'm basing my model on the matrix multiplication example. First set of questions: After some optimizations I have now a MM2S velocity of 1009 Mbytes/s and a S2MM ...
0
votes
0answers
31 views

HDLcompiler warning189

I am new to xilinx and verilog and am trying some basic stuff when I got this error. I know we can define input and output bus sizes using parameters like parameter width = 32; output [width-1:0] ...
0
votes
0answers
18 views

MatrixMult modification - Xilinx

I was following the example of the matrix multiplications present in here. As my objective is different since I don't need to multiply matrices but only all the elements of the entrance matrix by ...
0
votes
0answers
23 views

Xilinx ap_axiu parameters

I'm using ap_axiu from ap_axi_sdata.h in Vivado HLS like I saw in some example to stream data throught the AXI DMA. I'm defining my value like this: ...
2
votes
2answers
287 views

FPGA Floating-point to Unsigned 32bits

Regarding something I read in a Xilinx manual saying this: Because floating-point operations use considerable resources relative to integer/fixed point operations, the Vivado HLS tool utilizes ...
-2
votes
2answers
54 views

bit shifting using verilog

Im using verilog language for my program using ISE 14.5, when I give input for example x=0.707 and simulate it in test bench, it gives me wrong output because it consider 0.707 as 1. my question is ...
1
vote
1answer
36 views

How to avoid gated clock on a flip-flop?

I've read that it is a bad practice and I should use the enable signal. Is it also a bad idea to connect a gated, divided clock signal to the enable input?
0
votes
1answer
46 views

Zedboard clock cycles analysis

Based on the example in here, I tried a very similar example (but instead of multiplying two matrices I just multiply all the elements in a matrix by 2.0). However, when comparing the results of ...
1
vote
1answer
61 views

Zedboard 512x512 matrices, % utilization problem

My objective is to read seven 512X512 float matrices from the SD card to the DDR memory (step accomplished already with each matrix occupying around 1Mb), then pass them from DDR to my custom IP block ...
1
vote
1answer
69 views

Obtaining timing score of a implementation run with a PlanAhead TCL script

In a PlanAhead TCL script, I need to know the timing score of a completed implementation run. I have found an old way to do this from 2012. The solution is read directly the PAR report file. In ...
1
vote
1answer
23 views

How to access the selectmap pins (both hardware and software) in Virtex 5 development board?

We are trying to interface a Raspberry Pi with an Virtex 5 dev. board to read the configuration memory. We have decided to use the selectmap protocol and we understand the signals involved and ...
0
votes
0answers
83 views

Cannot program Xilinx FPGA with MicroBlaze project in SDK - missing download.bit file

I have a Xilinx FPGA project that I put together in Vivado 2014.4 (64-bit on Linux). The project uses a MicroBlaze. I've written my MicroBlaze firmware in Xilinx SDK 2015.1. My target hardware is the ...
0
votes
0answers
25 views

How to create several synthesis and implementantion runs in PlanAhead with different generics inputs?

I have set several synthesis runs in a PlanAhead 14.7 project. The main differences between these runs are some generic instantiation set in the "More Options" synthesis parameter by this way: ...
0
votes
0answers
27 views

XC7Z020 JTAG not connecting

In our design I am using a Xilinx XC7Z020 Zynq SoC. In some of the boards JTAG is not connecting, I have checked JTAG cables are working with other boards.
1
vote
1answer
42 views

What could be the usage of material declaration datasheet for Spartan-6 package?

I'm starting to work with FPGAs and CPLDs. like other professional EEs when I bought a Spartan-6 board, started to search in the website of manufacture (that was Xilinx) to find everything about my ...
0
votes
1answer
112 views

VHDL SPI xilinx spartan 3E

I have nearly non previous experience with VHDL and the most of the code here is given to me by the teacher. I'm trying to communicate with a ADXL362 accelerometer using SPI on a Xilinx Sparten 3E. ...
1
vote
1answer
46 views

Why has a LUT6 based SRL only 32 entries but not 64?

Xilinx FPGAs are capable of using LUTs as memory elements. The can be used as ROM, RAM and Shift Register (SRL). New Xilinx devices use 6-input LUTs, which gives 64x1 bit for RAMs/ROMs, but only 32 ...
0
votes
1answer
34 views

Xilinx CORDIC 4.0 Translate parameters question

I'm developing a SysGen model using a CORDIC 4.0 Translate core to pass from rectangular coordinates to polar coordinates. I need understand the Coarse rotation and Compensation scaling options. ...
2
votes
1answer
88 views

std logic conversion into float in vhdl

I am new in this field. I have a problem with conversion of std logic input into real values. I have been using to_float function but it always showed error. When I ...
0
votes
0answers
68 views

How to simulate and initialise Block Memory ROM created using Xilinix CORE generator?

I created the ROM correctly using the CORE generator and the correct .coe file. There is supposed to be instruction words inside the memory (32*256). But the data bus out of the memory is always set ...
-2
votes
1answer
85 views

What are LUT (look up table)? [duplicate]

I am learner in verilog with less knowledge and trying to develop more understanding.I wrote a simple verilog code and synthesize and implement it. I do not have understanding of Look up tables. When ...
1
vote
1answer
80 views

MM2S simple transfer gone wrong

I followed some examples and I already managed to make a big S2MM (stream to memory-mapped) transfer via an AXI DMA. However, now I'm trying the reverse, i.e. to make a simple MM2S transfer to a very ...
4
votes
1answer
129 views

Xilinx bitgen warning

I am getting a warning in bitgen like: This design is using one or more 9k block RAMs(RAMB8BWER). 9k block RAM data, both user defined and default requires a special bit format. Is it a ...
1
vote
2answers
85 views

How to solve routing issues in Artix7?

I am working with Artix 7 (xc7a15tftg256). When the time of Run Implementation,shows the following error message: [Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub ...
3
votes
1answer
47 views

FPGA utilization augmentation in a System Generator core when updating from ISE 13.2 to ISE 14.7

I have a huge system generator core originally developed with 13.2 version. Actually we are updating some projects to the latest version of ISE, the 14.7. In the final step we consolidate the project ...