A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices).

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22 views

Discrepancy in output of post PAR simulation and bit file output

I am using Xilinx ISE to generate a bit file. I verified the functionality by post synthesis as well as post Place and route simulation . But when same bit file was loaded in FPGA there was a zero ...
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2answers
56 views

Dynamically Configure FPGA From Host Program

I was wondering if anyone knows an efficient way to program the FPGA(PL) for a Xilinx Zynq-7 series or related devices,from a host C program (not on the SoC, but from the host PC). Is there an Xilinx ...
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0answers
46 views

VERILOG CODING FOR CHARACTER TO DECIMAL CONVERSION REGARDING [closed]

Can anyone post the verilog coding to convert the LCD CHARACTER to decimal numbers? Because I want to display the decimal value in LCD SPARTAN-3AN to 16*2 (1602zfa) LCD device.
1
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1answer
59 views

Why Linux doesn't get booted automatically only If I changed the BOOT.bin not the zImage, while in the first case it gets automatically booted

I have zynq board ( not the zedboard), it doesn't have all the peripherals of zedboard. I am facing some problem while booting the linux on zynq with my new BOOT.bin. When I used to put the sdcard in ...
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0answers
30 views

Running a program from SD card - Zynq 0720

I've been trying to test a simple hello world program on the Zynq 0720 with a TE0701-03 carrier board. I have followed tutorials online on how to do this but simply, I have created a boot image for ...
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0answers
31 views

Xilinx SDK - MMU Section Translation Fault Issue

I am trying to run the base programming hello world for the TE0720 with Zynq xc7020. The link to the tutorial is here. After following all of the instructions and proceeding without any errors, I try ...
-3
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1answer
58 views

Max output current per I/O pins from Basys2 (SPARTAN 3E) board [closed]

I am trying to drive IR leds out of spartan 3E fpga on xilinx's BASYS2 board. I will be using external current amplifier to drive the IR lEDs with control singal from the FPGA. I need to know the max ...
0
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1answer
55 views

Tutorials on embedded programing using Zynq 7020 with ARM processor

Just as the question states. I have been having trouble being able to just test out the programming side of the ARM processor on the TE0720 board. I have been searching online for how to setup the ...
0
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1answer
65 views

Problem with Xilinx SDK - Failed to Scan JTAG Chain

I am having an issue with running a simple Hello World program on the Trenz TE0720-01 board with a Zync 7020 FPGA. I have been following the tutorial to setup and run the Hello World program given ...
0
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1answer
57 views

Spartan 3AN FPGA DCM

While I use the internal clock for DCM clkin input I am getting clk0 as perfect frequency of output same as internal clock but not in remaining o/p pins. I changed from previous coding like this and ...
1
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1answer
82 views

Retrieving samples from an FPGA using Ethernet

I have a Spartan 3 FPGA for implementing a specific kind of digital modulation. I read the output signal by UART and RS232 but the rate is too slow for following high frequency signals. It was ...
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2answers
96 views

Help needed with SPARTAN-3AN FPGA frequency doubler

Here I attached the routed nets for this below verilog HDL program with DCM instantiate module. while I am implementing in XC3S50AN FPGA board using using ISE12.3 Design suite clk2x & locked ...
2
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2answers
50 views

Constraining a 7 segment display in VHDL

Right now I'm just trying to configure a single digit 7 segment display, and I'm pretty stuck. All of the resources I can find say to use a 7 bit logic vector and just stop there. So I understand ...
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0answers
37 views

Integrating third-party IP core using Xilinx command line tools

I am trying to integrate a third-party IP core, which is given in form of an .ngc netlist file and a corresponding .vhd file with only the entity declaration, into my design. The IP core was ...
1
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1answer
55 views

How to increase QSPI flash clock frequncy in Zynq ZC702

I am working on Zynq ZC702 board. The board has a QSPI flash. I want to increase the clock frequency of QSPI, so that I can read/write at a much faster rate. The closest I found is this : ...
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1answer
53 views

Any good suggestions for Basys2 optional oscillator 50 MHz or 100 MHz? [closed]

I want to get the optional stable oscillator for the Basys-2 but don't know which would be the best choice for 50 MHz and 100 MHz? Has anyone bought and used any? If so, what is the part number?
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44 views

Xilinx Spartan3-E FPGA input impedance and input leakage current for the GPIO pins

I am trying to use one of SPARTAN3-E FPGA GPIO pin as an input to ADC. I want to know the input impedance and the leakage current for GPIO? Should I just connect my circuit's Vout to GPIO pin or ...
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2answers
93 views

Spartan 3AN (XC3S50AN) memory [closed]

Presently we are doing some automation operation using microcontrollers but I wish to change the technology to CPLD/FPGA. So, I wrote a Verilog program in XILINX (XC9572XL) but it has 72 micro-cells ...
2
votes
2answers
128 views

Using BRAM instead of SRAM in Virtex-5 FPGA

I am working on a project where we are capturing signals from an ADC using a Virtex-5 FPGA and the samples are being stored on a 128K x 256 SRAM from where the data samples are acquired by a PC. I ...
2
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2answers
103 views

Using the PS/2 port of the Papilio One FPGA from VHDL

I'm trying to receive data from a keyboard via the PS/2 port on the Papilio One Arcade Megawing. Eventually I'll want to implement this from scratch, but I thought I'd get some public code working ...
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1answer
59 views

Problem using FSL with microblaze

I want to pass some data from my verilog to my microblaze core in ISE 14.7. I was doing some research and it seemed like the FSL was the easiest way to go about this. What I did was create a ...
2
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1answer
93 views

Xilinx FPGA Input data timing constraint

I'm using Xilinx Spartan 6 Automotive FPGA. My FPGA design has a SPI interface to a external peripheral. From FPGA to the peripheral, I have these SPI related signals: spi clk spi data (mosi) - ...
0
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1answer
77 views

What is the use of OFFSET IN/OUT constraint for FPGA design when using register in IOB?

The following is asked in the context of Xilinx FPGAs (my experience), but may also apply to similar technologies offered by other vendors. Background: When writing constraints for FPGA I/O, there ...
1
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1answer
112 views

Online FPGA/HDL synthesizer

I recall seeing a web-based HDL synthesizer a couple years ago, but I can't find it anymore. I believe it was just a frontend that ran the vendors' synthesis tools on the server. Does this sound ...
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43 views

ppc405 communication with custom ip ml403

I am trying to simulate a chemical reaction in FPGA. My basic FPGA architecure consists of 3 processes: ...
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3answers
119 views

Exact recreation of Xilinx FPGA binaries from source control

I'm software developer in a small shop where there's only been one EE guy responsible for a series of FPGA designs spanning a decade, almost all of which target the Spartan line, specifically the ...
0
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1answer
177 views

Connected to Multiple Drivers Problem Verilog

After I synthesize it, the error occured like this: ...
8
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3answers
244 views

How to identify areas of a FPGA design that use the most resources and area?

I am working on a large FPGA design, and I am very close to the resource limits of the FPGA that I am currently using, the Xilinx LX16 in the CSG225 package. The design is also almost complete, ...
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1answer
114 views

How to map LPC FMC pins to FPGA pins on a Zedboard? [closed]

How to map fpga pins to actual physical pins on the FMC connector on a Zedboard? Of course I have looked into the user's hardware guide and the master constraint file, but all I have found is a list ...
4
votes
1answer
122 views

Is it possible for an FPGA to “partially” configure?

I have a spartan 6 board that I designed and am having some configuration issues. I'm using SPI flash to program the fpga (e.g. I use jtag to write the flash and the flash then writes the fpga). The ...
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2answers
207 views

Project suggestions for Final Year [closed]

I'm a final year engineering student. I'm very keen to learn VHDL and FPGA synthesis. I believe choosing a final year project involving VHDL synthesis will help me a lot to learn more about it. ...
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2answers
96 views

Trouble with expansion connector pins in spartan 3 fpga

I know how to turn on the fpga LEDS using push buttons and switches. I'm still having trouble figuring out how can I receive a signal from the buttons to the expansion connectors. Also, how should I ...
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27 views

How to vary the supply voltage for XS40-005XL board?

I have a lot of XS40-005XL boards (http://www.xess.com/shop/product/xs40-005xl/). I know these boards are really old, but they are still functional. So I decided to do some experiments on them. What I ...
2
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1answer
215 views

Xilinx ISE Prevent Trimming For CPU

I am creating a custom CPU and would like it to be programmable on the fly instead of hard coded in VHDL. The issue I am having is that without initial code for the CPU to run, ISE will trim large ...
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1answer
74 views

why fork- join is not supported in ISE Webpack?

I am using the newest version of Xilinx ISE Webpack(v14.7). every time I try to use fork-join statement ( in Verilog ), I receive this error: ERROR:Xst:850 : Unsupported Fork Statement. Is this ...
1
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1answer
64 views

Specify Xilinx FPGA DSP placement with Vivado

How can I, either in the RTL or in a constraint file, map specific DSP blocks to certain locations? I see that DSPs are labeled by site, with names like DSP48_X5Y30 and I'd like to be able to map a ...
0
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1answer
126 views

Why Differential Standards do not exist in FPGA PlanAhead?

I have never used differential I/Os in FPGA ( XC3S400). I always use PlanAhead for pin planning .When I click on a specific pin, it has all single ended standards but none of the differential ...
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1answer
106 views

What is the fastest I/O planning for FPGA?

There are many timing strategies that can improve FPGA speed ( as Timing constraints , planning the clock regions ,....). One of these strategies is selecting optimal places for I/O pins and ...
9
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1answer
277 views

Can I use differential I/O pins of FPGA as high speed comparator?

High speed comparators are rather expensive and speed is what FPGAs are very good at. On the other hand, FPGAs (in my case: XC3S400) have paired differential pins in each bank that their voltages are ...
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401 views

How to assign a pull-up/down resistor in Verilog for inputs?

As a newbie in FPGA world, I realized that it is possible to set pull-up/down resistors in Verilog but I don't know how. I have written my code that works just fine but when I connect my XC3S400 to ...
3
votes
1answer
152 views

what is BUFGP used for?

I'm trying to do some verilog code for my class and I came around BUFGP. After doing some research I only found that it is a buffer for driving clocks. Can anybody explain this to me. For example I ...
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3answers
484 views

What is the meaning of speed grade marking on Xilinx FPGAs?

According to Xilinx FPGA product datasheets, the numbers on the 5th line as 4C or 5I stand for speed grade and temperature.I have a XC3S400 with 4C speed grade (4= standard speed, 5= High ...
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1answer
84 views

How to vary the supply voltage for Xilinx Virtex-5 FPGA ML501, ML506, and ML510 boards?

I'm trying to do an experiment to see how different supply voltages affect the frequency of ring oscillator and the reliability of SRAM cells. I have access to a couple of Xilinx Virtex-5 boards, ...
2
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2answers
236 views

Why my FPGA programs does not work?

I am very new to FPGA and sorry for this elementary question. I just made a very simple XOR code like this with Webpack ISE to download to XC2S100 ( just for test!) but it does not work. EDITION1: ...
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138 views

ALU using Component and Process

I'm designing simple ALU for my own that use 2 bits for select operations. Suppose that, my operations is as follows: ...
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2answers
133 views

Partial Reconfiguration in FPGAs

I have been doing a project involving partial reconfiguration of a FPGA for some time now. I am having trouble understanding what is meant by terms like 'partial bit file', 'bitstream' etc. How can a ...
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1answer
267 views

How to assign physical pins of FPGA to Xilinx ISE Verilog modules?

Recently I started learning FPGA programming. I have the " Verilog QuickStart book" and downloaded Xilinx ISE Webpack v14 and watched a number of YouTube videos. At this moment I can build my circuits ...
3
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3answers
104 views

Inferring BRAM with unused addresses efficiently

What is a correct way to infer a RAM with some unused higher addresses (using block RAMs)? Using the code below (default values for generics, Xilinx synth and map) I get a RAM sized the same as if ...
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1answer
86 views

IC legs (VCCIO1) Broken Accidentlly of Xilinx XC2c128 CPLD is it working?

This is the image of My Xilinx Ic that leg name VCCIO1 that broken yesterday ......but I found in its datasheet that their is a same pin named VCCIO1 are present at that time I was happy but when I ...
2
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1answer
123 views

Do I have to explicitly connect all pins of the ethernet chip in the FPGA when designing a new controller?

Regarding the Ethernet peripheral of the Spartan 3E FPGA specifically the SMSC LAN83C185 Ethernet chip. The task is to create our own interface between the PLB and the ethernet chip. So far, I've been ...