A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices).
2
votes
3answers
83 views
Fix Conflicting IO Standards
I am using the Basys 2 Spartan-3E FPGA board with Xilinx. I need the pmod i/o to be at 1.8v so I am using LVCMOS18 IOSTANDARD.
You can find all of the IOSTANDARD's available for Spartan-3E in this ...
4
votes
3answers
75 views
FPGA Logic Gate Count
I found an FPGA board that I liked. It uses a Xilinx Spartan 6 LX45. When I went to the datasheet for the Spartan 6 series, it only said that there were 43,661 logic cells. How many gates does that ...
1
vote
1answer
41 views
xilinx schematics to truth table
I have a somewhat complicated Schematics design. Is there a program which could convert my design into truth tables?
If there is no such program, how can I represent the D flip-flops of the following ...
0
votes
2answers
48 views
Non-clock signals routed into the clock tree
In my synthesis report, I see that several signals internal to the microblaze have been routed onto the clock tree.
...
0
votes
1answer
32 views
Downsample vs custom latency register
Is there a difference between downsample block (eg. in matlab) versus a register with custom ...
0
votes
1answer
42 views
For loop does not compile in Matlab mcode using Xilinx block
I have a simple code in xilix type mblock in simulink:
function q = test1( n)
q = 0;
for i = 1:n
q = i;
end;
end
If I run this code naively in matlab ...
0
votes
1answer
69 views
Digilent Basys 2 using TinyOS-nesC
I wonder if it is possible to use the TinyOS-nesC environment to program a Basys2 card? Digilent has developed a driver for this card under Linux but their technical department says that it utilizes ...
-4
votes
0answers
106 views
Ideas for a project combining arduino and FPGA [closed]
I would like some suggestions for my project. I need to implement ARDUINO and FPGA, nothing too complex nothing too easy. Just something Simple! where I can show that I have knowledge of these ...
1
vote
2answers
84 views
Static power of Xilinx FPGA
From the results given by power analyzer, I find that the Xilinx FPGAs always have a high static power consumption no matter what your design is, although it will vary if your design utilize different ...
0
votes
1answer
32 views
Difference between best/worse-case latency
I am doing performance optimization of an inverse 8x8 Type-II DCT transform code using Xilinx Vivado HLS. I have generated the report but am unsure of the difference between the best-case latency and ...
0
votes
1answer
99 views
VHDL: logical block 'dcm' with type 'DCM_BASE' could not be resolved
I keep getting the following error when I go to implement my design in Xilinx ISE:
...
-2
votes
1answer
41 views
Xilinx DDS IP for modulating a carrier
I explored XIlinx IP for DDS, and am able to get 2 different frequencies (samples) based on the input clock. But what I want is to frequency modulate the clock itself.
So basically when I say I ...
1
vote
3answers
55 views
Verilog Netlist format with “\”
After synthesizing my RTL level design into verilog netlist, I find the syntax confusing. Here is what I mean.
RTL compiler gives me:
...
0
votes
1answer
163 views
hold time violation during FPGA post place and route simulation in modelsim
I am designing a simple encryption circuit on Xilinx Virtex-5 FPGA. I have given the timing constraint in the UCF as below:
...
1
vote
1answer
70 views
Interfacing SJA1000 to Spartan6 FPGA
As the title says, I would like to interface an SJA1000 CAN controller to a Xilinx Spartan6 FPGA.
The SJA1000 has a shared 8-bit address&data bus with an address latch signal and either separate ...
0
votes
1answer
42 views
Xilinx Xpower Analyzer: Expected scope definition in VCD
I use a VCD file to evaluate the power of my design. The VCD is generated using the following command in the testbench file.
...
1
vote
2answers
78 views
Post synthesis level simulation xilinx xst
I have written a verilog code and it is working fine at behavioral simulation level. After this I went for synthesizing the design using XST tool in Xilinx ISE 13.2. Running the post simulation level ...
0
votes
1answer
121 views
Problem initializing Xilinx BRAM
A while ago I added a feature to GNU binutils to convert files to verilog mem files, suitable for reading with $readmemh. The output is very close to what you might get with xilinx's data2mem ...
1
vote
2answers
264 views
How to Add the Xilinx Library to Modelsim
I'm trying to simulate an example design of an IP Core, but the version of ModelSim I have installed (Altera Edition/Linux) does not link to the Xilinx library. How can I permanently or temporarily ...
4
votes
2answers
196 views
Using SVN with Xilinx Vivado?
I just stated using Vivado in a new project and would like to put the project files under SVN.
Vivado seems to create all the project files under the project name (say proj1):
...
-3
votes
1answer
146 views
PCB footprint of Xilinx Kintex 7 FPGA [closed]
I am laying out a board with a Xilinx Kintex 7 FPGA (serial number XC7K70TFBG676). The first step is to create a footprint of the FPGA for my layout tool, the Cadence Allegro PCB Editor.
Does Xilinx ...
4
votes
1answer
101 views
How do I calculate the supply current for a zynq 7010 chip?
I have a Zynq 7010 chip, and the current requirements in the datasheet confuse me a lot. Could someone explain how to determine how much current I'll need to supply to each rail?
...
2
votes
2answers
322 views
MUX verilog code
Can anyone explain the difference between the two codes below. Both written in Verilog, Xilinx. If someone can explain how the second one works would much appreciate it.
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2
votes
3answers
148 views
Aldec Active-HDL - No Default Binding
I'm getting some errors when I try to compile my design in Aldec's Active-HDL.
...
2
votes
1answer
51 views
Generating a MSS file at command-line?
Is there a way to generate a mss file from the exported SDK XML file at command-line? At the moment, I still have to open xsdk, generate a new hello world project to create the mss file. But I would ...
1
vote
1answer
392 views
Fixed Point Division in verilog for Spartan 6
I am developing a core on Spartan 6 which needs to do divisions like
1/6,2/4 etc... so the values are always between 0 and 1. As I dont need the precision of floating point I am want to use a fixed ...
0
votes
1answer
56 views
Xilinx: .bit --> .SVF / .ACE
I've generated the bitstream file for my device, which steps should I take to compile the .ACE file, I could flash my device with?
I'm using Xilinx ISE 10.1 with Virtex2 over an VME interface
1
vote
1answer
107 views
Starting FPGA project on Xilinx - trouble with some basics! Coming from Altera background
I'm just looking for a bit of help getting started with Xilinx FPGAs. Specifically, I'm looking for the analogue to Altera's HEX and ...
4
votes
3answers
192 views
Documenting Digital Design - Schematics and Figures
I'm working on a small digital design using a Xilinx picoblaze softcore processor, and I'm finding that producing schematics of acceptable quality to be frustrating and time consuming. I've attempted ...
1
vote
1answer
93 views
What is the minimum current I need to supply to a Spartan-6 pin in order to register a high signal?
Digging around in the spartan-6 DC and switching characteristics guide, I can't find what I'm looking for.
Also no absolute max sync/source current ratings for the user IO pins. Looking at the dev ...
4
votes
1answer
179 views
inout port in VHDL RS232 Module from Digilent
I'm looking at the Digilent RS232 reference component available from http://www.digilentinc.com/Products/Detail.cfm?Prod=S3EBOARD for the Spartan 3E Starter Kit. I began putting together a testbench, ...
8
votes
4answers
527 views
FPGA firmware design: How big is too big?
I have a particularly large signal processing transform that needs to be ported from matlab to VHDL. It definitely requires some kind of resource sharing. A bit of calculation gave me the following:
...
2
votes
1answer
105 views
pBlazSim Picoblaze simulator - Trouble Getting Started
I've been trying to simulate my Picoblaze code with pBlazSim, but I'm having trouble with the lack of documentation. Am I missing something? Could someone point me in the right direction?
Edit - ...
6
votes
4answers
555 views
How fast does a 64-bit multiply or divide execute on an FPGA?
When using a regular FPGA such as Xilinx Spartan 3 or Virtex 5, how many cycles does a double-precision floating-point 64-bit multiplication or division take to execute?
As far as I understand, the ...
2
votes
2answers
137 views
How to generate wait until division is over in verilog?
I am using a division module which has two signals other than inputs
"go" to indicate start of division.
"done" to indicate stop of division.
It is taking approx 300 clock cycles for the division to ...
2
votes
1answer
107 views
Design doesnot work properly when clock net delay is slightly higher in spartan3a fpga
I am running my design on spartan3a 3s700afg484 at 50 mhz.
There is no set up and hold time violations.
There is only one global clock net.
My clock report for two runs are
RUN 1:
Info: [707]: | ...
6
votes
1answer
281 views
3.3V IC <-> 2.5V FPGA IO Bank
I want to connect a 3.3V TFP401 to a 2.5V spartan 6 LX45T FPGA. It looks like each device is tolerant to the other device's voltage:
TFP401:
...
3
votes
2answers
119 views
SDRAM chip selection
I need to buffer 1.5Gb/s of video data through SDRAM, which works out to be 3Gb/s total in and out combined.
This is my thinking so far:
Write/read burst length is set to max (16 clock cycles), and ...
4
votes
3answers
228 views
LUT vs. hard IP based multipliers on Spartan-3 FPGA for constant coefficient multiplication
Before I get to my question, here are the specs for the board and synthesis tool I am using:
Family: Spartan3
Device: XC3S200
Speed: -5
Synthesis Tool: XST
My 4-bit multiplier is in my design's ...
0
votes
1answer
123 views
Why is ISE / XLS is mapping a signal to the global clock GCK0?
I've synthesized a design for a Coolrunner II CPLD. I intend to use the CPLD's internal clock. I have an input named CLK. I look at the fitter report and I see this:
...
4
votes
2answers
311 views
3.2 Gb/s high speed interface over 50m: copper, fiber, other ideas?
I need to run a 3.2 Gb/s interface over 50m. My client is keen on Cat6e. The lower the price, the better. These are my findings so far:
I'm looking at using a Spartan 6 GTP Tranceiver with copper ...
6
votes
2answers
239 views
Why does this Verilog hog down 30 macrocells and hundreds of product terms?
I have a project that's consuming 34 of a Xilinx Coolrunner II's macrocells. I noticed I had an error and tracked it down to this:
...
4
votes
0answers
100 views
Minimal redistributable coregen output for command-line rebuilds
I'm building an SoC with my own soft-core, and I want people to be able to easily rebuild it using Xilinx webpack command-line tools. I'm using coregen's Clock Wizard to create a clock module, but ...
0
votes
1answer
250 views
FT245R transmit buffer filling up, repeated IOCTL_SERIAL_WAIT_ON_MASK messages
I'm stress testing the FT245R chip using a basic CPLD to negotiate reading and writing with the chip and PC as the USB host.
Basically I have programmed up the CPLD to read in 8 bit words from the ...
3
votes
1answer
318 views
Multiplexing an I2C bus between two masters on a Xilinx FPGA
I have a single external I2C bus (SDA and SCL pins). This is currently controlled by a third-party IP core which provided "implicit" inout ports in the MPD, specifically:
...
8
votes
3answers
260 views
Compare implementing a simple automation design on a MCU vs an FPGA/CPLD
I have been working with MCU's since the 90's, and I've recently ventured into the FPGA scene with the Spartan6 series chips from Xilinx. Assuming a simple factory automation design with sensors and ...
7
votes
1answer
487 views
Simulating a simple test bench with a synthesized ROM core
I'm completely new to the world of FPGA's and thought I'd start with a very simple project: a 4-bit 7-segment decoder. The first version I wrote purely in VHDL (it's basically a single combinatorial ...
0
votes
2answers
302 views
Inferring BUFGMUX in Xilinx FPGAs for Clock Multiplexing
I have a VHDL memory core which requires me to multiplex between two clocks. The Write clock operates at 200 Mhz and Read clock operates at 100 Mhz. I think this can be done using ...
1
vote
1answer
99 views
Why does changing an 'add' to a logical or devour 7 CPLD macrocells?
I have a design that's synthesizing to about 50 macrocells.
I have this section of code:
...
3
votes
1answer
330 views
Multi-Port RAM (1 write port, many read ports)
I have a project where I may need a 128 KB lookup RAM. I have 1 write port which writes the lookup values at the start of the application. I will have more than 2 read ports (I am assuming 4). I do ...
