A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices).

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Driving a differential signal from FPGA

Disclaimer: I am not sure if this is the right place to ask this. I am trying to create an sdram controller for the numato mimas v2 fpga. The board contains an LPDDR module (either the Micron ...
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25 views

18bit Serdes - Xilinx Spartan6

In a project with FPGA stereo vision I use two MT9V032 cameras. The cameras are connected as in the application example in the data sheet. In stereo output mode the data length is 18bits long. ...
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1answer
21 views

Can't Find Further Documentation on Spartan3E IO

I am trying to find some further detail on the IO resources for a Spartan 3E. Using ISE, when I open PlanAhead to look at the floor plan I see a lot of names, organization and acronyms that I do not ...
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6 views

What is the condition s_axi_bvalid asserted high within AXI4LITE bus?

I'd like to control about xilinx fifo generator in vivado. Firstly I've make one master and connect to fifo generator with axi4lite protocol. But the problem is that s_axi_bvalid signal is not ...
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27 views

How do I tell when this Xilinx AXI BRAM Controller is reading data?

I am using a XILINX IP AXI BRAM Controller (document here) which is connected to another XILINX IP BRAM memory unit. The AXI Controller is used to connect the BRAM memory to PCIe. I want to replace ...
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11 views

Xilinx Generator_FIFO does not work

I'm trying to implement xilinx fifo_generator in vivado as AXI4LITE interface. But problem is that the fifo does not work. I've already read the user guide but it does not help me, also simulation ...
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1answer
10 views

VC707 SMA input voltage

I am trying to integrate with Raspberry Pi (RPI) and VC707 (FPGA board from Xilinx). VC707 has two GPIO SMA ports but it's input voltage is 1.8V according to manual. As output voltage of RPI is 3....
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42 views

How to output any intermediate signals in VHDL?

I have the following code, which describes a simple element with two registers and an adder. There are also some control signals, which are basically "load enables" for those registers. Each register ...
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23 views

Xilinx FPGA Editor + Line Names?

I am playing around with the FPGA editor and looking at a Spartan3E. When I click the different lines the console displays what I guess is a name for each individual line: What exactly do these mean? ...
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58 views

FPGA Performance of Routing

I am trying to learn more about the performance of different routings in my design using Xilinx ISE. I've figured out how to move logic around by changing which CLB/Slice holds which piece of using ...
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335 views

Is this BRAM being fully utilized if I use a different data width?

Background I am using a Xilinx FPGA from the Kintek-7 family. The documentation for the memory resources can be found here. Here are some important excerpts from the document (referencing pages 11 ...
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51 views

CLOSED-Custom IP register address location

In my current IP, I am trying to transmit the data(data1 and data2,each 32bit) from the PS to the custom IP.At first, I wrote the data1 to the base address 0x43C00000 and read at slv_reg0 and it is ...
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1answer
43 views

How to map custom IP to the output pin on FPGA

I have a custom IP created with 2 output pin (en1_out and dir1_out) May I know how to map these two pin to the PMod pin on FPGA (pin Y11 and pin AA11)? I have tried to open the elaborate design and ...
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73 views

How do I build an interface between MicroBlaze and the FTDI FT600

I would like to implement USB 3.0 communication (instead of UART) with a custom FPGA board using Microblaze. I have already testing basic communication functionality in verilog, writing and reading ...
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1answer
34 views

Xilinx XPS : On what bases the AXI master changes AWSIZE/ARSIZE…?

I have built my system with AXI interface using AXI4 From XILINX PLATFORM STUDIO(XPS). I used 32 bit data and address buses.I am facing problem with respect to xSIZE. In firmware(SYSTEM C), I have 8 ...
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26 views

Run XST from Windows Command Line

I am attempting to build a C++ program that performs all of the necessary steps generate a bit file using the ISE (14.7) tool chain. I generate the Command line Log File for my project and try to run ...
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11 views

Realtime In-system debugging for CoolRunner-II CPLD?

I am pretty new to the CPLD, and I started out with Xilinx's CoolRunner-II series with third-party demonstration board. So far, I learned how to program using verilogs and make the system work. Is ...
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1answer
31 views

How to generate .xst file from command line + Xilinx-ISE

I am trying to learn how to generate bit files from command line. Is there a way to generate the .xst script file from command line tools? I can only find mention of it being something that the GUI ...
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39 views

Connecting a Virtex 6 FPGA to a high speed DAC

I'm a university student who's relatively new to the FPGA so please forgive me if something's missing here. I've recently started worked with the Xilinx ML605 FPGA board and have tested it with some ...
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26 views

How to solve the unable to detect any supported xilinx cable in idenify?

Now I'm trying to run Identify Debugger, My Identify debugger is old version, 3.0. The problem is that I've got some error message as below. Meanwhile, I can use IMPACK as well. the IMPACK is work ...
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1answer
65 views

Signal is connected to following multiple drivers

This is the top module combining the Circular Shift Register, Multiplexer and Adder. ...
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2answers
40 views

VHDL - displaying 4 digits on 7-segment display

I wrote a vhdl code, that would display 4 digits on cpld 7-segment displays. I used a state machine to select the display, and with ... select instruction to select a set of bits given to the current ...
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60 views

How do I send continuous data over UART (Xilinx Zynq 7000)?

I want to interface with MATLAB to read out some sensor data which I acquire on my Xilinx Zynq SoC. For that I want to use UART which will send data during idle. I wrote this really simple routine ...
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1answer
37 views

I want to supply under 1.1V to xilinx virtex5 Vccint how to make the volatage? [closed]

I'd like to supply under 1.1v to xilinx Virtex5 Vccint. The input voltage is 5. But I can't find any reference how to make like under 1.1v. Does anyone know how to make it, please give to me any hint....
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28 views

Spartan-6 FPGA Input voltage

We are using the Spartan-6 FPGA from Xilinx. VCCO banks of the FPGA are running at 1.8V. We a have MIPI IC that outputs serial data, but at 2.7V. Looking at the Specs for the FPGA, it seems to be ...
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52 views

Xilinx FPGA editor + Relate to Design

I am trying to learn a little more in depth about Xilinx place and route and how everything works. I have made a very simple schematic design and am looking at the result on the board using the FPGA ...
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42 views

Interfacing a TM4C123 with a Basys3?

I'm trying to build a shell-based real-time OS on a TM4C123 LAUNCHPAD. I already have the kernel and file system done, and I was hoping to add interactivity to this implementation. I was hoping to ...
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1answer
18 views

Is there support XC5VLX110 list in ISE Project setting?

I'm just trying to setup ISE envirmonent. But There's not XC5VLX110 in Device list at the Project Settings in ISE as below picture. What should I do for solving in this situation?
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123 views

What the FPGA dev board to choose: Xilinx or Altera? [closed]

I'm very new to programmable logic world and have never worked with any HDL languages, but I certainly want to get started with FPGA. At the moment the goal is to develop/simulate simple 8bit CPU and ...
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1answer
88 views

VHDL - 10% Duty Cycle

I need to generate 500Hz from 50MHz clock frequency. I already got it. My problem here is how should the code to be adjusted if I want to change the duty cycle to 10%? Thank you. ...
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50 views

Vivado: Block Design sub module

I'm working on a Video processing project with Vivado 2015.2 on a Zynq device. My block design starts to get huge and hard to read. As I have several times the same pipline implemented, I would like ...
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60 views

An overall PWM system by using FPGA [closed]

I need to combine this 3 coding to form one whole PWM system by using FPGA. I tried it, there is no error, but the process is not synthesizable. Please help me. Thank you. This is code for ...
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57 views

lwIP initialization hangs when configuring TEMAC

I am working on a my master thesis, designing an FPGA solution, and have run into a very resilient problem. I will try to provide as much information as possible, in the hopes that someone might have ...
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1answer
82 views

Moving a large dataset from the PS to PL on a zynq device?

I am at the moment trying to interface with DRAM on my Xilinx Zynq device such that I am capable of moving a large amount of data from the processing system (PS) side to the programmable logic (PL). ...
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20 views

Is there any way to generate an MASTER UCF of xilinx ISE from Planahead?

I'm not sure but is there any way to generate master UCF file from PlanAhead? I'm trying to find a way to generate methods but I couldn't it. So would you please let me know how to generate an ...
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2answers
88 views

How to get a default UCF file of Xilinx Virtex-5 XC5VLX110?

How to get a default UCF file of the Xilinx Virtex-5 XC5VLX110? It doesn't seem to be anyhere. If I have to make it by myself, would you let me know how to ...
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23 views

IP Xilinx System Generator and XPS

Hi guys i have a problem with Xilinx XPS. I'm going to explain this. I have a peripheral AXI4Lite written all in VHDL to talk with an ADC, and into its structural I have to insert a design done with ...
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48 views

Possible to Use a Papilio One 250k Logic Analyzer as an FPGA?

I've just bought a Papilio One 250k logic analyzer, which seems to be based on an FPGA dev board of (nearly) the same name. Can/should I try to use this as an FPGA board? Could I easily flash my own ...
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290 views

Do I need to reset my FPGA design after startup?

I usually initialize state registers of my FSMs by specifying an initial value in my VHDL code, so that, I do not require a reset pulse after startup of the configured FPGA. The following example ...
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1answer
98 views

How to create .VCD file or Simulation activity file of verilog code?

I have Verilog's code. It is simulated correctly and synthesize too. I wanted to write.VCD(value change dumped) file. I got from internet few command to generate VCD file as given below: ...
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1answer
136 views

Generating video with ZYNQ, using IP block design?

I am trying to implement a video streamer on Digilent ZYBO board that has Xilinx ZYNQ 7010. By the way, reason of this thing is to test the quality of an encoder board. What I want is to: Generate a ...
3
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1answer
55 views

Xilinx ISE warns that a signal is trimmed since it has a constant value of 0, but the signal is used within my code

I have created the following VHDL module, which is used as an up/down counter. ...
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1answer
44 views

TX/RX pins on Xilinx Zynq

I have been using a Spartan 6 where the TX/RX pins are multiplexed with the IO pins, I can't find any dedicated TX/RX pins on the Xilinx Zynq Soc, is it a Xilinx thing to multiplex TX/RX with IO pins?...
2
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58 views

How to specify a minimum clock to output time in output timing constrain?

In a design, an external clock pin triggers a flip-flop, where the output goes to an external data pin. Using Xilinx ISE, how can I specify a timing constrain, so the output should be held for some ...
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2answers
70 views

How to generate IP cores with access to hardware in vivado

I am looking for some guide on how create an IP-Core in Vivado which make integrate the hardware. I want to create a IP-Core which should act as an driver for VGA port. The problem is how to create it ...
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181 views

Dual port RAM on Altera and Xilinx FPGA

I have always managed to synthesis a 256 x 32 bits dual-port RAM (not true dual port RAM) in Xilinx ISE with just 1 x 18K BRAM. The example code from here was used: ...
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121 views

FPGA Frequency Divider

I need to design frequency divider from 50MHz to 200Hz using FPGA. I'm using Xilinx and the language that I used is VHDL language. I got stuck because I can't get the output. So, anyone can help me? ...
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72 views

Failure: (vsim-3808) Incompatible modes for port

I am attempting use modelsim to simulate a peak detector and am having trouble with the simulation of the handshaking protocol between two modules: dataGen and dataConsume. I am certain that the code ...
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1answer
115 views

Measuring power consumption of VHDL code

I am trying to find power consumption of my vhdl code.I am going to use the power estimator in xilinx 9.2.Do the power analysis results vary in xilinx 9.2 and xilinx 14.7?? Also will xilinx provide ...
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2answers
132 views

Simple binary adder works only partially

LATER EDIT: 1. I've also investigated visually the Kintex7 device after implementation (i.e. interconnections, etc.) and everything looks OK - no connections that would indicate things would not be ...