A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices).

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This design does not fit into the number of slices available in this device

Below is the device utilization summary for the design(Zynq 7010) and the use of Slice LUTs exceeds the availabile number. Previously it was 82% and now it exceeds after adding a block of checksum ...
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28 views

Axi DMA correct parameters

I'm making my design with Vivado HLs and Vivado and I'm doing some somewhat big transfers between DDR and my custom IP block and vice-versa. Each transfer from DDR to custom IP is of 256x256x4=262144 ...
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1answer
17 views

Unable to open XPS from PlanAhead(Xilinx ISE 14.3)

I am unable to open Xilinx Platform Studio(XPS) from PlanAhead. It shows me following error messages: I have not opened multiple sessions of it. I have also removed the write protection for that ...
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1answer
45 views

PAR taking too long - Xilinx ISE

I am trying to compile a project and it takes a very long time to route. - ISE 14.3 In my main module, I am using a package where I have declared an array of constants. These constants use functions ...
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15 views

Coolrunner2 GSR Global Set/Reset

So the Coolrunner2 CPLDs have a feature called GSR or "Global Set/Reset". In the documentations I found lots of references to it but no chapter that tells me how the GSR exactly works and more ...
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22 views
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26 views

Change PL clock

I'm designing my project in Vivado and I had a WNS (Worst negative Slack) of -2.67 ns (my PL clock was 200Mhz). I had some problems when running my design since the results where good sometimes and ...
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2answers
65 views

How to analyse timing report for Xilinx FPGA

I'm trying to learn FPGA programming, my test project is a 5 stage pipelined MIPS CPU, which works. Up until now I have been optimising for area utilisation, however this has caused a very slow clock ...
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2answers
43 views

Component Not Found VHDL XILINX ISE

i know this might be a very simple question . i have to simulate some delays for various adders in ISE Suite . ( i'm a little familiar with vhdl concepts but ISE Environment , not at all ! ) this ...
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26 views

Axi DMA asynchronous

I was reading the Logicore of the AXI DMA and I saw this: Setting Enable Asynchronous Clocks enables asynchronous mode and creates four clock domains. This allows high-performance users to run the ...
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26 views

Design timing Summary - Xilinx

(Working with a Zedboard) I made a design in Vivado HLS, selecting a period of 200Mhz. In the synthesis report I can see that the estimated clock is 5.24ns with an uncertainty of 0.63. I decided to ...
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27 views

PlanAhead 14.7 multiple runs issues

My project in PAhead 14.7 have 6 different synthesis run and 6 implementation runs. Each implementation run have her own parent synthesis run. The differences between synthesis runs are some generic ...
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35 views

Axi DMA maximum velocity and DCache clarification

This is a 2 question in one thread. I'm basing my model on the matrix multiplication example. First set of questions: After some optimizations I have now a MM2S velocity of 1009 Mbytes/s and a S2MM ...
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27 views

HDLcompiler warning189

I am new to xilinx and verilog and am trying some basic stuff when I got this error. I know we can define input and output bus sizes using parameters like parameter width = 32; output [width-1:0] ...
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18 views

MatrixMult modification - Xilinx

I was following the example of the matrix multiplications present in here. As my objective is different since I don't need to multiply matrices but only all the elements of the entrance matrix by ...
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21 views

Xilinx ap_axiu parameters

I'm using ap_axiu from ap_axi_sdata.h in Vivado HLS like I saw in some example to stream data throught the AXI DMA. I'm defining my value like this: ...
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2answers
277 views

FPGA Floating-point to Unsigned 32bits

Regarding something I read in a Xilinx manual saying this: Because floating-point operations use considerable resources relative to integer/fixed point operations, the Vivado HLS tool utilizes ...
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2answers
47 views

bit shifting using verilog

Im using verilog language for my program using ISE 14.5, when I give input for example x=0.707 and simulate it in test bench, it gives me wrong output because it consider 0.707 as 1. my question is ...
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1answer
35 views

How to avoid gated clock on a flip-flop?

I've read that it is a bad practice and I should use the enable signal. Is it also a bad idea to connect a gated, divided clock signal to the enable input?
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38 views

Zedboard clock cycles analysis

Based on the example in here, I tried a very similar example (but instead of multiplying two matrices I just multiply all the elements in a matrix by 2.0). However, when comparing the results of ...
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1answer
52 views

Zedboard 512x512 matrices, % utilization problem

My objective is to read seven 512X512 float matrices from the SD card to the DDR memory (step accomplished already with each matrix occupying around 1Mb), then pass them from DDR to my custom IP block ...
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1answer
35 views

Obtaining timing score of a implementation run with a PlanAhead TCL script

In a PlanAhead TCL script, I need to know the timing score of a completed implementation run. I have found an old way to do this from 2012. The solution is read directly the PAR report file. In ...
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1answer
22 views

How to access the selectmap pins (both hardware and software) in Virtex 5 development board?

We are trying to interface a Raspberry Pi with an Virtex 5 dev. board to read the configuration memory. We have decided to use the selectmap protocol and we understand the signals involved and ...
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54 views

Cannot program Xilinx FPGA with MicroBlaze project in SDK - missing download.bit file

I have a Xilinx FPGA project that I put together in Vivado 2014.4 (64-bit on Linux). The project uses a MicroBlaze. I've written my MicroBlaze firmware in Xilinx SDK 2015.1. My target hardware is the ...
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24 views

How to create several synthesis and implementantion runs in PlanAhead with different generics inputs?

I have set several synthesis runs in a PlanAhead 14.7 project. The main differences between these runs are some generic instantiation set in the "More Options" synthesis parameter by this way: ...
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25 views

XC7Z020 JTAG not connecting

In our design I am using a Xilinx XC7Z020 Zynq SoC. In some of the boards JTAG is not connecting, I have checked JTAG cables are working with other boards.
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1answer
41 views

What could be the usage of material declaration datasheet for Spartan-6 package?

I'm starting to work with FPGAs and CPLDs. like other professional EEs when I bought a Spartan-6 board, started to search in the website of manufacture (that was Xilinx) to find everything about my ...
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1answer
78 views

VHDL SPI xilinx spartan 3E

I have nearly non previous experience with VHDL and the most of the code here is given to me by the teacher. I'm trying to communicate with a ADXL362 accelerometer using SPI on a Xilinx Sparten 3E. ...
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1answer
38 views

Why has a LUT6 based SRL only 32 entries but not 64?

Xilinx FPGAs are capable of using LUTs as memory elements. The can be used as ROM, RAM and Shift Register (SRL). New Xilinx devices use 6-input LUTs, which gives 64x1 bit for RAMs/ROMs, but only 32 ...
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34 views

Xilinx CORDIC 4.0 Translate parameters question

I'm developing a SysGen model using a CORDIC 4.0 Translate core to pass from rectangular coordinates to polar coordinates. I need understand the Coarse rotation and Compensation scaling options. ...
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1answer
69 views

std logic conversion into float in vhdl

I am new in this field. I have a problem with conversion of std logic input into real values. I have been using to_float function but it always showed error. When I ...
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60 views

How to simulate and initialise Block Memory ROM created using Xilinix CORE generator?

I created the ROM correctly using the CORE generator and the correct .coe file. There is supposed to be instruction words inside the memory (32*256). But the data bus out of the memory is always set ...
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1answer
63 views

What are LUT (look up table)? [duplicate]

I am learner in verilog with less knowledge and trying to develop more understanding.I wrote a simple verilog code and synthesize and implement it. I do not have understanding of Look up tables. When ...
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63 views

MM2S simple transfer gone wrong

I followed some examples and I already managed to make a big S2MM (stream to memory-mapped) transfer via an AXI DMA. However, now I'm trying the reverse, i.e. to make a simple MM2S transfer to a very ...
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1answer
120 views

Xilinx bitgen warning

I am getting a warning in bitgen like: This design is using one or more 9k block RAMs(RAMB8BWER). 9k block RAM data, both user defined and default requires a special bit format. Is it a ...
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2answers
64 views

How to solve routing issues in Artix7?

I am working with Artix 7 (xc7a15tftg256). When the time of Run Implementation,shows the following error message: [Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub ...
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1answer
45 views

FPGA utilization augmentation in a System Generator core when updating from ISE 13.2 to ISE 14.7

I have a huge system generator core originally developed with 13.2 version. Actually we are updating some projects to the latest version of ISE, the 14.7. In the final step we consolidate the project ...
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3answers
112 views

PCI-Express and FPGA Development Boards

I'm interested in using some high-performance FPGA development boards, but it seems like most of the high-end, modern options from both Xilinx (Digilent) and Altera (Terasic) seem to be PCIe-based ...
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2answers
53 views

How to multiply base system clock using .xdc constraints in Vivado

This question may be ridiculously rudimentary but I have been going through Xilinx's available guides and videos tearing my hair out... my problem is simply this: I want to use the base 100Mhz clock ...
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3answers
82 views

Datasheet hunting -

I'm having difficulty trying to figure out voltage outputs for FPGAs. Let's use the Xilinx XC3S2000 FG900 as an example, and say I'm trying to figure out the voltage for pin T22. I do a search for the ...
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68 views

S_axilite port, how to deal with AXI GPIO

I have a block made in Vivado HLS that receives 3 parameters: 1-Map_in which is a matrix of values to be normalized. My objective is to connect it to DDR via AXI DMA 2-Map_out which is a matrix of ...
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1answer
37 views

Check the value of FSL_M_Control in the MicroBlaze

I wrote a hardware accelerator which communicates with a MicroBlaze over FSL. In the Microblaze C code I would like to use putfsl() in a loop until the hardware ...
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84 views

Add DDR data into Vivado model - Zedboard

I initially had a doubt on how to read .txt matrices from an SD card to the Zedboard DDR memories:Read .txt (matrices) from SD to DDR - Zedboard Well, I'm now able to read the five 1Mbyte maps into ...
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1answer
55 views

Understanding Address Map

Please refer to this image of page 113 of this manual I'm not understanding this table. From what I can tell, I have from 0010_0000 to 3FFF_FFF of DDR memory, which is 1 072 693 247 bytes and ...
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39 views

Where to get started? Digital Lockin Amplifier

Being an experienced embedded programmer/designer (AVR, PIC, ARM), I want to design a digital lockin amplifier. I know that I need a DSP for this and I see many people using the Xilinx Spartan6 ...
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81 views

Read .txt (matrices) from SD to DDR - Zedboard

I'm converting a C algorithm into VHDL with Vivado HLS, and after exporting the RTL into Vivado and completing the design I'm using Xilinx SDK to right in the ARM9 PS. Problem: The algorithm is meant ...
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1answer
65 views

Best way to pass floating-point numbers to DDR - Zedboard

I have a Zedboard and I made a PL block in Vivado HLS that is going to return milions of floats to the DDR via an AXI DMA block, and those results are then going to be read by the PS from the memory. ...
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19 views

Extract dynamic power Xilinx XPower

As i see in text books, Power trace of a design can be extracted using Xilinx Design Suit which show dynamic power vs. time. However trying to use Xilinx XPower and Power Estimator, it only shows ...
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1answer
43 views

Can't Search for specific value at RAM - verilog

My module has search for specific value at RAM and then return its location address. when I wrote a test bench, I see that the module didn't work correctly! always the output value is "don't care". ...
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1answer
112 views

Which is the best way to version control Xilinx PlanAhead projects?

Actually I'm migrating some mature projects from Xilinx ISE to Xilinx PlanAhead. I need to take advantage of TCL scripting and partitioning of PlanAhead. This ISE projects are under version control ...