A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices).

learn more… | top users | synonyms

0
votes
2answers
26 views

How to give clock on xilinx spartan 6?

I am trying to run a counter on Digilent Atlys Spartan 6 xc6slx45 development kit, which changes counts on clock edge. I am new user to Verilog, so I don't know how to give clock to my program from ...
0
votes
2answers
70 views

PC serial communication with FPGA

I am designing a simple 16 bit adder circuit in Digilent's Xilinx Spartan 6 FPGA. The Verilog design accepts two 16 bit inputs A and B and returns the 16 bit sum C = A+B. I am ignoring carry in and ...
0
votes
0answers
41 views

Trouble configuring Virtex-5 FPGA using JTAG

I'm trying to configure a Virtex-5 FPGA on a custom board and I'm using Xilinx iMPACT in order to program the FPGA using a JTAG interface. But iMPACT has trouble detecting the FPGA and gives an error ...
0
votes
1answer
38 views

Why two Xilinx scripts with different bitgen options yield correct and incorrect behaviors?

I am really puzzled by a FPGA synthesis problem on Xilinx ISE. Precisely, it took me a long hour to discover why a same RTL design (set of VHDL files) works like a charm on a board using a synthesis ...
0
votes
2answers
75 views

Uploading C program to the ARM core for execution through ethernet!

I want to write a c code on my local PC and upload it to ARM core on Zed-board for execution. I know we can do it using JTAG, but for obvious reason I want to use Ethernet interface. I will be glad ...
0
votes
0answers
73 views

How does the read & write FIFO of the Xilinx work?

I'm having a problem understanding the mechanisms of the read FIFO and write FIFO of Xilinx IP core generator (in the Xilinx platform studio software). I don't understand how the read FIFO sends data ...
0
votes
0answers
70 views

Vivado optimizing away my pins

I'm fighting Vivado over what seems like a fairly stupid issue to me. I wrote some Verilog code in ISE (and simulated it). I generated a bitstream in ISE and downloaded it onto the board via impact, ...
1
vote
0answers
158 views

Bidirectional FPGA implementations (parallel ADC)

New FPGA convert here. I am trying to interface with a parallel ADC as part of a data acquisition project. The pins on the ADC are used for both input and output (not simultaneously). Therefore, I ...
1
vote
0answers
26 views

How to calculate average delay time of circuit having several possible transition states

Is it possible to calculate average delay for all possible states directly without calculating them individually using Xilinx or with Cadence.
1
vote
0answers
71 views

Trying not to be subjective, but is there an affordable development board for CPLD design? [closed]

Yes, I've Googled and I realize this could be considered "subjective" and not "fact based". But, this is the only EE community I know of that isn't centered around a brand (i.e., biased). I'm ...
1
vote
1answer
65 views

Xilinx Video Timing Controller freezes processor

I'm trying to acquire video from an image sensor using a ZedBoard with Vivado 2014.2 and I used an existing (working) video passthrough project of mine and simply added in a debayer (color filter ...
4
votes
1answer
94 views

Configuring a 7-Series GTXE2 transceiver for Serial-ATA (Gen1/2/3)

Hello this will be an experts questions :) You should be familiar with the following topics Xilinx Multi-Gigabit-Transceivers (MGTs), especially the 7-Series GTX/GTH transceivers (GTXE2_CHANNEL) ...
1
vote
1answer
64 views

In VHDL what is a data operator type “variable” when it is translated to circuit? [duplicate]

VHDL code is finally converted into hardware equivalent when it is synthesized. What happens to data operator type "variable" when it is synthesized?
2
votes
1answer
37 views

Optimum aspect ratio for storing data in Block RAMs

I am working on Xilinx virtex 4 FPGA. I want to store some filter coefficients in Block RAMs. Specifically, I have many sets of filter, each set having 64 coefficient, each coefficient is of 18 bits. ...
3
votes
1answer
264 views

having distorted image in VGA with FPGA board

I'm using spartan 3E-100 CP132 fpga board to display a basic plus image on a monitor. I have tried using 800x600 72 hz and 640x480 60 Hz but I always get a distorted vertical lines. Is it because the ...
1
vote
4answers
215 views

High speed memory interface between 2 FPGAs (Virtex 6)

I have a board with 2 Virtex 6 FPGAs, which are connected to each other through 64 parallel IO lines that can operate up to 400 MHz. One FPGA, let's call it B, also has 2 GB of DDR3 memory connected ...
0
votes
0answers
84 views

Routing errors when trying to implement PLL onto Spartan-6 FPGA board

I am attempting to synthesize and implement the reference design that is linked to in the 'Reference Design Additional Information' section of the following document. I get the following error ...
1
vote
1answer
121 views

How to simulate PCIe to debug my FPGA endpoint

I'm working on an FPGA controller connected through PCIe. The only way I can debug the hardware is using chipscope. So I execute commands through my driver and check out the signals from the FPGA. ...
1
vote
1answer
144 views

Xilinx Vivado: [Common 17-53] User Exception: Unable to launch Synthesis run. No Verilog or VHDL sources found in project

I have a vivado project containing a Xilinx IP core. A tcl script was generated for this project and contains links to the IP core source. The .tcl script and IP source files (xml, xci and veo files) ...
1
vote
2answers
111 views

Serialize bits from input/output pin with VHDL

The code below reads 40 bits of data sent in serial from a DHT-11 temperature/humidity sensor and stores the data in a 5 byte array of RAM. The code is: ...
0
votes
1answer
50 views

What does “no design unit detected in this file” mean?

I got this error then I tried to add a source file. Can anyone tell me what this means? What should I do to correct it?
0
votes
2answers
46 views

Debugging simulation error in Xlinx for VHDL

I used Xilinx to simulated Logic And Gate, and it worked fine. I followed same procedure to simulate Half-Subtractor, but got stuck in between. When I checked Xilinx window for two codes I found ...
1
vote
1answer
66 views

Analyzing Xilinx Design Summary?

What are: "Number using O6 output only: 1,511", "Number using O5 output only: 37", "Number of Slice registers: 1,866", "Number of 36k BlockRAM used : 2" How can I find out more ...
1
vote
1answer
86 views

Fixing 1 failing timing constraint in Xilinx

In the end of my project I have a timing constraint failure as follows : clk_in is the 100 Mhz system clock on ML507 I don't know why it is not meeting the ...
0
votes
1answer
62 views

Xilinx Design Summary

My project is finished and Xilinx gives lots of statistics in the summary like : How shall I evaluate these values, what can I say about them? What means what? Is this report good or bad? With ...
0
votes
1answer
102 views

Removing warning FF/Latch trimming

I have a 16 bit signal, for me only the last 4 bits are important and the first 12 bits are always "0", so I'm doing nothing with the first 12 bits and in the end it goes out of my component to next ...
0
votes
2answers
527 views

Using Digital Clock Manager with Verilog to generate 25Mhz clock from 32Mhz internal clock

I am writing a VGA driver program in Verilog on a Spartan 3E (FPGA board Papilio one- 500k bundled with LogicStart MegaWIng). The frequency of the internal clock of Spartan 3E is 32MHz. But I need to ...
2
votes
1answer
89 views

VHDL latch for Xilinx Spartan 3E

I am coding a display control for the Spartan 3E. It has 8 LEDs. When the ALU's state signal (from other block) is "00" the MSBs and LSBs are time-multiplexed for one second each byte. When state is ...
-1
votes
0answers
57 views

Learning FPGA Design (Books, Resources, VHDL/Verilog) [closed]

I used to use FPGA's back in college and I really enjoyed it. Years have passed though and I haven't had much time to play with it since then. I have realized I have forgotten some stuff (quite a bit ...
1
vote
1answer
42 views

Power Analysis in Xlinx ISE

I wanted to know the performance of the design in terms of switching activity (hence the power consumption) using Xlinx ISE. I have Xlinx ISE 14.3 webpack version. Is it possible to do such ...
0
votes
0answers
90 views

Where is the pixel data in xilinx AXI_video DMA IP ? to apply a sobel filter on that data

I want to read/write some data in streaming mode from/to memory using AXI video DMA. It has two signals M_MM2S and S_S2MM (memory to axi stream and axi stream to memory) which probably contains the ...
0
votes
1answer
99 views

Using '$display' in Xilinx(verilog)

I am trying to write a testbench for a 16-bit RISC processor using verilog in Xilinx. I have the following modules: - TOP -datapath -instruction_fetch -program_counter ...
0
votes
2answers
142 views

Usage of UCF file and Clock Divider?

I know VHDL and I understand the syntax but I never programmed an FPGA before. I am going to write soon my first VHDL code and then upload my code to Xilinx FPGA. When writing VHDL code we have ...
2
votes
1answer
96 views

making different clocks in system generator

I have a circuit in system generator which I cannot retrieve the output signal since it has a high rate. For this issue I planned to use a FIFO at the output. I wanna give the circuit clock to ...
2
votes
0answers
97 views

Spartan 6 configuration with Cypress FX2LP

I'm trying to load configuration to my FPGA board using Cypress FX2LP from USB. The basic implementation comes from Cypress's AN63620 application note, but instead Spartan 3 I use Spartan 6 (xc6slx4), ...
2
votes
1answer
166 views

FPGA or microcontroller for this robot

I am at a loss of whether I need to use an FPGA or a microcontroller. I need to build a robot that can chase my cats around and shoot them with a water gun. So there seems to be a number of parallel ...
2
votes
1answer
38 views

Discrepancy in output of post PAR simulation and bit file output

I am using Xilinx ISE to generate a bit file. I verified the functionality by post synthesis as well as post Place and route simulation . But when same bit file was loaded in FPGA there was a zero ...
1
vote
2answers
121 views

Dynamically Configure FPGA From Host Program

I was wondering if anyone knows an efficient way to program the FPGA(PL) for a Xilinx Zynq-7 series or related devices,from a host C program (not on the SoC, but from the host PC). Is there an Xilinx ...
1
vote
1answer
173 views

Why Linux doesn't get booted automatically only If I changed the BOOT.bin not the zImage, while in the first case it gets automatically booted

I have zynq board ( not the zedboard), it doesn't have all the peripherals of zedboard. I am facing some problem while booting the linux on zynq with my new BOOT.bin. When I used to put the sdcard in ...
0
votes
0answers
198 views

Xilinx SDK - MMU Section Translation Fault Issue

I am trying to run the base programming hello world for the TE0720 with Zynq xc7020. The link to the tutorial is here. After following all of the instructions and proceeding without any errors, I try ...
-3
votes
1answer
179 views

Max output current per I/O pins from Basys2 (SPARTAN 3E) board [closed]

I am trying to drive IR leds out of spartan 3E fpga on xilinx's BASYS2 board. I will be using external current amplifier to drive the IR lEDs with control singal from the FPGA. I need to know the max ...
0
votes
1answer
261 views

Tutorials on embedded programing using Zynq 7020 with ARM processor

Just as the question states. I have been having trouble being able to just test out the programming side of the ARM processor on the TE0720 board. I have been searching online for how to setup the ...
0
votes
1answer
379 views

Problem with Xilinx SDK - Failed to Scan JTAG Chain

I am having an issue with running a simple Hello World program on the Trenz TE0720-01 board with a Zync 7020 FPGA. I have been following the tutorial to setup and run the Hello World program given ...
0
votes
1answer
106 views

Spartan 3AN FPGA DCM

While I use the internal clock for DCM clkin input I am getting clk0 as perfect frequency of output same as internal clock but not in remaining o/p pins. I changed from previous coding like this and ...
1
vote
1answer
114 views

Retrieving samples from an FPGA using Ethernet

I have a Spartan 3 FPGA for implementing a specific kind of digital modulation. I read the output signal by UART and RS232 but the rate is too slow for following high frequency signals. It was ...
1
vote
2answers
147 views

Help needed with SPARTAN-3AN FPGA frequency doubler

Here I attached the routed nets for this below verilog HDL program with DCM instantiate module. while I am implementing in XC3S50AN FPGA board using using ISE12.3 Design suite clk2x & locked ...
2
votes
2answers
145 views

Constraining a 7 segment display in VHDL

Right now I'm just trying to configure a single digit 7 segment display, and I'm pretty stuck. All of the resources I can find say to use a 7 bit logic vector and just stop there. So I understand ...
1
vote
0answers
80 views

Integrating third-party IP core using Xilinx command line tools

I am trying to integrate a third-party IP core, which is given in form of an .ngc netlist file and a corresponding .vhd file with only the entity declaration, into my design. The IP core was ...
1
vote
1answer
261 views

How to increase QSPI flash clock frequncy in Zynq ZC702

I am working on Zynq ZC702 board. The board has a QSPI flash. I want to increase the clock frequency of QSPI, so that I can read/write at a much faster rate. The closest I found is this : ...
0
votes
1answer
119 views

Any good suggestions for Basys2 optional oscillator 50 MHz or 100 MHz? [closed]

I want to get the optional stable oscillator for the Basys-2 but don't know which would be the best choice for 50 MHz and 100 MHz? Has anyone bought and used any? If so, what is the part number?