A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices).

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In VHDL what is a data operator type “variable” when it is translated to circuit? [duplicate]

VHDL code is finally converted into hardware equivalent when it is synthesized. What happens to data operator type "variable" when it is synthesized?
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1answer
34 views

Optimum aspect ratio for storing data in Block RAMs

I am working on Xilinx virtex 4 FPGA. I want to store some filter coefficients in Block RAMs. Specifically, I have many sets of filter, each set having 64 coefficient, each coefficient is of 18 bits. ...
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71 views

Selfbuilt USB-JTAG programmer for FPGA's [closed]

I want to program an FPGA (XILINX Spartan III), with USB port of my laptop, and I want to design the programming circuit myself (not using the XILINX's cable). So, I want to build a USB-JTAG ...
3
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1answer
223 views

having distorted image in VGA with FPGA board

I'm using spartan 3E-100 CP132 fpga board to display a basic plus image on a monitor. I have tried using 800x600 72 hz and 640x480 60 Hz but I always get a distorted vertical lines. Is it because the ...
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4answers
161 views

High speed memory interface between 2 FPGAs (Virtex 6)

I have a board with 2 Virtex 6 FPGAs, which are connected to each other through 64 parallel IO lines that can operate up to 400 MHz. One FPGA, let's call it B, also has 2 GB of DDR3 memory connected ...
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0answers
50 views

Routing errors when trying to implement PLL onto Spartan-6 FPGA board

I am attempting to synthesize and implement the reference design that is linked to in the 'Reference Design Additional Information' section of the following document. I get the following error ...
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1answer
61 views

How to simulate PCIe to debug my FPGA endpoint

I'm working on an FPGA controller connected through PCIe. The only way I can debug the hardware is using chipscope. So I execute commands through my driver and check out the signals from the FPGA. ...
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1answer
40 views

Xilinx Vivado: [Common 17-53] User Exception: Unable to launch Synthesis run. No Verilog or VHDL sources found in project

I have a vivado project containing a Xilinx IP core. A tcl script was generated for this project and contains links to the IP core source. The .tcl script and IP source files (xml, xci and veo files) ...
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2answers
60 views

Serialize bits from input/output pin with VHDL

The code below reads 40 bits of data sent in serial from a DHT-11 temperature/humidity sensor and stores the data in a 5 byte array of RAM. The code is: ...
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1answer
39 views

What does “no design unit detected in this file” mean?

I got this error then I tried to add a source file. Can anyone tell me what this means? What should I do to correct it?
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2answers
41 views

Debugging simulation error in Xlinx for VHDL

I used Xilinx to simulated Logic And Gate, and it worked fine. I followed same procedure to simulate Half-Subtractor, but got stuck in between. When I checked Xilinx window for two codes I found ...
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1answer
39 views

Analyzing Xilinx Design Summary?

What are: "Number using O6 output only: 1,511", "Number using O5 output only: 37", "Number of Slice registers: 1,866", "Number of 36k BlockRAM used : 2" How can I find out more ...
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1answer
60 views

Fixing 1 failing timing constraint in Xilinx

In the end of my project I have a timing constraint failure as follows : clk_in is the 100 Mhz system clock on ML507 I don't know why it is not meeting the ...
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0answers
47 views

Xilinx Design Summary

My project is finished and Xilinx gives lots of statistics in the summary like : How shall I evaluate these values, what can I say about them? What means what? Is this report good or bad? With ...
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1answer
45 views

Removing warning FF/Latch trimming

I have a 16 bit signal, for me only the last 4 bits are important and the first 12 bits are always "0", so I'm doing nothing with the first 12 bits and in the end it goes out of my component to next ...
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2answers
163 views

Using Digital Clock Manager with Verilog to generate 25Mhz clock from 32Mhz internal clock

I am writing a VGA driver program in Verilog on a Spartan 3E (FPGA board Papilio one- 500k bundled with LogicStart MegaWIng). The frequency of the internal clock of Spartan 3E is 32MHz. But I need to ...
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1answer
68 views

VHDL latch for Xilinx Spartan 3E

I am coding a display control for the Spartan 3E. It has 8 LEDs. When the ALU's state signal (from other block) is "00" the MSBs and LSBs are time-multiplexed for one second each byte. When state is ...
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0answers
53 views

Learning FPGA Design (Books, Resources, VHDL/Verilog) [closed]

I used to use FPGA's back in college and I really enjoyed it. Years have passed though and I haven't had much time to play with it since then. I have realized I have forgotten some stuff (quite a bit ...
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1answer
36 views

Power Analysis in Xlinx ISE

I wanted to know the performance of the design in terms of switching activity (hence the power consumption) using Xlinx ISE. I have Xlinx ISE 14.3 webpack version. Is it possible to do such ...
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69 views

Where is the pixel data in xilinx AXI_video DMA IP ? to apply a sobel filter on that data

I want to read/write some data in streaming mode from/to memory using AXI video DMA. It has two signals M_MM2S and S_S2MM (memory to axi stream and axi stream to memory) which probably contains the ...
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1answer
80 views

Using '$display' in Xilinx(verilog)

I am trying to write a testbench for a 16-bit RISC processor using verilog in Xilinx. I have the following modules: - TOP -datapath -instruction_fetch -program_counter ...
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2answers
90 views

Usage of UCF file and Clock Divider?

I know VHDL and I understand the syntax but I never programmed an FPGA before. I am going to write soon my first VHDL code and then upload my code to Xilinx FPGA. When writing VHDL code we have ...
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1answer
60 views

making different clocks in system generator

I have a circuit in system generator which I cannot retrieve the output signal since it has a high rate. For this issue I planned to use a FIFO at the output. I wanna give the circuit clock to ...
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0answers
72 views

Spartan 6 configuration with Cypress FX2LP

I'm trying to load configuration to my FPGA board using Cypress FX2LP from USB. The basic implementation comes from Cypress's AN63620 application note, but instead Spartan 3 I use Spartan 6 (xc6slx4), ...
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1answer
149 views

FPGA or microcontroller for this robot

I am at a loss of whether I need to use an FPGA or a microcontroller. I need to build a robot that can chase my cats around and shoot them with a water gun. So there seems to be a number of parallel ...
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1answer
36 views

Discrepancy in output of post PAR simulation and bit file output

I am using Xilinx ISE to generate a bit file. I verified the functionality by post synthesis as well as post Place and route simulation . But when same bit file was loaded in FPGA there was a zero ...
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2answers
94 views

Dynamically Configure FPGA From Host Program

I was wondering if anyone knows an efficient way to program the FPGA(PL) for a Xilinx Zynq-7 series or related devices,from a host C program (not on the SoC, but from the host PC). Is there an Xilinx ...
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1answer
119 views

Why Linux doesn't get booted automatically only If I changed the BOOT.bin not the zImage, while in the first case it gets automatically booted

I have zynq board ( not the zedboard), it doesn't have all the peripherals of zedboard. I am facing some problem while booting the linux on zynq with my new BOOT.bin. When I used to put the sdcard in ...
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0answers
129 views

Xilinx SDK - MMU Section Translation Fault Issue

I am trying to run the base programming hello world for the TE0720 with Zynq xc7020. The link to the tutorial is here. After following all of the instructions and proceeding without any errors, I try ...
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1answer
126 views

Max output current per I/O pins from Basys2 (SPARTAN 3E) board [closed]

I am trying to drive IR leds out of spartan 3E fpga on xilinx's BASYS2 board. I will be using external current amplifier to drive the IR lEDs with control singal from the FPGA. I need to know the max ...
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1answer
182 views

Tutorials on embedded programing using Zynq 7020 with ARM processor

Just as the question states. I have been having trouble being able to just test out the programming side of the ARM processor on the TE0720 board. I have been searching online for how to setup the ...
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1answer
199 views

Problem with Xilinx SDK - Failed to Scan JTAG Chain

I am having an issue with running a simple Hello World program on the Trenz TE0720-01 board with a Zync 7020 FPGA. I have been following the tutorial to setup and run the Hello World program given ...
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1answer
93 views

Spartan 3AN FPGA DCM

While I use the internal clock for DCM clkin input I am getting clk0 as perfect frequency of output same as internal clock but not in remaining o/p pins. I changed from previous coding like this and ...
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1answer
100 views

Retrieving samples from an FPGA using Ethernet

I have a Spartan 3 FPGA for implementing a specific kind of digital modulation. I read the output signal by UART and RS232 but the rate is too slow for following high frequency signals. It was ...
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2answers
132 views

Help needed with SPARTAN-3AN FPGA frequency doubler

Here I attached the routed nets for this below verilog HDL program with DCM instantiate module. while I am implementing in XC3S50AN FPGA board using using ISE12.3 Design suite clk2x & locked ...
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2answers
98 views

Constraining a 7 segment display in VHDL

Right now I'm just trying to configure a single digit 7 segment display, and I'm pretty stuck. All of the resources I can find say to use a 7 bit logic vector and just stop there. So I understand ...
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0answers
55 views

Integrating third-party IP core using Xilinx command line tools

I am trying to integrate a third-party IP core, which is given in form of an .ngc netlist file and a corresponding .vhd file with only the entity declaration, into my design. The IP core was ...
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1answer
155 views

How to increase QSPI flash clock frequncy in Zynq ZC702

I am working on Zynq ZC702 board. The board has a QSPI flash. I want to increase the clock frequency of QSPI, so that I can read/write at a much faster rate. The closest I found is this : ...
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1answer
93 views

Any good suggestions for Basys2 optional oscillator 50 MHz or 100 MHz? [closed]

I want to get the optional stable oscillator for the Basys-2 but don't know which would be the best choice for 50 MHz and 100 MHz? Has anyone bought and used any? If so, what is the part number?
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81 views

Xilinx Spartan3-E FPGA input impedance and input leakage current for the GPIO pins

I am trying to use one of SPARTAN3-E FPGA GPIO pin as an input to ADC. I want to know the input impedance and the leakage current for GPIO? Should I just connect my circuit's Vout to GPIO pin or ...
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2answers
114 views

Spartan 3AN (XC3S50AN) memory [closed]

Presently we are doing some automation operation using microcontrollers but I wish to change the technology to CPLD/FPGA. So, I wrote a Verilog program in XILINX (XC9572XL) but it has 72 micro-cells ...
2
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2answers
241 views

Using BRAM instead of SRAM in Virtex-5 FPGA

I am working on a project where we are capturing signals from an ADC using a Virtex-5 FPGA and the samples are being stored on a 128K x 256 SRAM from where the data samples are acquired by a PC. I ...
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2answers
149 views

Using the PS/2 port of the Papilio One FPGA from VHDL

I'm trying to receive data from a keyboard via the PS/2 port on the Papilio One Arcade Megawing. Eventually I'll want to implement this from scratch, but I thought I'd get some public code working ...
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1answer
95 views

Problem using FSL with microblaze

I want to pass some data from my verilog to my microblaze core in ISE 14.7. I was doing some research and it seemed like the FSL was the easiest way to go about this. What I did was create a ...
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1answer
141 views

Xilinx FPGA Input data timing constraint

I'm using Xilinx Spartan 6 Automotive FPGA. My FPGA design has a SPI interface to a external peripheral. From FPGA to the peripheral, I have these SPI related signals: spi clk spi data (mosi) - ...
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1answer
147 views

What is the use of OFFSET IN/OUT constraint for FPGA design when using register in IOB?

The following is asked in the context of Xilinx FPGAs (my experience), but may also apply to similar technologies offered by other vendors. Background: When writing constraints for FPGA I/O, there ...
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1answer
135 views

Online FPGA/HDL synthesizer

I recall seeing a web-based HDL synthesizer a couple years ago, but I can't find it anymore. I believe it was just a frontend that ran the vendors' synthesis tools on the server. Does this sound ...
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50 views

ppc405 communication with custom ip ml403

I am trying to simulate a chemical reaction in FPGA. My basic FPGA architecure consists of 3 processes: ...
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3answers
143 views

Exact recreation of Xilinx FPGA binaries from source control

I'm software developer in a small shop where there's only been one EE guy responsible for a series of FPGA designs spanning a decade, almost all of which target the Spartan line, specifically the ...
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1answer
352 views

Connected to Multiple Drivers Problem Verilog

After I synthesize it, the error occured like this: ...