A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices).

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Understanding Address Map

Please refer to this image of page 113 of this manual I'm not understanding this table. From what I can tell, I have from 0010_0000 to 3FFF_FFF of DDR memory, which is 1 072 693 247 bytes and ...
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28 views

Where to get started? Digital Lockin Amplifier

Being an experienced embedded programmer/designer (AVR, PIC, ARM), I want to design a digital lockin amplifier. I know that I need a DSP for this and I see many people using the Xilinx Spartan6 ...
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29 views

Read .txt (matrices) from SD to DDR - Zedboard

I'm converting a C algorithm into VHDL with Vivado HLS, and after exporting the RTL into Vivado and completing the design I'm using Xilinx SDK to right in the ARM9 PS. Problem: The algorithm is meant ...
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25 views

Best way to pass floating-point numbers to DDR - Zedboard

I have a Zedboard and I made a PL block in Vivado HLS that is going to return milions of floats to the DDR via an AXI DMA block, and those results are then going to be read by the PS from the memory. ...
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12 views

Extract dynamic power Xilinx XPower

As i see in text books, Power trace of a design can be extracted using Xilinx Design Suit which show dynamic power vs. time. However trying to use Xilinx XPower and Power Estimator, it only shows ...
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28 views

Can't Search for specific value at RAM - verilog

My module has search for specific value at RAM and then return its location address. when I wrote a test bench, I see that the module didn't work correctly! always the output value is "don't care". ...
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34 views

Which is the best way to version control Xilinx PlanAhead projects?

Actually I'm migrating some mature projects from Xilinx ISE to Xilinx PlanAhead. I need to take advantage of TCL scripting and partitioning of PlanAhead. This ISE projects are under version control ...
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118 views
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56 views

VHDL Overmapping and Time Constaint issues in Xilinx-ISE

I have an issue with a module I use for rotation of a vector. I have two operations one uses 2 rotLeft modules and the other uses 2 rotRights. Originally I had occupied Slices overmapping issues which ...
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45 views

Synthesizable memory blocks

In Verilog, I am trying to store the input up to 4 previous values and then operate on them.The code is fine in simulation but on FPGA, it calculates output with the current input instead of previous ...
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40 views

Pipeline loop with sum

I'm working with a Zedboard and I'm trying to optimize some functions in Vivado HLS. However, when there are functions like the following where I don't know what to do. E.g: ...
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35 views

Which version should be used for xilinx in windows 8

which xilinx version should I use for windows 8.1?? I have xilinx 13.1 but it does not work for 8.1. Thanks in advance.
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153 views

Can I generate a 90° Clock signal with Xilinx's ODELAY for RGMII?

Some time ago I implemented a GMII interface for my Gigabit Ethernet core. Now I'm trying to do the same with the RGMII protocol. The reference implementation from Xilinx uses IDELAY[|E1|E2] ...
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16 views

Number of I/O pins in Xilinx Virtex 5

This might not be a typical Stackoverflow question, but I wasn't sure where I could get this answered. I have Verilog code to multiply two matrices and read them out, but my throughput is limited ...
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33 views

Why does Xilinx Translate for Virtex-6 not know IOSTANDARD LVDS?

I'm using several Xilinx FPGAs and boards from Spartan3E up to KC705/VC707 and I'm very familiar with UCF files, but there is one question that bothers me... Why does translate for Virtex-6 not know ...
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73 views

Using iSim to simulate 16-bit CLA schematic on Xilinx, all inputs and outputs on the waveform are 'X'. How can I debug?

I'm building a sixteen bit Carry Lookahead Adder for my EE class. I'm definitely a noob to all this so bear with me, however I've been googling for a WHILE and haven't found any answers. Here is the ...
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67 views

display FPGA frequency on oscilloscope?

I used sparten 3e starter board.i want to DISPLAY the PWM frequency output on Oscilloscope?which output pin i have to used ?I used J1 and J2 .the signal is distorted .why? How ? please
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36 views

How to assign the same value to a bus in Xilinx ISE (Schematic)?

How to set all the bits for example in bus(7:0) to the value in net0?
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75 views

Convert IEEE Double to Integer - Verilog

I want to convert the IEEE Double value computed in my code to Integer. E.g. I have computed: X = 64'hxxxxxxxxxxxxxxxx; Now i want to use it as index of an array as: some_array[X]; How can I do it? ...
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19 views

Convert IEEE Double to Integer - Verilog [duplicate]

I want to convert the IEEE Double value computed in my code to Integer. E.g. I have computed: X = 64'hxxxxxxxxxxxxxxxx; Now i want to use it as index of an array as: some_array[X]; How can I do it? ...
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23 views

Macrocell and Function Block optimization ISE XILINX

I get the following result when I compile my code in ISE. It says the CPLD is full, but I can't help but notice that the optimizer should be able to move elements from different function blocks to ...
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64 views

4 port 12 bit mux is consuming 48 macrocells!

I'm programming on the coolrunner II cpld. It is running out of resources so I decided to implement my own 4 port, 12 bit mux. After implementation I find that it's using over 40 macrocells. Any way ...
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23 views

synthesizable vhdl for comparison operations

does the relational operator synthesize < or > can we use IEEE.STD_LOGIC_UNSIGNED for synthesis
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84 views

Setup and hold time violation constraints for Xilinx Fifo generator

I have a problem concerning the Xilinx Fifo generator and timing contraints described in the fifo manual. I am using the fifo generator version 9.2 (manual ) to generate a fifo. I would like to ...
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113 views

Use Xilinx Primitive elements in Verilog inside ISE

I generated Verilog Post-Route simulation model of my original Verilog module, using Xilinx ISE. It will generate a Verilog module using LUT and fpga level primitives such as IBUF,X_LUT4, ... When ...
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76 views

Oscilator with Limited oscillation count

I did implement below oscillator using cascaded not gates. I want to know how can I change such circuit to oscillate only for limited number of oscillations? e.g. I want designed circuit oscillate ...
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112 views

PN sequence generator using linear feedback shift register in VHDL

I got a code for PN sequence generator using linear feedback shift register in VHDL. I am using 1010 as a initial seed but in the output all the four PN sequences ...
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135 views

Xilinx Virtex 6 Board - ISE gives error [Design Contains no instances]

I'm receiving a "design contains no instances" error but I'm unable to find out the cause of the error despite Googling a lot and trying out the solutions suggested on forums. Below is a report ...
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59 views

xilinx create schematic of top modul with lower level moduls

I have a top modul VHDL source file, which has a few instances of lower-level modules (VHDL) and signals which connects these lower-level modules. How can I generate a schematic for this? I mean, I ...
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78 views

How does Xilinx MIG AXI interface map to DDR PHY pinout?

At the bottom of page 156 of UG586 I can understand how the User Address maps to the PHY pinout. However, I can't understand page 155 of the same manual. How does the 32-bit Microblaze address space ...
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34 views

Video system processing using FPGA. Options [duplicate]

I have to design a PCB where a FPGA, ASIC or SOC will be used and the system has to be able to record the video from a camera and display the live video in a display HD. The camera has a resolution ...
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134 views

How to quickly fill up the entire DDR memory using Xilinx tools?

I have a board with a DDR3 memory and a Virtex 7 FPGA. I have used Xilinx MIG to create a memory controller and I am able to succesfully read/write to the memory using Microblaze registers. I would ...
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66 views

VHDL: Simulating Delay for ISE UNISIM components

I have extracted VHDL source of my design from Xilinx ISE. It uses UNISIM library to model Look-Up Tables and Flip-Flops and other components. When I simulate my VHDL design (a combinational circuit) ...
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122 views

Can program FPGA but not PROM on my Spartan-3A dev board

I decided to brush the dust off my Xilinx Spartan-3A starter board that I got a while back, and learn to use Verilog. So with the help of Pong Chu's book FPGA Prototyping By Verilog Examples: Xilinx ...
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244 views

The timing-driven placement phase encountered an error

Could someone explain inexperienced VHDL coder what this error message trying to tell me in simple words? I found a similar question here, but here was no answer to it: ...
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166 views

Verilog data input

Hello I am relatively new to verilog and need help on part of a project am working on. I need someone to guide me as to how you read data from an analog device. I bought an analog temperature sensor ...
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64 views

Why does this adder need two clock cycles (two pushes of the button) to display a result?

I'm implementing a simple adder with carry out in VHDL on a BASYS2 board. This is the code below: ...
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84 views

Using XST synthesis with Vivado 2014.3 +

Long time ago, I used to use a Vivado (2012.x) and could modify the setting of the synthesis menu to support XST and add extra option to choose from when doing synthesis. The command ...
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76 views

How to best synthesize a systolic circuit on FPGA?

I am developing a parameterized systolic circuit in VHDL, using generics. It exhibits regularity in 2 dimensions. I am about to synthesize it on Xilinx FPGA. I suspect it is worth informing the ...
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42 views

All Xilinx Blocks must be contained in a level of hierarchy with a System Generator Token error in xilinx

I am trying to simulate psuedo random data generator on simulink but I am getting this error ...
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83 views

BlockRAM location constraints (Xilinx)

I have a VHDL module in which several block RAMs are inferred. Now I would like to place these block RAMs into a certain region of my FPGA (close to some IO pins). How do I do this using Xilinx ...
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656 views

How to give clock on xilinx spartan 6?

I am trying to run a counter on Digilent Atlys Spartan 6 xc6slx45 development kit, which changes counts on clock edge. I am new user to Verilog, so I don't know how to give clock to my program from ...
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254 views

PC serial communication with FPGA

I am designing a simple 16 bit adder circuit in Digilent's Xilinx Spartan 6 FPGA. The Verilog design accepts two 16 bit inputs A and B and returns the 16 bit sum C = A+B. I am ignoring carry in and ...
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149 views

Trouble configuring Virtex-5 FPGA using JTAG

I'm trying to configure a Virtex-5 FPGA on a custom board and I'm using Xilinx iMPACT in order to program the FPGA using a JTAG interface. But iMPACT has trouble detecting the FPGA and gives an error ...
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120 views

Why two Xilinx scripts with different bitgen options yield correct and incorrect behaviors?

I am really puzzled by a FPGA synthesis problem on Xilinx ISE. Precisely, it took me a long hour to discover why a same RTL design (set of VHDL files) works like a charm on a board using a synthesis ...
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86 views

Uploading C program to the ARM core for execution through ethernet!

I want to write a c code on my local PC and upload it to ARM core on Zed-board for execution. I know we can do it using JTAG, but for obvious reason I want to use Ethernet interface. I will be glad ...
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212 views

How does the read & write FIFO of the Xilinx work?

I'm having a problem understanding the mechanisms of the read FIFO and write FIFO of Xilinx IP core generator (in the Xilinx platform studio software). I don't understand how the read FIFO sends data ...
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199 views

Vivado optimizing away my pins

I'm fighting Vivado over what seems like a fairly stupid issue to me. I wrote some Verilog code in ISE (and simulated it). I generated a bitstream in ISE and downloaded it onto the board via impact, ...
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310 views

Bidirectional FPGA implementations (parallel ADC)

New FPGA convert here. I am trying to interface with a parallel ADC as part of a data acquisition project. The pins on the ADC are used for both input and output (not simultaneously). Therefore, I ...
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132 views

How to calculate average delay time of circuit having several possible transition states

Is it possible to calculate average delay for all possible states directly without calculating them individually using Xilinx or with Cadence.