A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices).

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VHDL SPI xilinx spartan 3E

I have nearly non previous experience with VHDL and the most of the code here is given to me by the teacher. I'm trying to communicate with a ADXL362 accelerometer using SPI on a Xilinx Sparten 3E. ...
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23 views

Why has a LUT6 based SRL only 32 entries but not 64?

Xilinx FPGAs are capable of using LUTs as memory elements. The can be used as ROM, RAM and Shift Register (SRL). New Xilinx devices use 6-input LUTs, which gives 64x1 bit for RAMs/ROMs, but only 32 ...
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17 views

Xilinx CORDIC 4.0 Translate parameters question

I'm developing a SysGen model using a CORDIC 4.0 Translate core to pass from rectangular coordinates to polar coordinates. I need understand the Coarse rotation and Compensation scaling options. ...
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43 views

std logic conversion into float in vhdl

I am new in this field. I have a problem with conversion of std logic input into real values. I have been using to_float function but it always showed error. When I ...
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42 views

How to simulate and initialise Block Memory ROM created using Xilinix CORE generator?

I created the ROM correctly using the CORE generator and the correct .coe file. There is supposed to be instruction words inside the memory (32*256). But the data bus out of the memory is always set ...
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44 views

What are LUT (look up table)? [duplicate]

I am learner in verilog with less knowledge and trying to develop more understanding.I wrote a simple verilog code and synthesize and implement it. I do not have understanding of Look up tables. When ...
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43 views

MM2S simple transfer gone wrong

I followed some examples and I already managed to make a big S2MM (stream to memory-mapped) transfer via an AXI DMA. However, now I'm trying the reverse, i.e. to make a simple MM2S transfer to a very ...
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99 views

Xilinx bitgen warning

I am getting a warning in bitgen like: This design is using one or more 9k block RAMs(RAMB8BWER). 9k block RAM data, both user defined and default requires a special bit format. Is it a ...
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2answers
43 views

How to solve routing issues in Artix7?

I am working with Artix 7 (xc7a15tftg256). When the time of Run Implementation,shows the following error message: [Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub ...
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40 views

FPGA utilization augmentation in a System Generator core when updating from ISE 13.2 to ISE 14.7

I have a huge system generator core originally developed with 13.2 version. Actually we are updating some projects to the latest version of ISE, the 14.7. In the final step we consolidate the project ...
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3answers
81 views

PCI-Express and FPGA Development Boards

I'm interested in using some high-performance FPGA development boards, but it seems like most of the high-end, modern options from both Xilinx (Digilent) and Altera (Terasic) seem to be PCIe-based ...
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43 views

Verilog->FPGA: Synthesis, Implementation, and Bitstream (Xilinx Vivado)

I'm taking an introductory course in verilog/fpga. Can someone tell me where I can find detailed information on what the 3 processes (synthesis, implementation and bitstream) are doing before I ...
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36 views

How to multiply base system clock using .xdc constraints in Vivado

This question may be ridiculously rudimentary but I have been going through Xilinx's available guides and videos tearing my hair out... my problem is simply this: I want to use the base 100Mhz clock ...
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3answers
79 views

Datasheet hunting -

I'm having difficulty trying to figure out voltage outputs for FPGAs. Let's use the Xilinx XC3S2000 FG900 as an example, and say I'm trying to figure out the voltage for pin T22. I do a search for the ...
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44 views

S_axilite port, how to deal with AXI GPIO

I have a block made in Vivado HLS that receives 3 parameters: 1-Map_in which is a matrix of values to be normalized. My objective is to connect it to DDR via AXI DMA 2-Map_out which is a matrix of ...
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25 views

Check the value of FSL_M_Control in the MicroBlaze

I wrote a hardware accelerator which communicates with a MicroBlaze over FSL. In the Microblaze C code I would like to use putfsl() in a loop until the hardware ...
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47 views

Add DDR data into Vivado model - Zedboard

I initially had a doubt on how to read .txt matrices from an SD card to the Zedboard DDR memories:Read .txt (matrices) from SD to DDR - Zedboard Well, I'm now able to read the five 1Mbyte maps into ...
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50 views

Understanding Address Map

Please refer to this image of page 113 of this manual I'm not understanding this table. From what I can tell, I have from 0010_0000 to 3FFF_FFF of DDR memory, which is 1 072 693 247 bytes and ...
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32 views

Where to get started? Digital Lockin Amplifier

Being an experienced embedded programmer/designer (AVR, PIC, ARM), I want to design a digital lockin amplifier. I know that I need a DSP for this and I see many people using the Xilinx Spartan6 ...
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46 views

Read .txt (matrices) from SD to DDR - Zedboard

I'm converting a C algorithm into VHDL with Vivado HLS, and after exporting the RTL into Vivado and completing the design I'm using Xilinx SDK to right in the ARM9 PS. Problem: The algorithm is meant ...
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35 views

Best way to pass floating-point numbers to DDR - Zedboard

I have a Zedboard and I made a PL block in Vivado HLS that is going to return milions of floats to the DDR via an AXI DMA block, and those results are then going to be read by the PS from the memory. ...
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17 views

Extract dynamic power Xilinx XPower

As i see in text books, Power trace of a design can be extracted using Xilinx Design Suit which show dynamic power vs. time. However trying to use Xilinx XPower and Power Estimator, it only shows ...
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35 views

Can't Search for specific value at RAM - verilog

My module has search for specific value at RAM and then return its location address. when I wrote a test bench, I see that the module didn't work correctly! always the output value is "don't care". ...
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65 views

Which is the best way to version control Xilinx PlanAhead projects?

Actually I'm migrating some mature projects from Xilinx ISE to Xilinx PlanAhead. I need to take advantage of TCL scripting and partitioning of PlanAhead. This ISE projects are under version control ...
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163 views
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65 views

VHDL Overmapping and Time Constaint issues in Xilinx-ISE

I have an issue with a module I use for rotation of a vector. I have two operations one uses 2 rotLeft modules and the other uses 2 rotRights. Originally I had occupied Slices overmapping issues which ...
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46 views

Synthesizable memory blocks

In Verilog, I am trying to store the input up to 4 previous values and then operate on them.The code is fine in simulation but on FPGA, it calculates output with the current input instead of previous ...
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44 views

Pipeline loop with sum

I'm working with a Zedboard and I'm trying to optimize some functions in Vivado HLS. However, when there are functions like the following where I don't know what to do. E.g: ...
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52 views

Which version should be used for xilinx in windows 8

which xilinx version should I use for windows 8.1?? I have xilinx 13.1 but it does not work for 8.1. Thanks in advance.
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205 views

Can I generate a 90° Clock signal with Xilinx's ODELAY for RGMII?

Some time ago I implemented a GMII interface for my Gigabit Ethernet core. Now I'm trying to do the same with the RGMII protocol. The reference implementation from Xilinx uses IDELAY[|E1|E2] ...
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2answers
22 views

Number of I/O pins in Xilinx Virtex 5

This might not be a typical Stackoverflow question, but I wasn't sure where I could get this answered. I have Verilog code to multiply two matrices and read them out, but my throughput is limited ...
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1answer
43 views

Why does Xilinx Translate for Virtex-6 not know IOSTANDARD LVDS?

I'm using several Xilinx FPGAs and boards from Spartan3E up to KC705/VC707 and I'm very familiar with UCF files, but there is one question that bothers me... Why does translate for Virtex-6 not know ...
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90 views

Using iSim to simulate 16-bit CLA schematic on Xilinx, all inputs and outputs on the waveform are 'X'. How can I debug?

I'm building a sixteen bit Carry Lookahead Adder for my EE class. I'm definitely a noob to all this so bear with me, however I've been googling for a WHILE and haven't found any answers. Here is the ...
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72 views

display FPGA frequency on oscilloscope?

I used sparten 3e starter board.i want to DISPLAY the PWM frequency output on Oscilloscope?which output pin i have to used ?I used J1 and J2 .the signal is distorted .why? How ? please
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41 views

How to assign the same value to a bus in Xilinx ISE (Schematic)?

How to set all the bits for example in bus(7:0) to the value in net0?
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82 views

Convert IEEE Double to Integer - Verilog

I want to convert the IEEE Double value computed in my code to Integer. E.g. I have computed: X = 64'hxxxxxxxxxxxxxxxx; Now i want to use it as index of an array as: some_array[X]; How can I do it? ...
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19 views

Convert IEEE Double to Integer - Verilog [duplicate]

I want to convert the IEEE Double value computed in my code to Integer. E.g. I have computed: X = 64'hxxxxxxxxxxxxxxxx; Now i want to use it as index of an array as: some_array[X]; How can I do it? ...
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28 views

Macrocell and Function Block optimization ISE XILINX

I get the following result when I compile my code in ISE. It says the CPLD is full, but I can't help but notice that the optimizer should be able to move elements from different function blocks to ...
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67 views

4 port 12 bit mux is consuming 48 macrocells!

I'm programming on the coolrunner II cpld. It is running out of resources so I decided to implement my own 4 port, 12 bit mux. After implementation I find that it's using over 40 macrocells. Any way ...
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25 views

synthesizable vhdl for comparison operations

does the relational operator synthesize < or > can we use IEEE.STD_LOGIC_UNSIGNED for synthesis
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105 views

Setup and hold time violation constraints for Xilinx Fifo generator

I have a problem concerning the Xilinx Fifo generator and timing contraints described in the fifo manual. I am using the fifo generator version 9.2 (manual ) to generate a fifo. I would like to ...
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1answer
144 views

Use Xilinx Primitive elements in Verilog inside ISE

I generated Verilog Post-Route simulation model of my original Verilog module, using Xilinx ISE. It will generate a Verilog module using LUT and fpga level primitives such as IBUF,X_LUT4, ... When ...
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2answers
81 views

Oscilator with Limited oscillation count

I did implement below oscillator using cascaded not gates. I want to know how can I change such circuit to oscillate only for limited number of oscillations? e.g. I want designed circuit oscillate ...
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147 views

PN sequence generator using linear feedback shift register in VHDL

I got a code for PN sequence generator using linear feedback shift register in VHDL. I am using 1010 as a initial seed but in the output all the four PN sequences ...
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1answer
174 views

Xilinx Virtex 6 Board - ISE gives error [Design Contains no instances]

I'm receiving a "design contains no instances" error but I'm unable to find out the cause of the error despite Googling a lot and trying out the solutions suggested on forums. Below is a report ...
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66 views

xilinx create schematic of top modul with lower level moduls

I have a top modul VHDL source file, which has a few instances of lower-level modules (VHDL) and signals which connects these lower-level modules. How can I generate a schematic for this? I mean, I ...
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94 views

How does Xilinx MIG AXI interface map to DDR PHY pinout?

At the bottom of page 156 of UG586 I can understand how the User Address maps to the PHY pinout. However, I can't understand page 155 of the same manual. How does the 32-bit Microblaze address space ...
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34 views

Video system processing using FPGA. Options [duplicate]

I have to design a PCB where a FPGA, ASIC or SOC will be used and the system has to be able to record the video from a camera and display the live video in a display HD. The camera has a resolution ...
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144 views

How to quickly fill up the entire DDR memory using Xilinx tools?

I have a board with a DDR3 memory and a Virtex 7 FPGA. I have used Xilinx MIG to create a memory controller and I am able to succesfully read/write to the memory using Microblaze registers. I would ...
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75 views

VHDL: Simulating Delay for ISE UNISIM components

I have extracted VHDL source of my design from Xilinx ISE. It uses UNISIM library to model Look-Up Tables and Flip-Flops and other components. When I simulate my VHDL design (a combinational circuit) ...