A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices).

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-5
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1answer
23 views

verilog code to perform {w=(3*(p+t-1))/t} with look up taples

I want verilog code to perform {w=(p+t-1)/t} with look up taples . The lookup table is to be realized as a ROM where: p is 3 bits t is 2 bits (and not equal to 0)
0
votes
1answer
39 views

designing a state machine to detect a certain bit

So, I need to create a state machine (mealy machine) to detect the bit 1010 and also I need to code it in verilog. Here is a picture of my state machine: So, I created the state machine and Now I ...
0
votes
1answer
136 views

pulse width modulation

I need help on number one of this practice assignment. I barely learned about this so it is kind of hard me to understand it right now. So any advice or help is appreciated. I want to determine the ...
2
votes
1answer
38 views

What is the purpose of a “BUF” in Xilinx ISE schematic?

I'm working on a schematic for a Xilinx CPLD using ISE. The schematic has a triangle symbol labeled "BUF" before every output, and also between some other nets. I can't really tell why some ...
0
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0answers
83 views

FPGA ft232h/ft2232h communication problem

I am trying to output an image from a Kintex 7 fpga using the ft232h chip. What's supposed to happen in this process is: the fpga must wait until some input pin txe# goes down, then the fpga should: ...
-4
votes
0answers
30 views

I am trying to build a 4 bit squarer [duplicate]

I need some help with building a 4-bit squarer block diagram. Can anyone help me or know a link to a 4 bit squarer block diagram or a verilog code for it? Thanks in advance.
0
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0answers
62 views

I need some assistance on improving my Verilog code

Basically, I am using a lookup table to output in bcd the square of a single digit bcd. I need help on improving my code. So, when I input a number I get a square. But what I want to do is output the ...
3
votes
1answer
251 views

Vivado is removing registers which will be used

I am working on a verilog program that I want to have display some sort of audio waveform (captured from my microphone) over a VGA. I use the following module to shift in new audio samples, and swap ...
0
votes
1answer
33 views

Displaying signals in testbench from counter VHDL

Say I have a count signal in a counter VHDL file and want to display this in my simulation output, what would I have to do to my testbench to output such data?
0
votes
0answers
41 views

Implementing clock divider VHDL

I have written a FSM using a clock divider with the source frequency being 5MHz and trying to take it down to 3 for simulation sake but the clocks come as U in the simulation like so : I am ...
0
votes
1answer
34 views

Generated clock constraints in vivado

I created my own clock since I need a 2Mhz clock and the clock generator IP wont let me go bellow 6Mhz. I created a clock divider module. ...
1
vote
1answer
42 views

Is $realtobits synthsizeiable?

I have been trying to figure out why my verilog program is not working for hours. To test it I just added some constants as inputs to my module and I am using the integrated logic analyser to check ...
0
votes
0answers
25 views

Using on board SPI of Basys 3 to store custom data

I have a Basys 3 board which has an on board SPI flash memory. Configuration bitstream of the implemented logic can be written to this memory through vivado. Reference manual of the board says that ...
0
votes
2answers
79 views

creating a bcd squarer using verilog

Basically, I am using a lookup table to output in bcd the square of a single digit bcd. The problem that I have is that it is not outputting the correct answer. For example: the result I get for the ...
1
vote
1answer
54 views

Why SATA ALIGN primitive is shifted or swapped on 7-Series GTXE2 transceiver RXDATA output?

I am using a Xilinx 7-Series GTXE2 Transceiver configured as SATA host PHY. This transceiver is interfacing with an SATA Host controller and an SATA Gen1 device. During initialization, I am able to ...
-1
votes
1answer
31 views

Multiplier 4-bit with verilog using just full adders

I am trying to write the test bench part but I don't know how to do it. Basically, I want to test out 0x10 or 5x5. I don't if what I have is right. here's a pic to give you some idea of what i am ...
0
votes
0answers
57 views

Vivado IP is locked due to license

I just got the nexys video from diligent. I want to get the HDMI output working. I went to use the HDMI 1.4/2.0 Transmitter Subsystem IP. When I try to generate the output products I get the ...
1
vote
1answer
48 views

How can I constrain an imported netlist in Vivado?

I have a pre-compiled netlist (created by Xilinx ISE 14.7), which is imported into Vivado 2015.4 and used in synthesis to assemble my complete design. Vivado reports unconstrained paths for the ...
2
votes
1answer
49 views

Configuring multiple FPGA using JTAG

I have 2 devices, a Spartan 3 and a Spartan 6. I am trying to configure both of them through JTAG. One way to do this is to daisy chain the devices and use boundary scan. However , one thing I still ...
0
votes
0answers
40 views

Index in block ram is offset by one from position of write

I am having an issue with block ram I am using to create a table to powers of a 64 bit floating point number. I store powers between x^1600 and x^-1600. For some reason when I try to read the table ...
2
votes
1answer
57 views

Do I need a license to design IP cores with AXI interfaces?

Many IP cores especially from Xilinx have an AXI interface from ARM. (AXI, AXI-Lite, AXI-Stream, APB, ... are parts of AMBA - ARM's bus architecture). The AXI interface standard is free for download ...
1
vote
2answers
45 views

Xilinx IP for delaying data

I am working on a block design to compute the coordinate in the complex set represented by a pixel. Given an x and y pixel value, the step size, and starting x and starting y I need to compute a ...
0
votes
0answers
30 views

Xilinx ISE ERROR:Xst:2369 - Empty project file “C:\xxxx” what is it about?

I am trying to see the schematic output of my verilog module in Xilinx ISE. However, I am getting this silly error: ERROR:Xst:2369 - Empty project file "C:\Users\aozel\Desktop\Verilog ...
0
votes
0answers
34 views

I get error in vivado when I try to use source clock of generated one

I want to have two clocks in my project. One that sends output to a VGA and runs at 25 Mhz and another which runs my mandelbrot set calculation at a higher frequency. Here is the code I have. ...
0
votes
0answers
38 views

Do I have to create generated clocks in the top level module?

I have been working on a module to send VGA output from my fpga. I want to generate the 25 MHz clock inside of the vga module. vga_clk_gen is from the clocking wizzard IP in vivado. I get the ...
0
votes
1answer
45 views

FPGA VGA driver not working

I am not really sure what is wrong with my code bellow for a vga. All I want the program to do is display a solid color on the monitor. I want to use the switches on my card to change the color ...
0
votes
0answers
18 views

Petalinux zynq uart connection

I have installed petalinux on my zynq board and I want to connect uart to MIO. I have checked vivado schematic (somebody else has done it) and the uart pins are not connected. If I connect it in ...
2
votes
0answers
50 views

Vivado Webpack VS Design Edition

Right now I am using Vivado design edition which I got for free with my diligent basys 3 FPGA. I am currently looking to upgrade my card to Nexys Video which has a lot more features. ...
0
votes
0answers
26 views

Strange verilog errors in vivado

I am trying to make a floating point module to take the integer power of a double base. I want to compute it using x^y = e^(y*ln(x)). I am using the non-blocking floating point IPs provided by ...
1
vote
1answer
48 views

Why do I get a “[Synth 8-5413] Mix of synchronous and asynchronous control for register” warning in Vivado?

The code bellow is to take the reciprocal of a fixed point number using Newton's method. When start is asserted the state machine enters the estimate state. To get ...
3
votes
1answer
42 views

Error when passing wire of different size to module input

I have a module to display a base 10 number on my 7-Segment display. ...
0
votes
2answers
42 views

BASYS2 - Verilog: how to properly edit ucf file?

I am a newbie at FPGA. I bought BASYS2 digilent board(Spartan3E). I have background on microcontrollers. C/C++ is no problem for me. But I am having some trouble with FPGA. Actually, not with FPGA ...
3
votes
1answer
42 views

Xilinx FPGA, error creating generated clock

I just got a Digilent Basys 3 board (Artix-7 FPGA) and I am trying to create a program to transmit data over the UART-USB connection. I wrote a module but when I tried to implement it I got a timing ...
1
vote
1answer
43 views

What is the pin to light up colon in Basys 2?

I am trying to make a clock in a Basys2 board but I can't find in documentation the pin to light up the colon of the 7segment display. Where is it?
0
votes
0answers
25 views

P&R using Sfixed signals in Xilinx ISE

In my filter design , I am using fixed point arithmetic and using sfixed for signals. The design synthesizes with all timing met but my functional simulation and post synth/P&R simulation do not ...
1
vote
1answer
61 views

Artix 7 Block RAM instantiation in Vivado 2015.2

Ok I'm trying to create a Block RAM instantiation in true dual port type. I have used the IP catalog and block memory generator in Vivado, which has given me a giant file that I now need to strip down ...
1
vote
0answers
67 views

Multi-driver net found

I have been putting together a project for work in Vivado 2015.2 When I try and implement the design I get these errors. The project is pretty large that's why I haven't included it in the post. Is ...
3
votes
1answer
71 views

Xilinx clocking wizard - How to connect clkfb_in and clkfb_out

I created a VHDL design which needs a 50 MHz clock input. The Spartan-6 I'm working on gives me a 100 MHz clock signal, so I used the Xilinx Clocking Wizard to get a 50 MHz clock. When I choose "No ...
2
votes
1answer
51 views

Slow clk output (Spartan-6)

I have a design which looks like this: ...
0
votes
1answer
17 views

Xilinx Coregen FIFO as ZeroDelay model

My VHDL design contains a FIFO generated by Coregen from Vivado 15.3. I try to debug the design with a ZeroDelay simulation. But the core is not Zerodelay and makes short changes (much shorter that a ...
4
votes
1answer
271 views

Pulse on edge of different clock

I have a clock coming from a pin (GMI_CLK). It passes through a PLL and a new clock with 4 times the frequency is generated (Sys_CLK). Now I need a pulse each time a rising edge of the original clock ...
1
vote
0answers
30 views

How to specify timing constraint for two paths to have a equal delay in Vivado

I am trying to sample an asynchronous signal in multiple clock-domains. I do not care too much about the absolute delay from the source of the async signal to the sampling FF's, but I want to ...
0
votes
1answer
63 views

modules in verilog?

In my recent project in Xilinx ISE, I need to create two modules, one for 4-bit multiplier and other for 4-bit adder. In between i need to call the 4-bit adder in multiplier module which I am doing ...
2
votes
0answers
35 views

Xilinx unconstrained path analysis

I'm using Xilinx ISE 14.7 to implement my design but I have some doubts about how to read the constraint interaction report (.tsi) generated during the Post Place&Route Static Timing Analysis. ...
0
votes
0answers
54 views

Next step after making a VHDL design (create IP?)

First of all, I want to say sorry for asking so many questions in the last weeks. It's just that this VHDL to FPGA business is really difficult to understand. I made a design in VHDL with the help of ...
1
vote
0answers
43 views

CellularRAM CE# signal confusion

I'm trying to write a simple memory controller that does synchronous reads/writes for the Micron CellularRAM on the Nexys2 board (http://www.micron.com/parts/psram/cellularram/mt45w8mw16bgx-701-it). ...
2
votes
1answer
57 views

IP Core Generator fails with Error

I'm working on a project using a Spartan-6. I created a FIFO with the IP Core Generator (New Source -> IP Core -> FIFO -> Generate). The LOG looks like this ...
1
vote
1answer
46 views

Adder Implementation in Verilog?

In my digital electronics project I need to calculate dot product of two vectors a and b (256 length of each). Following the basic concept, I need to calculate \$ \sum_{k=1}^{256} a_kb_k \$. Each ...
0
votes
1answer
40 views

FIFO for spartan 3AN : no storage on board but ok in simulation

I made a FIFO using the Core Generator and I'm trying to implement a code that use it... 1) By putting the switch (T9) ON, I start transmitting some datas to my fifo (Here H-e-l-l-o for test) 2) By ...
1
vote
0answers
65 views

Why can't I program a ZC706 (Zynq) board a second time over JTAG?

I have a ZC706 board equipped with a Zynq 045 FPGA. I switched the jumpers to add the Zynq into the JTAG chain of th Digilent programmer. The first programming works as expected, but the second ...