I wish to make sure the input files are checked into source control so I (or others) can build, recreate, branch/modify a design. However with PlanAhead, the same suffixes are used for both input and ...
I asked Xilinx for such a list but they don't have a complete list. I wish to make sure all input files are in source control and all output files aren't. This is with 13.1-13.2 with ISE and PlanAhead ...