Tagged Questions

2
votes
3answers
117 views

Fix Conflicting IO Standards

I am using the Basys 2 Spartan-3E FPGA board with Xilinx. I need the pmod i/o to be at 1.8v so I am using LVCMOS18 IOSTANDARD. You can find all of the IOSTANDARD's available for Spartan-3E in this ...
4
votes
3answers
101 views

FPGA Logic Gate Count

I found an FPGA board that I liked. It uses a Xilinx Spartan 6 LX45. When I went to the datasheet for the Spartan 6 series, it only said that there were 43,661 logic cells. How many gates does that ...
1
vote
1answer
78 views

Interfacing SJA1000 to Spartan6 FPGA

As the title says, I would like to interface an SJA1000 CAN controller to a Xilinx Spartan6 FPGA. The SJA1000 has a shared 8-bit address&data bus with an address latch signal and either separate ...
1
vote
1answer
424 views

Fixed Point Division in verilog for Spartan 6

I am developing a core on Spartan 6 which needs to do divisions like 1/6,2/4 etc... so the values are always between 0 and 1. As I dont need the precision of floating point I am want to use a fixed ...
1
vote
1answer
98 views

What is the minimum current I need to supply to a Spartan-6 pin in order to register a high signal?

Digging around in the spartan-6 DC and switching characteristics guide, I can't find what I'm looking for. Also no absolute max sync/source current ratings for the user IO pins. Looking at the dev ...
4
votes
1answer
180 views

inout port in VHDL RS232 Module from Digilent

I'm looking at the Digilent RS232 reference component available from http://www.digilentinc.com/Products/Detail.cfm?Prod=S3EBOARD for the Spartan 3E Starter Kit. I began putting together a testbench, ...
6
votes
4answers
658 views

How fast does a 64-bit multiply or divide execute on an FPGA?

When using a regular FPGA such as Xilinx Spartan 3 or Virtex 5, how many cycles does a double-precision floating-point 64-bit multiplication or division take to execute? As far as I understand, the ...
2
votes
1answer
109 views

Design doesnot work properly when clock net delay is slightly higher in spartan3a fpga

I am running my design on spartan3a 3s700afg484 at 50 mhz. There is no set up and hold time violations. There is only one global clock net. My clock report for two runs are RUN 1: Info: [707]: | ...
4
votes
2answers
326 views

3.2 Gb/s high speed interface over 50m: copper, fiber, other ideas?

I need to run a 3.2 Gb/s interface over 50m. My client is keen on Cat6e. The lower the price, the better. These are my findings so far: I'm looking at using a Spartan 6 GTP Tranceiver with copper ...
8
votes
3answers
264 views

Compare implementing a simple automation design on a MCU vs an FPGA/CPLD

I have been working with MCU's since the 90's, and I've recently ventured into the FPGA scene with the Spartan6 series chips from Xilinx. Assuming a simple factory automation design with sensors and ...
1
vote
2answers
343 views

constant memory on the Spartan 3 Starter Kit

I'm in dire need of compile-time generated constant memory of ~512K x 16Bit on the Spartan 3 Starter Kit Board. I'm configuring the board over the JTAG port, and wondered if a) there is a way to ...
0
votes
1answer
169 views

Verilog: Pass a vector as a port to a module

I have two modules counter: Output is a vector called error_count. lcd: Module to display the code on an LCD. Input includes clock and error_count. Following snippet of the code is most relevant ...
0
votes
1answer
428 views

Working with Spartan-6 LX9 clock

I am a novice in digital design and are learning things using "Advanced Digital Design with the Verilog HDL" along with a Spartan-6 LX9 board by Xilinx. So far I have managed to blink few leds on the ...
1
vote
4answers
877 views

Clock generation using FPGA

I am trying to use Spartan 3E kit to generate 50 MHz clock. The kit comes along with a 50 MHz crystal which I am trying to use. So, I wrote a simple code to output the clock from the FPGA to the SMA ...
0
votes
1answer
431 views

How to output signal though SMA connector in Spartan 3E Starter Kit

I want to output a signal through the SMA connector available on the Spartan 3E starter kit board. Can someone guide me as to how to do it?
5
votes
3answers
1k views

Can I use ghdl or some other VHDL compiler/simulator than WebPack with a Spartan 3E?

I'm struggling with WebPack's bloat and random broken pieces when running in Linux. So, I'm thinking it may just be easier to use a different compiler/simulator. Is it possible to use something ...
-1
votes
2answers
317 views

Rf modules for FPGA board

Are there any good data rate(~Mbps) RF modules available in market that can be interfaced with Digilent Atlys Spartan®-6 FPGA Development Kit ? Thanks in advance.
10
votes
3answers
1k views

FPGA, first steps

Well this is a continuation of my question on FPGA over here. I finally selected a Digilent Atlys with a Spartan 6 FPGA, I don't have any prior experience of FPGA's although I have done some amount ...