System Generator is a Xilinx tool for developing DSP chips.
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1answer
41 views
For loop does not compile in Matlab mcode using Xilinx block
I have a simple code in xilix type mblock in simulink:
function q = test1( n)
q = 0;
for i = 1:n
q = i;
end;
end
If I run this code naively in matlab ...
0
votes
2answers
127 views
Splitting a bit array in Verilog
i am designing a basic AES algorithm on verilog, and i need to split a 1828 bits array into 16 parts each one of 8 bits, for example (basic no 128 length example), if i receive in my 8 to 2 splitter ...
1
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1answer
178 views
System Generator:How to know how many clock cicles are nedeed for my FFT block?
I would like to know how many clocks cycles the FFTv4_1 require?
Does anyone know how to determine the required clock cycles? I am using the System Generator 9.2i version.
Thank you so much!
1
vote
1answer
155 views
System Generator: Does an fft block need a buffer?
I wonder if is necessary to put a buffer before a FFT block. I want to do a fft, with N = 16 (samples).
Is necessary to design a temporal memory system to save 16 samples before loading into FFT or ...
1
vote
1answer
346 views
System Generator: How to make a buffer implementation
I would like to make a buffer in system generator to use it with a FFT block.
I want to charge 16 values to a FFT block from another system I´ve designed and I need a temporary memory system. Could ...
1
vote
1answer
194 views
Xilinx System Generator: A summary of frequent errors during the Simulink - modelling stage
I wonder if there is a kind of guide or summary about tipical errors at modelling design stage that users tend to do.
Thank you so much for your help.
By the way. Some people ask me why I don´t use ...
0
votes
1answer
153 views
System Generator. Estandard exception in FFT block
I am trying to generate a bitstream file from a the FFTv4 block, but I get errors, one of the errors is about a file called 'fftv4_cw.ise'
This is the error message I get:
standard exception: ...
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votes
1answer
374 views
System Generator: Problems with CORDIC block at getting the bitstream file
I don´t get to get the bitstream file. I have an several errors when I try to generate the bitstream file.
The error
I have this error message from the file call 'xflow.results':
ERROR:Par:228 - ...
0
votes
1answer
165 views
System generator frequency issue
I have a design in Xilinx system generator which meets maximum frequency of 50MHz (I found this from Timing and Power Analyzer of System generator). However, my FPGA board offers 100MHz clock rate. ...
2
votes
1answer
138 views
System Generator: a block similar to a three state logic
does anyone what is the xilinx block for getting a three state logic?
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1answer
293 views
System Generator: How to make an implementation a mathematical function through a ROM
I want to put in a ROM a vector of values I have in the workspace. Does anyone know how to do it?
Thank you to all possible references, articles or comments.
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votes
1answer
257 views
System Generator: a block to change sign of a floating point
I´m working with floating point numbers in System Generator. I need to perform this arithmetic operation y = x*(-1) . I think it could be done by using the mult block, but I don´t like this way ...
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votes
2answers
217 views
System Generator: How to know if my FPGA could have enough resources to perform a design
I am doing a design using System Generator, and I have some doubts if my design could be performed in a Virtex 4 FPGA.
Does anyone know what can I do to check this?
-1
votes
1answer
348 views
Choosing a tool for development: System Generator vs Xilinx ISE
I am trying to make a an implementation of a vhdl design. It´s an application for signal processing. Does anyone know what is the fastest development tool Xilinx System Generator or Xilinx ISE.
Thank ...
1
vote
2answers
320 views
System Generator: How to configure the pins for the signals of your design?
I am programming a FPGA by System Generator. I have done this design:
I don´t know what are the respectives pins of my FPGA for the blocks of my design called 'Gateway In' and 'Gateway Out'. I would ...
1
vote
1answer
438 views
System Generator: How to generate a .bit file?
I am using System Generator and I would like to generate a .bit file in order to load into my FPGA. Does anyone know how to generate a .bit file with SG?
Thank you.
1
vote
1answer
738 views
System Generator: How to configure the CORDIC divider block. Understanding the block parameters
I have some dudes about the block parameters of the CORDIC DIVIDER.
I would like to someone explain me the parameter called "Latency for each processing element".
(See the parameters inside the red ...
1
vote
1answer
587 views
System Generator: How to configure the CORDIC divider block?
He all, I was wondering how should be the parameters fo the CORDIC divider block in order to get proper results.
In this example I´m trying to get 0.1/0.2 = 0.5 but I don´t get it and I don´t know ...
