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Speaking about the general case, IR explains how gate series resistance can be important for controlling turn on time. http://irf.custhelp.com/app/answers/detail/a_id/215


The 50mA draw indicates that the chip has been damaged, and ESD is a likely cause, or trigger, for such damage. A damaged chip could exhibit strange behavior as you indicate, perhaps because of power supply bypassing that is insufficient for such a high fault current (it's possible that if you shunted the 100nF cap with 1000uF it would appear to work ...


It's all about the total resistance. In most cases, that is probably dominated by the resistance of the switch, but ESR (equivalent series resistance) of the cap can also be significant. The resistance of the switch is the resistance of the two FETs in series in your top diagram. All else being equal, that should be higher than that of the single FET in ...

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