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1

Here is an awfully incomplete answer : By doping, oxyding, metallising a slice of sillicon, you can create on the surface several types of components : wires, bipolar transistors (aka BJT), metal-oxyde transistors (aka MOS), resistors, inductors, capacitors... (but it is often easier to create a transistor than these passive components). Components are ...


4

Each logic family has different circuits for the same function (e.g. an AND gate), since each was an advance on earlier technology. The earliest logic families used bipolar junction transistors. Some examples are: RTL (1963) - resistor transistor logic (used in the Apollo Guidance Computer) DTL (1962) - diode transistor logic (used in the Minuteman II ...


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TTL logic uses bipolar transistors and CMOS logic uses, well, CMOS transistors. The structure of gates is also quite different between the two since the two types of transistors are so different and therefore need to be used differently.


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Here is a (slightly dated) paper that discusses the differences: http://www.ece.neu.edu/faculty/ybk/publication/ASSESSING_MERDRAM_ELSEVIER.pdf Basically, it boils down to a few important differences. Leakage current. The pass transistors for the DRAM cells must be extremely low leakage, otherwise the leakage current will affect the bit stored in the ...


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It might be easier to see this with an example. Let's take a look at the CD4001/CD4011 gates which are NOR or NAND gates respectively. Here is the internal schematic of a single NOR gate and a single NAND gate from the datasheet: You can ignore the four transistors that form the buffer for the output: Now for the NOR gate you can see that there are ...


2

It's actually quite simple, and it's based on two requirements: Every node in the signal path must be connected to either Vcc or GND, to be at logical level 1 or 0 respectively; There should never exist a conductive path between Vcc and GND, else it will short the supply and start draining a lot of current and possibly burning some parts here and there. ...


0

In general, CMOS inverters won't be able to source 3A. As Wouter van Oeijen stated, an H-Bridge is what you want. The princicple of operation is shown below. As shown, S_B1 and S_B2 are closed, causing a current flow from right to left. When you instead close the A-Switches, the current is reversed. When you want no current at all, open all switches. In ...


0

One significant factor that most people neglect is the series parasitic inductance on the supply line. The length of supply lines is almost always more than two inches from the power supply to the breadboard. That means a huge parasitic series inductance for 16MHz. I suggest fitting a 10nF to 100nF ceramic capacitor next to the hole of pin 16 and pin 8 ...


1

(answering from the comments) You could use a slower, inexpensive oscillator as your base clock, then use a PLL in the FPGA to generate various internal clocks at higher, lower or equal frequencies for use in your design. The functionality of the PLL's that are available to your design will depend on the type of FPGA; by way of example (modern) Xilinx ...


1

UCLA apparently offers an undergrad program in semiconductor process engineering. You could suss out the course materials. See this and this. If you have access to the manuals for the expensive equipment used, you've got an advantage already. Note that it's offered by the chemical engineering faculty, and the electronics content is pretty minimal.


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From the original post: "On the other hand, NMOS shares a common substrate, so if you were to connect the source and bulk, you will have to do so for all NMOS." However, I still don't see the reason doing this in NMOS will cause any problems at all. The reason this causes problems in a bulk process is that all the NMOS devices' "wells" (or ...


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Regarding the split in the diagrams, ST has separated the crystal equivalent circuit from the load capacitors with which it resonates, whereas TI have chosen to keep all the resonant components together for their description. As LvW points out, the circuit needs a resistance in the gate output to raise the "amplifier's" output impedance. Logic gates with ...


1

Perhaps looking at it another way, a traditional bulk CMOS process is built on a P-type wafer. This allows NFETs to be built directly in the substrate without "extra" steps. To get PFETs in the same circuit, they need to add N-type wells to the substrate. Since this well is an added feature, you can place it wherever you want. It forms a diode to the ...


2

Diverger - I think some confusion can arise because there are always two different ways to explain the functioning of oscillator circuits (models). Normally, we discriminate between two-pole and four-pole oscillators - however, it is important to know that this is nothing else than a different way to describe the oscillation principle. a) Two-pole ...


1

It works when the source is at the same potential as the substrate. But not all NMOS transistors will have their sources connected to the substrate. Sometimes they are put in series, where the lowest one is connected to the substrate, and then the drain is shared with the source of the next transistor and so on. It's also possible to use an NMOS in a ...


0

If you connect the input and output of a CMOS inverter, both the PMOS and NMOS FETs will be drawing current, and the exact voltage it stabilizes at is determined by the relative "strengths" (or current gains, really) of the FETs. It's not necessarily half-supply, but typically it's close. The output voltage stabilizes at the point where the current through ...


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The diodes in a MOSFET are from the source to the bulk and from the drain to the bulk (often called source/drain diodes for short). These are not really part of the ideal MOS transistor structure. Rather, these are parasitic devices that are not helpful to MOS operation, and they exist in all "bulk" CMOS processes. They add undesired parasitic capacitance ...


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The Diodes are forming from p- to both n+ Areas. The Gate contact is connected via the gate capacitor to the middle of the diodes in this model.


1

Logic gates like AND, OR, NOT, and so on are not discretised in time, they don't handle time in steps. At every moment they reflect the input at some earlier moment (a few nanoseconds ago, usually). For various reasons signals can get delayed for a tiny moment of time (line length, capacitance, etc), and as a result for similarly tiny lengths of time your ...


1

@sanjay: A standard CMOS NAND gate has two PMOS devices in parallel to pull the output (to supply) and two series NAND gates to pull the output down (to ground). If either input is zero, then at least one PMOS is on pulling the output up and at least one of the series NMOS FETs is off preventing the output from pulling down. So the output will not "lose ...


1

With the output of a CMOS inverting gate connected to its input through a resistor, a rising output voltage driving the input past a certain point of equilibrium will cause the output to servo its voltage down until the input gets to that happy point. Conversely, if the output voltage falls below that point it'll be servoed up until the input rises to the ...


2

Diverger - I recommend to study the V(in)-V(out) transfer characteristic to be found in the relevant CMOS data sheets. As you will see - the output voltage will be at Vdd/2 in case the input also is Vdd/2. Because the transfer curve of the inverter has a negative slope (rising input causes falling output) you can find a stable operating point at ...


1

Consider a simple CMOS inverter composed of one n-channel MOSFET and one p-channel MOSFET: With feedback IN and OUT are connected through a resistor. Suppose IN is at about 0V. The p-channel MOSFET is on and the n-channel MOSFET is off, so the voltage at OUT is high (at \$V_{DD}\$). Due to the feedback resistor current flows from OUT to IN and charges up ...


0

An inverter is just a rather nonlinear amplifier. It is possible to use 'digital' inverters to build some simple analog circuits. Generally, the initial oscillation of a crystal oscillator will be very small, much too small to get to the logic-level threshold of the open-loop amplifier. So adding some feedback allows the small signal to be amplified and ...



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