New answers tagged cmos
at Lg ~< 10 nm Still some solutions exist like: http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6523122
In most (all?) cases there is some company-internal policy that determine the manner in which both the stem (74, Atmega, PIC16F, CD40, ....) and the suffix (00, 04, etc) are derived. Often they make little or no sense without the internal structure of the company. Once a company-specific type has gained widespread use and other vendors make it too, it might ...
Your logic looks like a sum of products (ANDs feeding into an OR). In that case, you can replace both the ANDs and the OR with NAND gates. Also, you can replace (~a ~c) with ~(a + c), which saves a gate. Putting it together, that gives 1 NOR, 1 NOT, and 2 NAND, for a total of 14 transistors.
Use a pulldown resistor connected to ground that results in a current that is less than the drive from the previous stage but more than the input requirement for the next stage.
3rd one doesn't work as XOR. Look at case A=0, B=0: Upper right MOSFET (p-channel) is turned ON. This yields 1 at the output which is wrong. Also look at case A=0, B=1: Upper left MOSFET (p-channel) is turned ON, which makes source of lower right MOSFET (n-channel) high. Gate of lower right MOSFET (n-channel) is high but its source is also high. N-channel ...
The table is trying to summarize information that would really best be shown as a graph. If you draw 0.51mA or less at a temperature of 25C or below [the "min" column], the part is guaranteed to output at least 4.6 volts; if you draw 1.6mA or less, it will output at least 2.5 volts. Note that the causal relationship implied by the table is that if you need ...
The specification is letting you know how much current the output can provide. With a 4.6 volt output the maximum current that can be drawn at room temperature is 1 ma. If you try to draw more current the output voltage will drop. At an output voltage of 2.5 volts, the maximum current that can be drawn, again at room temperature, is 3.2 ma.
I take it that the delay line in the upper box labeled "tracking logic and safety margin delay" somehow models the delay in the "combinational logic" block in the lower box. At equilibrium, the output of the "timing checker" flip-flop will be a 50-50 mix of ones and zeros. BTW, this should be at least two flip-flops, since the D input needs to be treated as ...
You are probably correct about why you're always seeing a "1" on the display on power up. As C3 is charging, the Schmitt Trigger U2A will see it as a low voltage until the voltage on C3 exceeds U2A's minimum threshold. With such a large value for R1, it takes a long time to charge up C3. I'm assuming the pendulum is relatively slow if you're using such a low ...
If I understand correctly your aim is to have falling slope of inverters appear later than rising slope? If so, if it is available reduce W/L ratio of NMOS transistor and increase W/L ratio of PMOS transistor. Capacitances on the output are seen both by NMOS and PMOS transistors.
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