New answers tagged cmos
If you're stuck with a 555, this should work for you: I don't have an LMC555 model, so I worked it out with a bipolar 555 and got less than 10nA of quiescent current between pulses. You should do better with the CMOS 555. I picked the MOSFETs semi-randomly from the LTspice library, so you may want to pick something else which may be more appropriate ...
The main problem I see is that you want the trigger input to be higher than the V+ input when the LMC555 is off, and that violates this requirement: It's there because there is a diode-like structure inside the chip from each input to V+, for input protection. You are forward biasing that diode, and drawing a relatively high current. Since you are ...
For the third question, propagation delay and transition time gives you the maximum frequency at which the circuit can operate. The clock period must be long enough to allow for the longest path of a signal between flip flops, which includes propagation delay of each logic gate along the path. Such a path is referred to as a critical path(in reference to ...
It would seem there is a simulator called NEMO5 I will also link in the paper which called this out... https://www.e3s-center.org/pubs/187/Huang_David.pdf
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