New answers tagged cmos
A PMOS can be used as a pull-down device, but it isn't because of its poor performance. In books like Rabaey Digital Integrated Circuits they refer to this phenomena as the PMOS passing a strong 1 but a weak 0. The reason behind this is the regions of operation during pull-up and pull-down. To synthesize: Pull-up The PMOS is mostly in linear region ...
This answer assumes that the P channel device is connected like this: - Source connected to the "high" voltage Drain connected to ground/0V Gate used to control the device. It can be used to pull a "high" (rating dependent) voltage to ground/0V but to do so requires that the gate voltage be BOTH taken below 0V AND constrained to be within about 15V of ...
I've never done this, but here's how I would start: find the data sheet for the camera. If none available, I would find the most similar part with a datasheet available and start with that and learn all you can. for this camera, make an interposing board with male and female of the camera connectors, and breakouts for a logic analyzer. capture waveforms ...
If a small delay between switching is acceptable, you can easily insert these with minimal parts. This is sometimes called "dead-time insertion" or "dead-time generator", something along those lines. There are tons of variants out there. This is one of the most common I see around: Uses a RC time constant to achieve the delay: You can find a few more on ...
The usual way to solve this (AFAIK) is to make sure Vctrl switches very quickly so that the transition time is very short and not much heat can be generated during the transition. Since you have a simulation model of your FETs, you should be able to check this. Simply drive Vctrl with a ramped edge, and measure the transient current through the switches. ...
What you want is a "break before make" circuit. You can do this with some logic gates but since you're using a controller, maybe you have an extra output available ? If so, I would control both FETs separately, switching one off before switching on the other one, perhaps with a small timedelay in between. Problem solved :-)
The two MOSFETs are drawn incorrectly in the question's picture. That is why you are confused. This is how they should be i.e. sources tied together: - I'm not aware that there is a decent non-isolated gate-drive version.
While I can't be sure, since you have provided no context or links to the original source, I would guess that this is part of a discussion on how to quantify 3 terms: input high, input low, and mid-voltage. What the author seems to have done is to take the position that, for a logic circuit, there will be input/output high and low regimes, where changing ...
Another trick/workaround are finFETs, by moving from a planar device to a "3d" structure leakage in "off" state is reduced while maintaining small device size (in the planar direction anyway), see: http://www.newelectronics.co.uk/electronics-technology/what-makes-finfets-so-compelling/56795/
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