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3

This is a typo. The not in the Note (as transistor points out) should not be there. Then it makes sense. Be sure to tie off any unused input, but unused outputs are fine. Line in TI article, Designing with Logic, Note: Unused outputs of a device should not be left unconnected (open). The title of the section where this line is referenced is: ...


2

I would try to connect 10 buffers to the data source and then 10 74HC574 inputs to each buffer output. Think about a rack with a data bus to ten boards, each board has its own buffer for its internal data bus driving ten 74HC574. No problem with current and capacitance limits. Just avoid a common data bus to hundred HC574. It is possible to drive even a ...


2

A weak transistor is one that has lower current \$ I_{ds,sat}\$ relative to others in the circuit. This is done primarily with a lower \$ \frac{W}{L} \$ although in most digital processes you don't change the L so much, so that means that the W must be smaller than those other transistors. In this circuit these weak transistors are being used as bus ...


4

A "weak" transistor has a lower transconductance, which could be done by making something longer, current starved or a threshold implant. I would encourage you to avoid "weak" transistors for a few reasons: we really cannot use them on aggressive processes due to doping spacing you cannot just make "Long" devices because it moves the threshold toward the ...


5

I'm pretty sure they mean a transitor that is designed to have a deliberately high on resistance. This allows other transistors to overpower it.


2

Yes actually, there are a plethora of different designs of FF's at the transistor level. One of my favorites are known as TSPC (True Single Phase Clock) FF's and I can recommend an excellent paper " Yuan, J., & Svensson, C. (1997). New single-clock CMOS latches and flipflops with improved speed and power savings. Solid-State Circuits, IEEE Journal of, ...


1

In your NMOS case the voltage source is mentioned correctly with the total current but in the second PMOS image it does not match. And also the Vgs of both should not be same because for the PMOS Vsg refers to a positive threshold. Try this, connect the ground that is in your image which is connected on top(source) to the bottom which is the drain (Symbols ...


0

I'm not quite sure you're looking at this the right way, but anyway: P- and N-Channel MOSFETs are different in how the respective semiconductor need to be doted and sized for the same current. Due to that physical difference, device of the same dimensions but different channel type will be able to carry a different current.


0

BCL and BCP and BD are just referring to casing. So all three are the same.



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