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As others have stated: the behaviour of the FF after power up is not random at all. The behaviour is neither completely determinstic (considering the factors you have under control), but being not completely deterministic doesn't mean it can be used as a good random generator. In this context a story concerning the state of FFs after power off: I remember ...


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They don't use that concept because, unfortunately, it doesn't work-- the start-up state of a FF won't be very random at all. Quoting from "Cryptographic Hardware and Embedded Systems -- CHES 2003: 5th International Workshop Volume 5" Making a truly random number generator is not easy.


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This problem has already been solved. Thermal radiation is not perfectly uniform, and fluctuates rapidly at extremely small scales. Sample a space with enough precision and you have your RNG: http://www.newscientist.com/article/dn6289-prize-draw-uses-heat-for-random-numbers.html Intel beat you too it buddy. Hope you didn't pay the patent fee already... :P


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As you may have gathered from the other responses, this is generally not a trivial exercise. At the individual component level, each manufacturer publishes a datasheet that lists, among many other things, the max and min supply voltages and the expected current for at least one recommended supply voltage. Add up all the components on the same internal ...


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A computer is a very complex beast, with power management circuits that control the amount of power being fed to various subsystems. A laptop computer is designed to limit the amount of power it consumes. That is both to reduce the drain on it's battery and to not exceed the heat dissipation limits of the device. A laptop has one or more voltage ...


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The computer was probably designed with a power budget of 60 watts. Most of this is consumed by the CPU, GPU, screen, and battery charger. They also decided that the input voltage from the adapter would be 16.5 volts, requiring 60W/16.5V ~= 3.65 amps. The power draw of the components can be measured under full load to ensure the power budget is met.


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Whether you need a transistor buffer or not will depend on the current capability of the IOIO-OTG board, and the current requirements of your motor. A quick look through some of the IOIO_OTG documentation didn't reveal any IO current spec, but a photo of the board just shows one chip - presumably the PIC microcontroller, so I would assume the board can only ...


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Here's a circuit that'll do everything you asked for:


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You should look at the 40xx CMOS series. Wikipedia has a good list: http://en.wikipedia.org/wiki/List_of_4000_series_integrated_circuits You also should inform yourself what you have to consider using cmos devices in real life (what to do with open pins, additional capacitors, what means open drain, output current and so on...) Some important ...


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Altium is releasing a new free PCB design tool: http://circuitmaker.com/


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I found the Molex 5569 library you're using. Whoever made this library did something very odd. For each square through-hole pad, they also added a co-centric hole on top of it. So there's a pad and a hole in the same spot for every pin. Eagle is programmed to isolate pours away from holes, which is why you're getting an isolation circle around each square ...


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I've designed over a dozen FPGA based boards that employed a wide range of different types of FPGAs from low power Lattice Mach X02s to high performance Virtex 6's with 24 SERDES channels. The normal steps I follow are: Find a COTs board (similar to MarkU) and get a rough idea of the internal FPGA resources you will need, in particular I pay attention to: ...


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The ER341245 data sheet says it can supply 450mA continuous, and 1000mA pulse. So it does not look like a capacitor is needed to protect it from damage by a 60mA peak. According to the data sheet the battery capacity is quite sensitive to the discharge rate, so trying to smooth out the discharge rate might have some benefit. "peak last 25ms and its ...


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With only simple logic gates, you're going to be "putting a crazy amount of them" on the four MSBs. Optimizing your logic can help reduce the number of gates (there are two that start with 11, so they can share some gates, for a start). However, if you were to spend a few pence and invest in a 74xx154 4-to-16 decoder then the 16 possible combinations of ...


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In principle it is ok but it does suffer from shoot-through's during PWM transitions. This is compounded by the fact that P-TYPES switch slowed than N-TYPES. Depending on how much current you plan to draw through the MOSFET's you could simply solves this by putting a diode-resistor pair in parallel with the already present gate-resistor (while possibly ...


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Single-transistor BJT amplifiers won't come up trumps for all the "rules" you have written at any frequency. For instance, you require an amplifier so I'm assuming you want voltage amplification. OK so far? The collector delivers a current output signal and not a voltage signal. This means that this current signal only becomes a sensible voltage signal ...


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At my company, we've previously designed some custom FPGA boards, and have recently started using commercial off-the-shelf ("COTS") FPGA boards with custom FMC daughterboards. Prototype stage If you're still in the early project definition stage, plan on buying at least one COTS FPGA board for prototyping. You can wire up one of your sensors to the I/O ...


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I think a good starting point for a custom PCB equipped with a FPGA will be the reference design boards from the FPGA vendor. You can inspect these designs for example for the power supply, but be aware that reference design boards are sometimes undersized. We had many trouble with Xilinx ML605 boards loosing there configuration, because of an undersized ...



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