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The next variable always covers the half section that you add when you mirror the table.


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I know you asked this a while ago, but in case you still need the answer, yes it is possible. According to http://www.cburch.com/logisim/docs/2.1.0/guide/menu/edit.html "Note: Logisim's clipboard is maintained separately from the clipboard for the overall system; as a result, cut/copy/paste will not work across different applications, even including other ...


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From the data sheet the highest voltage on a GPIO is 3.8V. So If I have 5 Volts going through a.... lets say 1M resistor to the 3.3V input pin is this ok? The datasheet DOES explicitly cover the situation by stating an absolute maximum voltage. Above that voltage damage MAY occur. If the IC is operating mis-operation may occur. Or may not. ...


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Static-1 Hazard: the output is currently 1 and after the inputs change, the output momentarily changes to 0 before settling on 1. Now consider the circuit. Assume that all the 2-input NAND gates have a delay of \$\delta_1\$ seconds and 3-input NAND gates have a delay of \$\delta_2\$ seconds (\$\delta_1 > \delta_2\$). Let the initial input be ...


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EEPROM Data degredation My first call here would be to move to a EPROM, even without a window. They're much more sturdy than EEPROM or flash. Failing that, see if you can get one of Atmel's space grade EEPROMs, which will likely be more resistant to all sorts of things. Electrolytic capacitor lifetime Start with a good capacitor in the first ...


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Delays such as "wait for" and "after" are not synthesizable. That said, they way you separate the input and output datapath seems wierd. I would do something like this: -- -- 74153 implementation -- Dual 4-Line to 1-Line -- library ieee; use ieee.std_logic_1164.all; entity TTL_74153 is port( c0, c1, c2, c3: in std_logic_vector(1 downto ...


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Using the function to_integer in ieee.numeric_std package, the logic part can be reduced further. I think the correct way to model propagation delay in VHDL is by using the transport delay model. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity TTL_74153 is port( c0, c1: in std_logic_vector(3 downto 0); sel, g: in ...


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You're at university and studying (presumably) to be an engineer. As an engineer you should understand how things work at a low level. In order to achieve this you need to strip away layers of abstraction, not add them. For this reason, my advice is that you don't use SystemC for this project. You may end up using it in your professional career, but ...


2

That sounds like the Bessel filter: In electronics and signal processing, a Bessel filter is a type of analog linear filter with a maximally flat group/phase delay (maximally linear phase response), which preserves the wave shape of filtered signals in the passband. Bessel filters are often used in audio crossover systems.


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The given function belongs to a third-order lowpass. The circuit as shown realizes a first-order function only. I recommend to do the following: Because the given function has only REAL poles, you can find a corresponding realization based on a simple series connection of first-order circuits (without any feedback, but with buffering between the three ...


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Well you have three poles in your equation and one reactive element in your circuit, so you need two more caps. Also, I'd refer to Ron Mancini's "Op Amps for Everyone" for reference on op-amp circuit design. Available for free here: ...


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Point nr.1 circuit won't work, you have problems in the output stage. Point nr.2 (top): L+ is always zero (actually noise) Point nr.4: does nothing. You should simulate the circuits. EDIT: circuit 1 was corrected, but I would not use a FET unless it is a logic level FET. In this case loose the bipolar and find a strong enough logic level FET and drive ...


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I have often used keynote (you may also choose to use PowerPoint). This has the advantage of allowing screen caps of simulation software such SPICE GUIs and such. Really key for me is the ability to drop in snippets from data sheets and mark them up so the relative importances in my design decisions show up. I can also include photos of early circuit ...


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I keep a design notebook, and carefully document needs/wants. For the earliest prototypes, I'll go through part selection, taking notes on all the real decisions. For subsequent changes, I use a fairly formal FMEA process, documenting which need is not being met so as to justify a change -- because obviously, if there is no unmet need, there's no need for ...


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For many of my smaller projects, I've generally been placing a simple green label and border around sub-circuits. For larger projects, some eCAD software allows you to build from a block diagram down, where each sheet further describes a single block. There's an art to decomposing any problem, and managing the tradeoffs (that's engineering IMHO). Where ...


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I personally go the old-fashioned route: I have a design notebook where I write down absolutely everything about the design decisions I make. Especially component and value choices, current calculations, power supply calculations, everything. I also document software/firmware decisions and notes on timing and resource usage. Each notebook has a contents ...


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I do a lot of quick-turn design and I have to say: annotating the schematic is by far the most convenient thing. It's rare for any of my designs to be more than 2 or 3 A4 sheets, so the amount of design decisions is limited. A lot of design decisions are pretty much automatic; I don't need to list reasons for every single part. Just one or two main parts and ...


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You could go back and update the design spec with this information. Or take the spec and create a lower level spec where you describe in more detail what you are going to do and why, ideally before you start schematics :). Then update as you go along and archive with the schematics. Answering questions below: Well what we usually do is start with ...


2

You've got a number of problems, and I'm not sure which one of them is biting you on the butt. 1) You don't show the entire connection for the TL431, but I assume that you've tied the reference input to the cathode so as to get 2.5 volts. Please check the data sheet http://www.ti.com/lit/ds/symlink/tl431.pdf, figure 17. You must get rid of C1. 2) The fact ...


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http://www.tij.co.jp/jp/lit/an/slyt202/slyt202.pdf Using the formula $$PSRR = 20 \log \frac{Input ripple}{Output ripple}$$ I get 20 log 3000 ~= 70db. Which is exactly what the later graph shows as an example rejection ratio. So your regulator seems to have exactly normal performance here.


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The best way to do this in Altium is to use Net Ties. These will join two separate nets. See: https://www.smtnet.com/library/files/upload/NetTies-and-How-to-Use-Them.pdf I will also occasionally use zero-ohm resistors to accomplish the same goal if there is a chance that I may need to break the connection to help troubleshoot an issue.


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Once you start incorporating specific primitives into your design, that design is no longer portable — it is locked into the technology in which those primitives appear. In order to simulate such a design, you need to have the manufacturer's simulation library for those primitives. Such libraries are often delivered as encrypted binary files, in order ...


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For the most part, the synthesizer is good at inferring primitives. However, there are primitives that cannot be inferred. Sometimes it as simple as a dual port RAM with different port widths or a FIFO with no extra fabric logic. There are also things like DCMs and PLLs for generating and managing clocks that can't be inferred with pure HDL. FPGAs in many ...



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