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There are two transients to consider: High dV/dt: these occur on the switching node (emitter of high-side IGBT and collector of low-side IGBT), each time you switch either IGBT. A high dV/dt can couple to neighboring traces capacitively. If the neighboring trace terminates to a high impedance node (eg. the input to a comparator for current sensing), the ...


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You question regards basic signal integrity principles. You will want to avoid sending tracks through vias as much as possible since as frequency increases, vias will cause reflects on the traces which will introduce an new noise source. The only one I would say is okay to send through vias is the connections to the GND plane and connections going to a ...


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What your trying to do here is build two filters, one high pass, and one low pass. Horizontal inductors shunted to ground with caps, create a low pass filter. When the caps are horizontal and the inductors got to ground, you have a high pass filter. If you want to analyize this in detail you need to learn how to use a technique called ABCD matricies. ...


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The smallest, cheapest, most reliable solution will use a small, 6-pin microcontroller: VCC, GND, input, output, with two pins left to spare. If you're not after necessarily smallest nor the cheapest, but are after low-tech, then a double 555 (say LMC556/TLC556) would do: one half would act as a toggle F-F, another one as a PWM generator, using the input ...


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There's one important thing that everyone forgets: more modern logic families might have the same logic levels, but they can switch much faster than old logic families. If your board is not designed to cope with such fast switching, it will either completely stop working, or will work erratically, once you start swapping out old chips for newer, faster ...


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I'll assume you're talking about 'glue logic' and you're not trying to build a CPU out of logic chips. I think you're better off using popular types of HC CMOS chips since they'll likely still be available in some years. 4000-series CMOS is too slow when operated from low voltage, and LS TTL is becoming rare, has lower fan-in and requires that you use HCT ...


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A few arguments: with HC and HCT, the fan-out (at lower frequencies) is essentially unlimited, for LS it s IIRC 10 (or was it 20)? the HC and HCT families are newer than LS, so my bet would be that they will be around longer than LS HC and HCT use much less current than LS (except maybe for a few gates that switch at a very high frequency), which eases the ...


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The practical FPGA register (a set of D flip-flops) only has one clock pin so it serves exactly one clock domain. Keep this low-level hardware in mind when writing HDL code. When a signal crosses from one clock domain into another, it's common to use a pipeline of three registers, with the first stage in the source clock domain and the second and third ...


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I would not represent each floor as a separate state. States are associated with a set of behavior which is different from the behavior of other states. Generally, a lift does not behave differently at floor 1 versus floor 2. So I don't think floors make good states. I would start with three states: Idle, Loading, and Moving. The Idle state is when ...


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You're confusing the floor destinations with the states. They are not the same. For a lift, states would be: Idle Moving up Moving down The states would be changed by events such as: Call button pressed Floor button pressed Arrived at target floor The FSM doesn't care about what floor is what, only which floor it wants to get to when in a moving ...


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Theory is great, but by stacking many layers of aluminium, you are introducing some unknown factors. (What is the thermal resistance form one (oxidized?) plate to another??? I suggest you test the cooling capabilities of your creation. For example, Bolt a component to it (transistor / regulator) Make it dissipate a known amount off watts. and measure the ...


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There is no real difference between the formulas for designing a toroidal transformer vs. an E-I transformer. The core cross-sectional area is \$\pi r^2\$ rather than the L \$\times\$ W of the center post, but the exact shape of the core does not matter much. You'll need the core volume calculation for losses, but that's a straightforward lookup of a ...


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Here's a free one that I haven't seen mentioned that is pretty nice for simple layouts: ngspice My company primarily works with PADS and Eagle, so +1 on recommendations for those. However, as mentioned, not free! Fritzing and Diptrace are both worthwhile to take a look at.


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Dual gate MOSFETs (tetrodes) have characteristics that make them very suitable for RF mixers. Typically RF is applied to G1 the first gate, and local oscillator is applied to G2. This maintains good isolation between oscillator and RF circuits, and low third order intermodulation (by which strong signals can wipe out nearby weak signals) While just about ...


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You can get pretty much any transistor acting as an RF mixer (aka 2-quadrant multiplier) you've just got to bias it in the correct region (low collector voltage to the left of the following diagram): - Why is it important to use this area as a mixer - here's a closer look at a JFET: - This is a JFET's response because it is diagrammatically easier to ...



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