# Tag Info

2

In the case of a circuit containing a device with a power on reset mechanism, too much capacitance on the VCC (or power input pin) can cause the voltage at the power pin to rise too slow to meet the devices dV/dT requirement. This is sometimes remedied by adding an RC network at the devices 'RESET' pin to allow the Reset pin to stay active long enough to ...

2

The trouble with too much decoupling capacitors is that if the layout is bad, i.e. high trace inductance all the decoupling capacitors in the world won't help. So you might actually never realize you have a decoupling issue, because you think it can not be the decoupling...

0

Ultimately I think the question is flawed. And I do NOT get close to any answer. Hard to get 22k saved from 32K, when nanocode takes up 14.4K. From 1. In some cases, such as the Motorola 68000, there is also a nanocode engine. The 68000 uses 544 17-bit words in its microengine and 336 68-bit words in its nanocode engine. It thus has 32,096 bits of ...

1

Absolutely, it is done all the time in practice, especially when you want a device in triode. I use it regularly in bias circuits or comparator preamps with triode loads. From a practical standpoint, if you want to use a really long device, you shouldn't have the width at minimum but it is usually better to have it closer to 2x or 3x minimum.

4

He's talking about biasing a diode with a voltage source. simulate this circuit – Schematic created using CircuitLab I've taken the liberty of adding C2 since the output will have some offset, and left out his "tweaks". The threshold will depend on the ratio of currents between the two diodes. The current through D2 will obviously be less so ...

3

Schottky diode- a hefty one such as this. The 1N914 can't conduct enough current to protect the MOSFETs. There are cheaper 10A ones- do a parametric search. But it would be nicer to use a series MOSFET (or a unipolar TVS and a polyfuse) and protect the product against reverse voltage. Every customer who has a warranty claim denied is a potential source of ...

1

The 1N914 has fairly high voltage drop at high current (~1.4V at 800mA) so it probably won't keep the reverse voltage down low enough to prevent damage to other devices. I would replace replace D1 with a Schottky type (eg. PMEG2010) which should conduct at lower voltage and higher current than the devices needing protection. You could combine this with a ...

0

How about a large fuse in series with the power supply input? If they blow that fuse, then they did something bad. I would go with a surface-mount fuse that is sized not to blow until the FETs are about destroyed.

2

I have drawn your circuit in LTSpice and could not get it to work at all. I replaced Q1 and R1 with a voltage source and a simulation DC sweep. Your first OP07 stage has no supply, I added that but the OP model seem flawed. I replaced it with a LTC7652 provided in LTSpice. I don't understand the point of R2 (please enlighten me!) so I removed that. I'm ...

1

This is a simplified explanation, however it should help explain why the cold sink is smaller than the heat sink: A peltier cooler pumps heat from the cold side to the hot side, and in addition a peltier cooler generates heat in addition to the heat its pumping. A peltier unit's Qmax (the amount of Watts it can pump) is rated at zero delta T (the ...

0

The size of a combinatorial circuit is a function of its input. The more input a circuit can use in figuring its output, the larger the circuit must be. Suppose, for example, one needed to design a circuit that would determine whether an input had an even or odd number of rising edges within the last second, if every high and low time was guaranteed to be ...

-2

Here is a design platform. Freeware. http://opencircuitdesign.com/magic/ Here are 3 CCD specimen source files. Magic compatible. http://www.filewatcher.com/p/magic-doc-8.0.60-4.fc18.x86_64.rpm.784608/usr/share/doc/magic-doc-8.0.60/scmos/examples/ccd-0.htm Here is a simulation environment. Freeware & compatible with those specimen. ...

0

Any realtime system using digital filters or controllers will necessarily require memory elements fulfilling the delay requirements of discrete-time difference equations. Batch data that could theoretically provide all relevant input data, is not available in realtime systems. In a control system you usually at least require an Integrator which requires a ...

1

If you have some set of boolean inputs S, and some function f that maps S to a set of boolean outputs R, then yes: any f can be represented with pure combinational logic, and you can derive which logic you need from the Karnaugh map etc. The process of filling in the Karnaugh map may be difficult: you're manually pre-computing all the answers. This has two ...

0

All digital problems that are inherently combinatorial can be solved using combinatorial logic. For example AES-encryption would normally be done using sequential logic, but it could theoretically be done combinatorially provided you had all the available inputs ready simultaneously, and unrolled all the loops by duplicating logic. Of course, it'd be ...

0

Sequential logic was developed out of a necessity to be able to accurately predict when a certain value or set of values was in a certain place, so that other logic could decide to then do something with that information. Many logical problems can be resolved using only combinational logic, but a problem arises when you need to use the output of one function ...

1

$r_o>5\rm{k\Omega}$ is the condition that sets the length of the transistors. It is desired for the PMOS current source and the NMOS current sink to have an output impedance $r_o\geq 5\rm{k\Omega}$. Knowing that $I_D$ is 50 or 100μA, $$\frac{\Delta V_{DS}}{\Delta I_D} = r_o = \frac{1}{\lambda I_D}$$ Thus, for the PMOS, \lambda = ...

0

Ro is the inverse of the slope of your Id vs. Vds curve. You're right, it only really matters for P2 and N@. Do you know the lambda (channel-length modulation) for your technology? If you do, ro = 1 /( lamdba *Id ). if you don't know lambda you can start with small L (minimum is a good place to start) and then increase L based on simulation results. You ...

2

Your friend either misunderstood what you are doing or was thinking of SystemC as a preliminary step. An HDL is the only choice In any case, and I would suggest you use synthesizable SystemVerilog that is powerful enough to do a lot of exploration whole being essentially the same as Verilog for everything else. Partially. You distinguished between Verilog ...

2

Add a pair of resistors to the end of the lines. One up to VCC and the other to ground. This will allow you to terminate the line at the end in addition to (or instead of) source termination. The problem with source termination is it works best with only one endpoint and you have many. The intermediate points will see a step on the edges, the placement of ...

3

What you want to do is not possible. The datasheet shows the ULN2003A to have open collector outputs. That means it only switches between open and actively driven low. Open is the same as disconnected. Your circuit therefore can't tell the difference between open and disconnected. To make this work, you need the off state to be when the ULN is open, and ...

2

Here's a slightly different approach- simulate this circuit – Schematic created using CircuitLab Whenever the input signal exceeds the reference (shown as 200mV) the input is assumed to be 'high' and the capacitor C2 charges or discharges towards 1/2 the input signal with a time constant of 5msec through the CMOS HC4066 switch. U1B acts as a ...

3

As has been implied in comments, if there is a digital 1 or zero event for some lengthy period of time any peak measurement made will need to rely on analogue values being held on a capacitor and no, there is no way of passively achieving this. I have previously done this by using "peaks detectors" (an opamp with diode and capacitor) for "storing" the most ...

0

Some of the previous answers overlook the most obvious: Check the solder joints for the button, resistors, capacitors and the uC. Under microscope you may be able to see a cracked solder joint. If you don't have a microscope, re-solder one and one joint and see if it cures the problem.

0

Generally with an RF application, you want to tune higher or lower than the frequency you are trying to broadcast. Th surrounding material attenuation then matches with the proper operating frequency. In this case you can not do that, so the range will drop. I believe you will still be fine for a few feet of range after looking at the datasheet and seeing ...

1

As its most likely a homework/class problem I'll take you through the process and let you finish it off. For a silicon transistor the base voltage (Vb) will be about 0.6V higher than the emitter so if you know (or set) Ve you can write down Vb. The gain of a small signal transistor will be at least 100 so if we take the current flowing through R1 and R2 as ...

3

Drive the transformer from a low impedance. The source impedance and the transformer's primary inductance form an R-L high pass filter which determines the LF rolloff of the circuit. So with the attenuator ahead of the transformer it'll be all about the treble ... no bass.

2

That circuit is rather simplistic and a bad idea. It's clear enough how it's intended to work, but the implementation is lacking. In particular, the lack of emitter resistors in the output stage is downright irresponsible. I was going to go into detail on how this circuit works and how to tweak it, but now realize you didn't provide component designators. ...

1

In the Australian world, we use AS 1102 Graphical Symbols for Electrotechnical Documentation, which is derived from IEC 60617 Graphical Symbols for Diagrams. The following areas are covered in the database: Conductors and connecting devices Basic passive components Semiconductors and electron tubes Production and conversion of electrical ...

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