# Tag Info

24

Possible reasons: Load Balancing The driver of A has an unknown number of fan-out to drive. Fan-out within the circuit and the parasitic it induces can be calculated for the specific circuits, but we do not know the other circuits that are connected the driver. Essentially the inverters are being used as buffer equivalent. and help manage the parasitic. ...

13

Absolutely. This circuit takes advantages of the properties of a MOSFET to bidirectionally switch a signal between two different voltage levels.

12

These "hardware addressing" pins are not for addressing words in the RAM, but rather to select the address of the whole device on the IIC bus. The manufacturer realizes that you might want to have several of these chips on the same IIC bus, which means they each need a different IIC bus address. These pins allow you to pick one of 8 pre-defined addresses ...

9

This is down to Boolean algebra rather than electronics. We have for your initial circuit with inputs $A$ and $B$ and output $Q$: $$Q=\overline{\overline{A\land B}}=A\land B$$ Where $\land$ represents AND and $\overline{\cdot}$ represents NOT. So in this case you have created an AND gate. For the second circuit we have (where $\lor$ represents ...

8

You can use a third harmonic filter (inductor and capacitor) to resonate at clk*3 and then a schmitt trigger inverter (or other gate) to turn the sine wave into a decent square wave at clk*3. This works because a typical square wave has fundamental and odd harmonics in its spectrum: - The blue waveform is the output from the tuned circuit when excited by ...

8

The time required for a gate to switch is dependent upon the amount of capacitive load it must drive, the size of the transistors, and the number of transistors in series. An inverter consists of one NFET (N-channel Field Effect Transistor) and one PFET (P-channel FET); a three-input NAND gate has three PFETs in parallel and three NFETs in series. In order ...

8

ECL outputs are referenced to the most positive supply rail. This means that any noise appearing on the most positive supply rail will be directly coupled onto the output signal. For example, if the power supply is 5V and GND, then all outputs would be referenced to 5V, and any noise on the 5V supply would also be seen at the ECL outputs. Therefore, the ...

7

A microcontroller could do it very easily. Since there are only 256 possible combinations, a simple lookup table would be the fastest way. (I did the below outputting 8 for all high for consistency, you can change the last entry to 7 if you want). The code could look something like this:- unsigned char lut[256] = {0x0, 0x1, 0x1, 0x2, 0x1, 0x2, 0x2, 0x3, ...

6

If the NAND gate is made in the obvious way (three parallel transistors to GND and three series transistors to Vdd) then it will have low source capability, the transitions will not be sharp, and the delay time will be load capacitance dependent. Adding a buffer (or two to restore the logic) cleans up all those problems. Here is what a typical unbuffered ...

6

The most common way it to use a PLL based frequency multiplier. Source (www.ee.ucl.ac.uk/~pbrennan/E771/PLL.ppt‎) The Phase Locked Loop works for frequency of a signal (or more correctly -phase), like an op-amp works for Voltage. It has a high enough gain to keep the two inputs of the phase detector equal in frequency (and usually phase). Applying a ...

6

This is a simple job for a microcontroller. Spehro correctly points out that it can be accomplished with a simple lookup. If you can tolerate lower speed then counting the bits in a loop will do it too, but will take less code space. Another way is to do this in analog. Put a 100 kΩ resistor in series with each digital output, then feed that into a ...

6

There isn't really any technology that competes with FPGAs by trading off field-programmability vs cost. There are ways to lower the cost of your FPGA, though: Use the slowest speed-grade part your design can work with. Use the smallest gate-count part you can comfortably fit your design into (but it is wise in most cases to retain some unused resources to ...

6

The input is digital at 3.3V and should output 5V TTL levels. For this situation you very likely do not need any conversion circuit at all. Both 3.3 V and 5 V TTL logic switch with a threshold of about 0.8 V. Therefore no conversion circuit is needed to drive a 5 V TTL input with a 3.3 V logic signal. To be absolutely sure, check the minimum Vih of ...

5

Like this:- simulate this circuit – Schematic created using CircuitLab

5

It simply relies on the phenomenon called propagation delay. Consider the following circuit. When simulated, you'd find that it doesn't stabilize in either low or high state. It simply oscillates. If you were to probe such circuit in reality with a scope, you'd find that it's output has a somewhat fixed frequency - derived from the system's propagation ...

4

This is silly if you are just trying to communicate the logic of a chip. Probably it is drawn this way because internally there are some buffering stages. The internal gates are probably very small with little drive capability. Signals that go outside need to go thru a buffer that can source and sink much more current. Somehow this implementation detail ...

4

It's a subtle point, but your thinking is going astray when you think of a 330-Hz tone as somehow conveying 660 bits/second of information. It doesn't — and in fact, a pure tone conveys no information at all other than its presence or absence. In order transmit information through a channel, you need to be able to specify an arbitrary sequence of ...

4

The problem with having more than 2 variables in an axis is that terms that have a single bit difference are no longer adjacent to each other, which makes interpretation more difficult. This is why (2-dimensional) Karnaugh maps usually have no more than 2 variables per axis and no more than 4 variables per "slice".

3

The voltage that must be greater than $V_{TN}$ is the voltage from the gate to the source, $V_{GS}$, not just the voltage at the gate. Once the source voltage rises to $V_{DD} -V_{TN}$ the voltage from the gate to the source will just equal $V_{TN}$. Any increase in the source voltage will cause $V_{GS}$ to be less than $V_{TN}$ so current flow ...

3

"State machine" is a very generic term for any process (electronic or otherwise) whose output is not simply a function of its current inputs, but also depends on its past history. In other words, it has "memory", or internal state information. Electronic state machines started out as analogs of the mechanical state machines (including such examples as ...

3

The problem with your premise is that FPGAs are completely volatile* already. There is no special manufacturing step used to create FLASH/EEPROM, the "program" is stored directly in the Look-Up Tables (LUTs) where it is needed to perform your arbitrary logic. The LUTs consist of small SRAM arrays that are programmed, as well as some switch routing. I know ...

3

From a first look and a glance at the datasheet, generally speaking this seems fine. But the Arduino isn't exactly nippy at changing those outputs and while they are changing (with LE low), the outputs will also be changing. Could that be what you mean by "flashing" display? I'd guess that the display isn't really flashing per-se, it's just changing slowly ...

2

Technically, yes. This is how you get the NOR function: simulate this circuit – Schematic created using CircuitLab And if you can get NOR or NAND you can get any other gate. Though, since it takes two deMUXes to get a NOR, I don't know if it strictly is universal.

2

Since you only care about deviations from recent "average", what you want is a high pass filter. This also eliminates the large DC offset you have on your readings, and allows you to amplify the differences without amplifying this DC offset along with it. You have to decide how long "average" takes. In less hand waving terms, this means you have to decide ...

2

This is only a partial answer, but hopefully it gets at the main points you're misunderstanding. My problem is that I'm having a hard time understanding why bandwidth relates to bit rate at all. ... If a zero is expressed as a 30 Hz carrier frequency, a one is expressed as a 330 Hz carrier frequency, and the modulation signal is 330 Hz, then the ...

2

Assume an initial condition S = 0, R = 0, Q = 0, Q_bar = 1. (1) SR = 00 Now consider NOR1(top), inputs of this gate is R = 0, Q_bar = 1 this gives output Q = 0. at NOR2, inputs are S = 0, Q = 0 this gives output Q_bar = 1. (2) SR = 00 to 01 change occurs at R (0 to 1) at NOR1, inputs are R = 1, Q_bar = 1 this gives output Q = 0. at NOR2, inputs are ...

2

The A0 output (aka PC0) on the Atmega328 works for everyone else, so the issue is either in your software, or in what you have connected to it. To eliminate the software aspect, start with minimal code which sets the output high and leaves it there: void setup () { DDRC = 1; PORTC = 1; } void loop () { } If the flickering occurs then the issue is ...

2

The last piece you need is a multiplexer, specifically a 1-of-4 multiplexer such as the 74153. Since you have 4 inputs to the decoder you will need 2 chips at 2 multiplexers per chip. Connect the A and B inputs to S0 and S1, each of the C inputs to each of the function output bits in turn, and the Y outputs to the decoder inputs.

2

Your reference oscillator p-p voltage is a 5V logic level: - The chip is a standard 4000 series CMOS part that has voltage levels of: - You're running at 10V and the guaranteed minimum high voltage level on a 10V supply is 7.5 volts. Do you see where this might be your problem?

2

The pixel clock rate needs to be adjusted to achieve Vsync rates and Hsync rates that are acceptable for your multisync monitor. Since 40Hz is not a common Vsync rate, try 30, 50 or 60 or higher. 640*480 * 40Hz = 12.3MHz so it seems pixels are pushed out at 1/2 of 25MHz clock rate The NTSC timing for V Sync , front porch (480~494) , Hsync, back ...

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