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13

Those "logic ports" (I would call them "inverters", and some people call them "not gates") have limited current/power output. By connecting multiple units in parallel you simply multiply the current drive capability. You can pull a heavier load with two horses (or mules or oxen) than with one. And, as a separate matter, driving each side of the transducer ...


7

You can drive the clocks from the FPGA if you want to reduce part count. In general there are two downsides I can think of: Clock jitter - the I/O pins of the FPGA will add jitter to the clock - this is basically where the clock edges aren't at exactly the right place and as a result the frequency varies by a small amount cycle to cycle (the average ...


6

A driver has a maximum output current capacity. When you put two drivers in parallel, the output current capacity is ideally doubled. In reality it is not always exactly doubled because of impairments, but the output current is close to double of the current that each driver can deliver alone. Regarding the voltage, when one driver outputs high (~Vcc), the ...


5

simulate this circuit – Schematic created using CircuitLab Figure 1. Dual comparitor circuit using open-collector outputs to form logical AND function. How it works: R4 and R5 divide V2 by 2 giving 50% of V2 at the junction. R1, 2 and 3 set reference points of 55% and 45% of V1. The LM324 has open-collector outputs so they can be connected ...


4

I don't know about online classes, but I can tell you what I did when I designed my first CPU. So there are three steps: Get a good Digital Design / Computer Architecture book. I strongly recommend the "Digital Design and Computer Architecture" from Harris and Harris, and also "Computer Organisation and Design" from Patterson and Hennessy (2nd edition). Of ...


4

When your program makes the synthesis of your VHDL, plenty of reports are generated. Normally you can see detailed logic resources usage per VHDL block, component and so on. This is the way I do it in Quartus.


3

It is 8, fan-in speaks to the hidden logic complexity and thus speed. Tying inputs together does not remove those elements inside the gate (transistors). In some synthesis engines, this cell would be optimized to a 4 input gate and then the fan-in would be 4.


2

With the photo added, it does indeed appear to be an MP1470. Comparing the pin functions from the datasheet we see that the circuit does indeed seem to match. There's a capacitor between pins 2 and 6 which match the boost capacitor in the example schematic. Pin 4 is connected to a network of resistors which seems correct. Pin 3 seems to be some form of ...


2

Since this device drives LEDs and is connected to an EEPROM (the ATMEL 312 24C02N), it is likely some kind of microcontroller. There aren't very many types of components that would make sense being connected to both a memory device and a set of LEDs. If it were only connected to the EEPROM, it could be something like a protocol bridge to allow a ...


2

I think viewing this as sorting is a complicated way to address this problem. Shuffling the bits all the way in Verilog would certainly be a pain. Unless I did not uderstood the problem well, it seems to boil down to counting the bits that are set to 1, and outputting a string that has this number of 1 to the right. I think this would be a more appropriate ...


2

As a designer of a digital circuit you generally do not have to worry about the W/L ratio of the transistors. Actually a schematic and a netlist describe the same thing ! They both describe how all components are connected to eachother. A schematic is easier to read for humans, a netlist is what a computer program expects as input. Fortunately almost every ...


2

At full data rate, you have a square wave that is 25 MHz and if you have a 3dB bandwidth of 75 MHz you'll pass the 3rd harmonic through without too much loss of shape. It won't look perfect but the eye pattern will be good enough. Below shows how the square wave is "built" from its harmonics. The picture after the sinewave at the fundamental is the "square ...


2

Simple answer. Do not hook them [push-pull outputs] together. Ask yourself why you thought you had to hook them together. If it was because you wanted to signal when the output of either gate output was high level then the simple solution is to add a third gate to take the other two outputs and OR them into the final net signal.


1

This can be easily accomplished with a pulldown resistor. That's a fancy name for a resistor to ground. The resistor value is set low enough so that the line is held solidly in the logic low state when nothing else is driving it. The value is high enough to not exceed the current source capability of anything that needs to drive the line high. For ...


1

If you had put y2, y1, and y0 in the truth table you would have noticed that this circuit adds x0, x1, x2, and x3 and outputs the sum as y.


1

Your switches are arranged LSb to MSb, but you're inputting the numbers MSb to LSb. Your schematic shows 0b0010 + 0b1010, with a correct result of 0b1100.


1

You have forgotten that the concurrent assignment in VHDL is actually working concurrently. So these lines: Q <= NOT Q; NQ <= NOT Q; Will take the previous value of Q, invert it and assign to both Q and NQ. Probably you might want to replace the second line by NQ <= NOT NQ;


1

Electronic peek-a-boo! simulate this circuit – Schematic created using CircuitLab Figure 1. Open circuit switch loaded by voltmeter impedance. I think you are expecting about 1.5 V across TA and TB. If you redraw your circuit as open switches (transistor bases pulled to ground) it should become more obvious what's happening. The internal ...


1

If those gates are both "totem-pole" outputs (where they actively drive the output high or low) then that configuration is undefined and "illegal". For exactly the reason that you have discovered. The diagram you show is simply wrong and must be re-designed. It is NEVER proper to connect the outputs from two active gates together. There is a technique ...


1

Have you seen this page? Also it helps to understand the behavior of the device. It stores one bit of data until it detects the rising edge of the clock, at which point it loads a new bit from the input.


1

There are eight possible input states, of which three are invalid: (a,b,c) = (0,0,0); (0,1,0); and (1,0,1). The first two of these give a high impedance state at the input to the final inverter, and the third gives a 0/1 conflict at the final inverter input. Construct the truth table and it's clear that \$out=a.c\$ is the correct answer.


1

If \$c=0\$, then the top tri-state is hi-Z. The lower tri-state must be on (\$a=1\$) for the output to be well-defined, so \$out=c=0\$. If \$c=1\$, then the top tri-state is enabled and: a. \$a = 0\$ so that the bottom tri-state is off and \$out=a\cdot b = 0\$; or b. \$a = 1\$ and the top and bottom tri-state must have the same output for the state to ...


1

The simplest way would be to use an integrated chip that does the whole up/down counting. There are some specialized for this, for example the 74HC191. If you use this specific chip, the input are a bit different than what you need: you have the \$\overline{CTEN}\$ pin which can serve as a STOP input (if it is 1, the count is inhibited), and the ...


1

Start by making the problem smaller. What if you only had two-bits. Then you would have the truth table 0 0 => 0 0 0 1 => 0 1 1 0 => 0 1 1 1 => 1 1 Notice that the LSB is the OR of the input bits, and the MSB is the AND of the input bits. Then think about a repetitive structure that could be applied to give you the result you are looking for., ...


1

Here, your calculation seems to be correct, VIL - VOL = NML VOH - VIH = NMH, from your calculation, NML = 2.3 V - 1.4 V = 0.9 V and 1.8 V (NMH) = VOH - 4.5 V, so VOH = 6.3 From your valuation we can say that, If Vdd is 5 V then VOH can't be 6.3. See Image and interpret accordingly.


1

Without knowing what PLC you are using, I'll give you an example with a CLICK PLC. The CLICK PLC makes this trivial as it has built in I/O on the processor and I'm using model C0-02DR-D $139 which has (4) 24VDC inputs (4) Relay outputs (2) Analog inputs (configurable as 4-20mA or 0-5V) (2) Analog outputs (configurable as 4-20mA or 0-5V) The first thing ...


1

I have designed and built boards with mixed analog and digital, and they do have separate ground planes. (I used a 4 layer board) The ADC converter had separate analog and digital ground pins. (it was an LTC1605IN) This is the point were Agnd and Dgnd were joined with a very short jumper wire. ALL analog sources were analog grounded at their inputs, ...


1

I agree with @transistor's comment. Programming at assembler level might be a much quicker and more effective way to learn initially than trying to start at designing a CPU. I think designing a CPU would be quite a lot of work to get it to do anything meaningful, and without proper test cases or use cases, the design might be rubbish but there'd be no way ...


1

I can recommend this online coursework. You make a 1 bit ALU, then a 4 bit ALU and then an 8-bit ALU. Download Quartus II from Altera and start making a multiplexer, an adder, a decoder and put it together as an ALU and you got a 4 or 8 bit system that can perform your operations. If you get an FPGA you can even execute your own code in your own custom CPU. ...


1

Somewhere in all that circuitry you must have an ADC converter. That is the point where analog and digital signal grounds meet. Some ADC's even have separate gnd pins to handle this issue. The digital gnd then has a trace to connect it to power gnd. This way all signal grounds are on the circuit board and power gnd follows its normal path from the board to ...



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