# Tag Info

7

You asked for a circuit. Here it is: Using a microcontroller is the obvious way to do this. This is exactly the kind of sequencing and timing a finite state machine is great at, but analog circuitry not so much. Note how elaborate and relatively complicated the solutions using analog parts like the 666 555 timer are. in this circuit, the pushbutton ...

6

Yes, it is usually an IC with 4 of the same gate inside it sharing a common $V_{CC}$ and GND. The datasheets sum this up pretty well. Here is a quad NAND gate pinout: Notice that there is one set of power connections and 4 identical gates.

6

The naming scheme on the primitives in your image suggests that this design is intended to be implemented in an FPGA. If this is the case, gating a clock network is not recommended. Clocked logic elements in an FPGA can usually only be clocked by dedicated clock networks. These networks are only available in very limited numbers (i.e, perhaps a dozen on the ...

4

It's not the mystery other comments are saying. Consider the standard CMOS inverter: There are two FETs, one n-channel and one p-channel. Normally one is on and one is off. What happens in the intermediate voltage range? Both of them are partly on. This connects the power rail to the ground rail and a substantial current can flow. This is called ...

4

If the present output depends on previous output, then use the previous output as as one of the variable in truth table and K-map. Take JK flipflop as an example: ------------------- J K Qn Qn+1 ------------------- 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 ------------------ ...

4

Analyse the working of the circuit for all possible values of A and B. Write down a truth table of A, B and the output. Then you should recognise a pattern. In this case, note that the output is directly connected to 6V. What does that tell you?

4

The question is not whether current flows, but what the voltage is. When both A and B are false, C is connected only to +5V through the pull-up resistor. When A or B is true, C is connected directly (without much of a voltage drop) to ground through one or both transistors. See open collector for pratical applications of this circuit.

4

Your inputs may be lacking pull up resistors. Without them, the inputs float and can be at any voltage level. Some inputs can be pulled up internally by configuring them that way. But not on port A for this device. (It is available on port B, though.)

4

I have seen older logic analysers that were capable of showing if an input signal was in a disallowed state. That is: the input voltage was in the region between a defined logic LO level and a defined logic HI level. This was many years ago and I don't recall which logic analyser it was - I'm guessing Tektronix but I honestly don't remember. Certainly the ...

3

Hint #1: Break the problem down into chunks. You have a system with two inputs (a measurement and a value to compare it with) and an output (a single bit). You know that you must compare the measurement and the value, and spit out a single bit indicating if the values are equal. So, at least you know that you need some comparison logic. You should also ...

3

You've got a good start. Just re-distribute the second term over the first: (A + B)(AB)' = A(AB)' + B(AB)' And then apply De Morgan to the whole thing: A(AB)' + B(AB)' = ((A(AB)')'(B(AB)')')' The Boolean expression gets to be a little hard to read, but it translates to the following circuit: simulate this circuit – Schematic created using ...

3

The blocks labeled "FA" are called full adders, and they are fundamental to how binary arithmetic is done at the gate level. The circuit you have presented here is an implementation of a 4-bit adder/subtractor. Combining addition and subtraction in the same operation requires the use of an alternative representation of binary numbers. This is called 2's ...

3

I don't know if this is a homework question or not. But I'll give you a hint of how I would do this. You need an astable oscillator with a period equal to your desired ON and OFF time. A 555 timer works well here. Then use a packaged counter chip that includes fully-decoded outputs. A CMOS 4017 comes to mind. There are other choices as well. You OR ...

3

I think the circuit shown below will do what you asked for, and here's how it works: A 555 needs to be triggered by a low-going pulse (Vcc to GND) which lasts for less time than the output pulse does. When triggering it with a manual switch, such as S1, below, the 555's TRIGGER input needs to be pulled up to Vcc with a resistor, R2, and the low generated ...

3

This technique is generally called Direct Digital Synthesis (DDS). How can the frequency be varied without effecting the number of samples present in the wave? It doesn't; The sample rate is fixed. I.e. the synthesizer/oscillator outputs some number of samples per second, this does not vary, the sample value varies. Lets say you used a sample rate ...

3

Low pass filtered PWM can do what you want, but you need the PWM frequency to be much higher than 500 Hz. Yes, you can get hard-wired logic to do some of this task. Use the PWM hardware built into most microcontrollers. If yours doesn't have any PWM outputs, go use one of the many many micros that do. PWM hardware in the micro will take care of producing ...

2

An XOR gate and a pair of inverters will do this if you don't need precise control over the pulse width. simulate this circuit – Schematic created using CircuitLab How it works: An XOR gate output is high only when its inputs are at different states (i.e. 10 or 01). The two inverters add a small amount of delay to the signal seen on the bottom ...

2

The steps I usually follow to find the solution are explained here. (Disclaimer:I am not an expert here.) 1. Derive the input-out relationship The first step is to understand and express the input-output relationship in some form. You can express this relation in a convenient form. Some of the standard forms are mathematical expression truth table ...

2

What you have there is a decoder, also refer to in this usage as an address decoder. It decodes a binary number into one-hot. An encoder does the reverse. The benefit in using one is that you don't need a wire in your address bus for every memory location. If your memory has $k$ locations, you would need $k$ wires, but with a decoder, you would only ...

2

Erm, that's just $A \bar B$.

2

It appears there definitely is some inconsistency on the definition of a dynamic hazard. Although I have seen some definitions of dynamic hazards that are similar to yours, for example this one: "Dynamic hazards occur when the output signal has the potential to change more than once when it is expected to make a single transition from 0 to 1 or 1 to 0." ...

2

In ASK, a carrier is multiplied by a set of discrete amplitudes, depending on the information bits. In practice, binary ASP (BASK) is often used, where one of the amplitudes is zero, i.e. for a digital $0$, the modulated signal is zero, and for a digital $1$ the modulated signal is the carrier multiplied with some fixed amplitude. This important special ...

2

Where a logical 1 is equal to +V minus a diode drop, and a logical $0$ is equal to $0$ V plus a diode drop, using resistors and diodes it's only possible to construct AND and OR gates like this: Inversion isn't possible and Y must either be pulled up - through a resistor - to +V for the AND function, or the polarities of the diodes reversed and Y pulled ...

2

What you have there is an RTL (Resistor-Transistor Logic) NOR gate. When A and B are both low the transistors are turned off. It's like they aren't there, so the output C is connected to +5V. That equates to both inputs being 0 and the output being 1. A | B || C ------------ 0 | 0 || 1 When either transistor is turned on a path between C and ground ...

2

I'm sorry, but you're out of luck. There is no obvious way to tell if a digital input is floating. The bus receivers cannot tell if a given input voltage level is occurring because a driver wanted to, or if it's because there is no input driver. All it knows is that the input is either higher (logic 1) or lower (logic 0) than the receiver's threshold ...

2

In most simulation software, the bus data display depends on the number representation being used. The general rule is that if any of the bits that affect a particular display digit are undefined, then that digit is displayed as an 'X'. When the display is in binary, octal or hex, the resulting number might have valid digits with 'X's among them, because ...

2

This would be easier and have a lower part count and cost with a microcontroller and a transistor or optó coupler. A standard push button code example would be all that you really need.

2

Inputs of bipolar TTL (74xx, 74LSxx, and others without a "C" in the middle) parts source current, so require a fairly low resistance to ground to be recognized as a low. You may need to draw up to 0.8 mA from the Clear input pin (and most others) to get the pin below 0.4 volts, so it will recognized as a Low. CMOS versions (74 AC, 74HC, etc) have very ...

2

If the output of one edge-triggered register feeds the input of another, and both are fed from a common clock and respond to the same edge, then it is expected that on a rising clock edge the second register will capture the value that the first register was holding before the clock, at the same time as the first register captures the value which was on its ...

2

There's no need for any such book. The reason is that "all of the different Logic devices that can be implemented with basic logic gates" is just all the possible truth tables that can be constructed with any particular number of inputs. So a book of all the possible gates would be the equivalent of a list of all the numbers between 0 and 2n-1. In FPGAs, ...

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