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12

The answer is the inverse of X0 i.e. \$Y = \bar{X_0}\$ It's clearly this because if \$X_0\$ is 1 then the number is an odd number. Sometimes you've just got to look at the truth table without thinking much about boolean algebra.


10

Of course there's an external power supply. Take a look at a NOR gate chip (say, 74HC02) and you'll see it there clear as day: Logic symbols purely show the logic flow of a circuit, not the power flow. Many schematic capture programs will take the power connections as read and automatically connect them to the right nets for you. Internally a typical ...


8

In today's world with many decent choices of hardware design suites with HDLs (Hardware Description Languages) and Digital Circuit Optimization and Minimization there is no real need for small topology logic design as offered by Karnaugh maps. On the other hand there are two pretty useful areas where they come into play. A) One area is in the training and ...


7

With synchronous counters the delay occurs while the clock is inactive (unchanging, or an inactive edge). When the next active edge arrives at the clock inputs, the data inputs are already stable. Hence all outputs change at the same moment, which is the essence of the system being 'synchronous'.


6

Of course there is an external power supply (as you suspected). Here's a quad nor gate: - Notice pin 7 and pin 14 The same sort of thing is done with op-amps - they don't necessarily show the power pins because they are assumed folk know they are there: - But once you've learned about them you realize the basic op-amp has power pins (normally 7 and ...


5

2B Or NOT 2B - That, is the question! Implement with a NOT gate, and a dual-input OR gate. You're welcome :)


5

By sequential I assume you mean a (bit) storage cell? A static storage cell must have two elements: positive feedback, to maintain a stable state forever an input that can overrule the feedback (in both directions!) Cross-coupled NAND or NOR gates have both properties. (The cross-coupling is the positive feedback path.) There are more complex building ...


5

12.5 Mhz (80 ns cycle) should be doable. Wire up your clock lines first. Pick placement that keeps them short and cut the jumpers to length so that you don't have big loopy antennas. Verify that you are getting nice square clocks before wiring the rest.


4

The other answers have addressed part of the question, but it may also be worth noting that the power supply connections are often omitted from schematics (especially conceptual rather than practical ones) such as the RS latch of the question. One also often sees OpAmp circuits where those connections are not mentioned, but rest assured that real parts do ...


4

Your circuit needs to be started in a known state, and if the default is to be with the 4013's Q low and both 4017s' Q0s high, then to that end I've taken the liberty of redrawing your circuit, below, to include the Power-On-Reset using diodes to make it compatible with the rest of your diode logic. Note that your R5 isn't needed since the diodes are being ...


4

For each 16 bit device (other than the final one) put a single D type flip flop on the output and use it's output as feed to the next 16 bit device. The d type will soak up each 17th bit or, looking in a different way, the d type makes the 16 bit device a 17 bit device.


4

I generally take a top-down design approach, and I start by drawing a block diagram that shows the interfaces among the top-level blocks. I then draw additional diagrams that represent the implementations of the top-level blocks in terms of lower-level blocks. This hierarchy of block diagrams translates pretty much directly to the hierarchy of the HDL ...


3

It is easy to go through these circuits. Lets say that on the left side of the first inverter is a logic value of 1. This value is inverted and is 0 at the left side of the second inverter. This will become a value of 1 on the left side of the 3rd inverter. After the 3rd inverter the value is 0. this value is also on the left side of the first inverter. ...


2

I'm afraid your assumption is not entirely correct. If a datasheet doesn't give a guaranteed initial state, which standard HEF40** device sheets intentionally don't, there is no guarantee. The decade counters in fact hint at the fact that they start with the value you assume if, and only if, the master reset has been triggered. The only thing you can ...


2

This is normally solved by a dedicated /RESET pin on the IC that can be pulled low to bring the IC into a predictable and useful state. This line is usually driven by the power supply for as long as the supply voltage isn't stable, and can be used again if the system goes into an invalid state. This state need not necessarily have defined states for all ...


2

Gate delay causes it to ripple. While the first one is receiving the output of the last one, the middle one is propagating the output of the first one, and it will continue like this forever. The logic in general will cause this toggling, because it would go 1:0:1, or 0:1:0 and would constantly oscillate between these states.


2

No discussion of why is is common to use + instead of ∪,∩,∨,∧ would be complete without noting that printers and tranmission codes (such as Baudot, ITA, and ASCII) provided the Alphabet, Numbers, and 'common business symbols'. It's hard to imagine now, but there was a time when special symbols were not easily represented on input, and represented an ...


2

My suggestions would be (expanding on what Jeff has suggested): Make sure you run a ground from a pin as close as possible to the clock pin to another pin as close as possible to the clock pin. Twist the clock and ground wires together. Keep them as short as possible. Do you have a good high bandwidth scope to check the clock with, so you can see any ...


2

NAND and NOR gates are the basic building blocks of all logic. Using only NAND gates, or only NOR gates, you can create any other gate you want. For instance, the Apollo Guidance Computer was created entirely out of NOR gates. NAND and NOR are the only common gates* you can do this with since they have an inverting output and can be arranged by just tying ...


2

Many CMOS logic designs (and also NMOS and PMOS designs, btw) make use of a circuit element called a "pass gate". In its simplest form, a pass gate is simply a single NMOS or PMOS transistor (also called an NFET or PFET). An NFET will connect is source and drain when the gate is high and disconnect when low; a PFET will connect the source and drain when ...


2

RSA will not be easy to implement and may require a very large FPGA. RSA is far better suited to running on a general purpose CPU than an FPGA. I have seen some implementations of RSA on an FPGA that use a softcore to run the algorithm and the FPGA to accelerate some of the math, but the complete algorithm is not implemented in Verilog. And generally when ...


1

An RFantenna does not produce a proper EM radiating field up close to the antenna. Fact of life I'm sorry to say. What it does produce up close is an E field and an H field that are more akin to that measured near to an inductor or capacitor. Up close, the two fields have not managed to become in time phase with each other and, as a pair of fields they ...


1

Rule of thumb: physically larger antennas have narrower beam width for the same frequency. If you want to make a 30 MHz monopole more directional, you can't just cover it with a piece of metal. One solution would be to get a bunch of antennas and build a linear array, where the array factor would give you the gain. This array will need to be at least ...


1

The Short Answer is YES it is possible and indeed it is very common to NOT use cross-coupled Gates. In fact most active circuits (in the form of microprocessors, SOC's ASIC's etc.) do not use this form (cross-coupled) of latch or memory. The absolute minimum requirement for a memory cell is hysteresis, and in designs that only use transistors the easiest ...


1

You didn't take my hint form your previous question: "Gate count can be reduced further by share logic with the gates inside the fulladder." To get the minimum gate count you need to look the full combination logic. One of the best methods to simplify the logic and reduce the gate count is by using a Karnaugh map (also referred to as a K-map). This is ...


1

That code is not verilog. It looks like it is probably C. However, it is possible to use an if statement in verilog. Looks like the only thing you need to do to make that code into valid verilog is to replace the { and } with begin and end. However, you may need to put it inside an always block of some sort for it to work correctly.


1

Addition and subtraction have inverted constants \$C_{in}\$, we can be connected to \$(I_3 \vee I_4)\$. Then invert the subtracting value before passing to a full adder. ADD/SUBR/SUBS can be expressed as : $$ (R \forall I_3) + (S \forall I_4) + (I_3 \vee I_4) $$ Using the same xor inversion method you can mearge: AND/NOTRS : \$ (R \forall I_3) \wedge S\$ ...


1

So you want to be able to display the ALU result both before and after it is stored in memory, and be able to load that result into the ALU's a or b input? Connect all the data lines together to form a bus. Obviously this bus can only carry one 8 bit value at a time, so each device connected to it needs an input register (8 bit latch) to write (STORE) ...


1

You can shift it like this if you don't have the center voltage already available: simulate this circuit – Schematic created using CircuitLab Or like this if you do: simulate this circuit You may recognize it as a highpass filter, which it is. In signal processing, DC (constant offset) is 0Hz, and is considered a frequency just like ...


1

In the last few pictures, it looks like you've configured the "sub flag" as an output, not an input. Since there's nothing driving that net, it's resulting in an error.



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