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10

Both answers are correct. Let: $$ f_1(A,B,C) = AB+AC+\overline{C}\\ f_2(A,B,C) = A+\overline{C} $$ Let's build the thruth table: $$\begin{array}{|c|c|c|c|c|} \hline A & B & C & f_1 & f_2 \\ \hline 0 & 0 & 0 & 1 & 1\\ \hline 0 & 0 & 1 & 0 & 0\\ \hline 0 & 1 & 0 & 1 & 1\\ \hline 0 & 1 & ...


5

Yes it's possible. Virtually any gate is possible so long as you have a 2 input gate with the capability for inversion. Take a closer look at an XOR gate truth table and you should be able to see how to do it: \begin{array} {|c|c|c|} \hline A & B & OUT \\ \hline 0 & 0 & 0 \\ \hline 0 & 1 & 1 \\ \hline 1 & 0 & 1 \\ \hline ...


4

Why do you feed the carry out back around to the carry in when you're subtracting? That doesn't seem right, and that's the feedback path that's causing the "oscillation" (which basically means that the simulator can't find a self-consistent output state). To negate a number, you need to invert all of its bits — which is what I assume the upper-left ...


4

Try searching yourself at a distributor such as Digikey to get some idea of availability. I'll take you through a step-by-step if I was looking for, say, a NOR gate with at least 4 inputs. I'll be primarily interested in 4000 series CMOS or 74HC CMOS families (usually it would not be for the same application). First, get on the site and search for NOR ...


4

You should try loading the output with something like a 10K resistor, first to ground then to +12V and see what happens. One way or the other you will likely see a reliable logic change, the opposite way you'll see no change in voltage. Sounds like this might be an industrial standard output that can only source or sink current. If you don't put an ...


4

Oh, take a step back a little from it first and look at the different parts of it. What stimulus, ignoring the extra conditions, would make the alarm sound? Simple: someone tampers with the vault -OR- someone opens the bank door. Now, when would those stimuli cause the alarm to sound? Again, simple - when the alarm is armed. When is it considered ...


3

A schematic would be helpful as there is no way to know what "the component on the right" is; however here is what I can tell you: From the datasheet for the 74AHC574, you can see that the 74AHC574 is "OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS". The tri-state (3-state) outputs are probably the reason for the pull-up resistor. The pull-up ...


3

Your question makes no sense since 910 can't be expressed by a 8 bit 2s complement number. Such a number can only take on values from -128 to +127.


3

Take a look at the data sheet: - When the output is driving low (trying to drive to 0V), with an 8 mA load, the specification tells you that it is guaranteed to drive as low as 0.36 volts at ambient temperature and as low as 0.55 volts at full temperature of the device. If it's running from a 5 volt supply and the resistor is 1 kohm, the most current ...


3

It's just simply to reduce the "glue logic" needed in implementing the device. It's simple enough to simply just tie the one input to low to just the pin as a single input but tis gives more flexibility in implementation. If you look at the package you realize that without the extra /enable that package would have an NC pin. I suspect the first designers ...


3

There were quite a few 3-input gates made, with three circuits per package. This meant that 12 pins would be needed (3 inputs, 1 output) x 3 and adding VCC and GND uses up all 14 pins in a 14-pin package which was very popular at the time these parts were designed 40 some years ago. Here are the 3-input logic ICs I am aware of: triple 3-input NAND ...


3

Transpose of a Matrix can be given below For example suppose matrix is as below 1 1 1 1 0 1 0 1 0 0 1 0 0 0 0 1 Transpose of the matrix can be given below (Flip Across diagonally) 1 0 0 0 1 1 0 0 1 0 1 0 1 1 0 1 Now keep this matrix on K-MAP As shown in fig below So the expression can be given as ...


2

With only simple logic gates, you're going to be "putting a crazy amount of them" on the four MSBs. Optimizing your logic can help reduce the number of gates (there are two that start with 11, so they can share some gates, for a start). However, if you were to spend a few pence and invest in a 74xx154 4-to-16 decoder then the 16 possible combinations of ...


2

If you use a latching relay on the fan end, it can latch on a high pulse, then "un-latch" on the next high pulse. You will have to check the relay datasheet to be sure the length of the pulse is long enough to latch/unlatch, and that the voltage and current requirements are met for the relay coil latching.


2

If you're asking what would be involved in building such a project: First step is to select what processor architecture you intend to build, then find an actual Linux distribution from Red Hat or SuSE or BSD that runs on that architecture. For example, i386-32bit or ARM-32bit might be a place to start. I doubt you will find any (modern) distribution that ...


2

You do not want a octal latch. Instead what you want is an Analogue MUX. A 4-1 Analogue MUX should do what you want. There are many options and factors to consider when selecting such a part. Some important ones are: Is the analogue signal bipolar (i.e. swing above and below GND? What is the peak voltage swing range of the analogue signal to be switched? ...


2

I have done it by using an I2C GPIO expander chip. I used the Microchip MCP23017, but there are others out there as well.


1

Use one GPIO as an Output and toggle it while timing the rise and fall times of the other GPIO set to input. Choose resistor values to separate the timings for each key as much as possible while accounting for component variations and uController logic input threshold variation with temperature.


1

A serial interface could do the trick. An I2C-like interface could operate on only two I/O lines (Data and Clock). Utilizing shift registers would be possible using three I/O lines (Data-in, Data-out and Clock) in an SPI like mode (assuming to skip any chip select lines).


1

I strongly recommend adopting an existing Instruction Set Architecture (ISA), unless you are very keen to write your own C compiler. A related issue is, should your machine be 'self hosting'? Do you want the machine to be able to run the compiler, and compile programs, including the OS on itself. The implications of that decision constrain several choices. ...


1

Interesting. What goes around comes around. A boolean matrix is a way of describing a set of functions on a group of input variables. In fact, most modern FPGAs implement this directly, where one function is implemented by a 4-, 5- or 6-input LUT (lookup table). The matrix algebra allows you to compose arbitrary functions by combining functions you already ...


1

I suspect they use a sequential method where they weakly drive the pin high and low and sample the states. There are four possibilities in the truth able, one of which should never happen. Since they do not seem, to be too concerned about floating outputs connected to SA0, a reasonable CMOS input should be okay- but I'd be concerned about long conductors ...


1

There are quite a few more-than-two input logic gates available. For example, the 7400 series of logic gates is outlined on this wikipedia page. For 8-input specifically, there is: 7430 8-input NAND gate 744078 8-input OR/NOR gate


1

Your assumtion is right: digital logic signal '0' (or 'LOW') means a connection to 'GND' (or a voltage close to 'GND'). It does NOT mean 'not connected', as many novices may think. That's the case in most digital logic families (TTL, CMOS); there are, however, exceptions, e.g. ECL.


1

Simply use De Morgan's Theorem twice. Using it once we get $$A \cdot B + \overline{C} + \overline{(\overline{A} + \overline{(B+C)})}$$ Using it on the final term then gives us $$A \cdot B + \overline{C} + A \cdot (B+C)$$ which simplifies to the expression given $$A \cdot B + A \cdot C + \overline{C}$$



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