# Tag Info

## Hot answers tagged digital-logic

25

What happens is usually cases 3. or 5. You have not defined case 5 :-) The joined input-output will sit at some voltage near the middle of the supply. 74HC14: When a Schmitt triggered gate is used oscillation will almost certainly occur. Assume Vin-out initially = low = 0. When input = 0 output will transition to 1. Time to do this is ...

22

what you are describing is called a Ring oscillator Your output will oscilate with a certain frequency depending of the gate delay of your NOT gate. A perfect NOT Gate would oscillate with an infinite high frequency. Since such a perfect device does not exist, your frequency will be $f=\frac{1}{2*t}$ where t is the gate delay of the NOT gate you use....

21

What is 180 degrees phase shift? When the signal is a sine wave, a 180 degrees phase shift delays the signal for half the period of that sine wave, the sine wave then looks inverted: Can an inverter do this? No, because it has signal gain, the output would be a square wave, not a sine. When the signal is a square wave with a 50% duty cycle, then ...

11

Looking at the transistor schematic it can be seen that the resulting circuit consists of two transistors that have their gates connected to their drains. This so called "diode-connected" transistor acts like a non-linear resistor. simulate this circuit – Schematic created using CircuitLab Basically you end up with a voltage divider and ...

6

I wouldn't recommend it. There are a lot of weird quirks to redstone logic in Minecraft, and it's constrained by the mechanics of the game. In particular: Redstone circuits must be constructed on the surface of a structure in 3D space, and the player must move around that space to work on their circuit. Building that structure will suck up a lot of time. ...

6

LTspice does not have a limit on the number of components or nodes. Likely, not the number of components or the overall size of yor schematic is the problem, but you might be facing some no-nos that make your circuit hard to solve. If you have capacitors, try adding a small ESR by editing the component properties. If you have inductors, adding a DC (copper)...

5

"I want this!" You're not the only one. Such a circuit would be very useful to tell when share prices had bottomed out and I'd use the interrupt to tell me when to buy. As drawn in your second diagram you are looking for a circuit that will predict that this is the lowest value that's coming. We don't have electronics to predict the future. What you can ...

5

It depends on how short the pulse is. If it is extremely short, the transmission gate or tristate element which grants access to the master latch will not have time to even properly turn on, so the bitcell will retain its original value and nothing will happen. The other case of failure due to minimum pulse width is the case in which the forward element ...

4

Your circuit is a strange mix of upside-down-ness. Figure 1 shows a more-likely-to-work configuration. simulate this circuit – Schematic created using CircuitLab Figure 1. The standard solution to this problem. A few tips: Draw your schematics with positive rail on top and negative at the bottom. It will be easier to trace current flow from ...

4

Use some filtering to get rid of the majority of false flats and then use an analogue differentiator (CR high pass filter circuit) to produce zero crosses on the remaining flats. This can feed a comparator that rises or falls depending on the signal direction change. Then, use an exclusive OR gate and a small RC time constant to convert the comparator ...

4

Your problem is that your load resistance (an electromagnet) is far too small. The 4000 series should not be asked to put out more than a few mA at 12 volts. Try disconnecting the load and measuring the voltage. Without knowing how much current your magnet requires, I can suggest the following circuit: simulate this circuit – Schematic created ...

4

I am not that good with explanations, but I'll try. Mike, the creator of LTspice, had went through great lengths to ensure that the solver does not encounter abrupt changes which could pose problems. This means that even the ideal diode, when simulated, will show a small rounding around the knee. Add enough points and it will get sharper, but zoom in and ...

3

This may be technology dependent, but at least a TTL NOT gate (bipolar transistors) can often be viewed as just a high gain inverting amplifier. By connecting input to the output, you create the strong negative feedback, so the amplifier will stabilize somewhere between logical 0 and logical 1. If you connect input to output through a resistor, it may be ...

3

Metastability is generally not oscillation, but the signal from a latch, not an inverter, hovering around 50% of rail for an extended period of time before settling to one or other state. Just a few weeks ago, I successfully observed metastability in an LtSpice simulation. I googled for a transistor level model of a d-latch, and then used a binary search ...

3

Never underestimate the benefits of capacitors. If the lighting was constant intensity any capacitors would be redundant, however if your strobing the LED's or sequencing them, small brief voltage drops would occur in the power feeds. Even if the WS2812B drives the LED's with constant current 100uF 16vdc electrolytics will remove glitches from the power ...

3

Given inputs A, B, C, D and outputs X, Y, Z, where XYZ is a 3 bit unsigned binary number representing the number of bits in ABCD that are 1. Let X be the most siginfiant bit of the binary number and let Z be the least significant bit. The truth table for the function looks like... ABCD => XYZ 0000 => 000 0001 => 001 0010 => 001 0011 => 010 0100 => 001 ...

3

Why not just switch the mosfet directly? Its not as if you are using the logic gate to perform any logical combination.

3

The great answer of Zebonaut was about the circuital aspects that may impact the simulation. I'll add a couple of points on the software side aspects: Try increasing the precision LTspice uses in performing the calculations. By default it uses single precision. If you add the directive .options numdgt=12 on the schematic it will use double precision. This ...

3

But what about when the gate is disconnected? The disconneced gate pin acts as an antenna, and will pick up some electromagnetic noise from the environment - likely the 50 or 60 Hz from the nearest wall power lines. The end result is largely random, and there are other effects like leakage currents to account for. Thats why you want a pullup or ...

2

Using the parts we have in CircuitLab, which are 2 and 3 input ORs and including some logic for getting an output tied to even/odd which was not in your initial question (for the initial question the circuit without the AND gates will do): simulate this circuit – Schematic created using CircuitLab This version gives you an additional output ...

2

The simplest transistor-based circuit is the RTL flip-flop: simulate this circuit – Schematic created using CircuitLab C1 is added so that the circuit prefers to power up with the output low, with Q1 not conducting and Q2 conducting. It also sets a minimum pulse width on the input signal. Once that threshold is exceeded, Q1 switches on, Q2 ...

2

I would suggest an exclusive-or gate. If you tie one input high, you have an inverter. If you tie one input low, you have a buffer. The propagation time should be the same.

2

If 'SET' and 'RST' are 15 volt signals, then these mosfets are designed for a gate voltage of +2 to +10vdc, with a limit of +/- 20 vdc. Full ON voltage is +10 volts to +15 volts, so going below 10 volts on the gates takes them out of saturation and into a resistance (non-linear) much greater than zero ohms.As the voltage lowers down to +2 volts and below the ...

2

Not a new-answer, but as simple-way understanding that "point- 5." (that was explaind by other users), with a simple mechanical analogy. A not-gate could be compared with a lever, with a fixed, resting fulcrum at the centre of the lever. (Such as in a scissors). If its one-end (supposed as input-end) pressed-down, the other-end (supposed-as output-end) ...

2

A LUT (Lookup Table) in modern FPGAs is nothing more than a RAM. The inputs are the address lines, and the output is the data output bus. There's really nothing more to it. FPGAs also tend to have more advanced logic modules (some vendors call them ALMs) which consist of one or more LUTs along with additional dedicated adders, high speed carry chains, and ...

2

That bubble stands for P channel MOSFET transistor. See the following equivalent symbols. See the picture for structure of a P channel MOSFET. In CMOS technology the main substrate is P: For example in the NAND gate in the question making both A and B HIGH will cause the upper transistors to be OFF and lower transistors to be ON, therefore F is ...

2

AO222 just means And-Or 2 2 2 which logically means: 3 2-input ands feeding into 1 3-input or. Most inverting complex gates are actually implemented in a single CMOS stage, but non-inverting gates, like the one you mention, need at least two stages. AO222 is most likely made from a AOI222 and an inverter. AOI222 = 3 2-input ands feeding into one 3-input ...

2

Usually the transistor parameters are provided to the customer by the foundry after signing an NDA (non-disclosure agreement). Transistor modeling and parameter extraction is a nontrivial task and usually based on a large number of measurements to get reliable data for the models. Of course with an automated setup this task can be done very efficiently. ...

2

No, your circuit does not invert. When IN is driven low, it should be fairly obvious that OUT will then be driven low thru the diode. OUT will be one diode drop above IN, or Vcc, whichever is lower.

2

A not gate has too much gain to provide a clean 180 degree phase shift but with the right amount of negative feedback some not gates can do it.

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