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22

You can't send half a bit, but you can effectively pack two half bits in one bit before transmission or storage. You give an example yourself, so you effectively have answered your own question with a YES. A maybe somewhat easier way is to simple encode the value of two decimal digits in 7 bits. (Sort of binary coded dual-decimal).


19

You can use huffman coding so the numbers are with varying bit length. if you are aware of a digit that will occur more often than others it will help. example(with equal occurrence): 0 - 1111 1 - 1110 2 - 110 3 - 101 4 - 100 5 - 011 6 - 010 7 - 001 8 - 000 receiving-end example for getting the number 1: The first bit comes in and leaves only 0 ...


14

In a mixed signal system it's recommended to join AGND and DGND close to the mixed-signal IC, often the one performing the A-D function. The reason for this is to reduce differential noise in the mixed-signal IC. See the diagram below. The objective of minimising noise coupling from B to A is aided by joining the GNDs on a low-impedance ground plane. In a ...


12

Perhaps what you are looking for is Arithmetic Coding, which can efficiently encode a string of symbols, each of which in principle might require a fractional (non-integer) number of bits. (though the total message must be a whole number of bits) Quoting Wikipedia: Arithmetic coding differs from other forms of entropy encoding such as Huffman coding in ...


10

The new IEEE P754 for floating point arithmetic now defines decimal formats in addition to binary. One of the encoding proposes to group digital digits by 3 into 10 bits. encoding 0 to 999 using 10bits = 1024 possible codes is quite efficient, and decimal digits are often grouped by three anyway. Densely Packed Decimal : ...


6

The XOR operation is bilinear: inverting either of the inputs always inverts the output. This property is preserved even if you cascade multiple XOR gates (and, optionally, constant inputs and/or NOT gates) together: inverting any input always inverts the output. Of course, you can construct more complex circuits where a single input can be split and fed ...


5

For a real computer, you definitively would want more than 4 bits of program address since 4 bits only allows 16 instructions. So I came up with a scheme using a two-byte instruction for jumps, calls, load and stores which would give you a 12 bit address or 4096 location. However, if you leave off this extra byte, then my instruction format allows for 5 ...


4

Data representation depends on the interpretation you or your program gives to it. We could send '27' also as ASCII characters, for example, yielding 0x3237 = 0b0011001000110111. The way you want to represent the data in bits depends on your application. In the end, with a variable \$x\$ with \$n(x)\$ different possible values, you're going to need ...


4

A 1:1 correspondence of binary (or Hexadecimal) is but one symbol encoding for bits. So yes, as you showed it is possible. Another place this is used is (but slightly differently) is in trellis encoding/decoding in communication systems in which bit transitions are kept farther apart to ease the decoding. And of course 8b/10b and 64b/66b etc. etc. ...


4

Here's a proof that might be a bit easier to picture visually . . . Since XOR is commutative (p XOR q = q XOR p) and associative (p XOR (q XOR r) = (p XOR q) XOR r), there is no interesting way to re-order or re-structure a formula where XOR is the only gate; something like p XOR ((t XOR (s XOR q)) XOR r) is equivalent to p XOR q XOR r XOR s XOR t. So if ...


4

You can do this with 2 ICs and no MCU. I'm assuming you have 3.3 volts available for power, but 3 volts will work. You can use a 74HC4538 monostable multivibrator to detect your 1 MHz, and a 74HC157 to select your data. See http://www.nxp.com/documents/data_sheet/74HC_HCT4538.pdf for the 74HC4538. A schematic looks like simulate this circuit – ...


3

Not with only the standard AND, OR, and NOT gates. For the two-bit adder that takes in two-bit numbers AB and CD, and outputs a three-bit number XYZ, the truth table looks like this: A B C D | X Y Z 0 0 0 0 | 0 0 0 0 0 0 1 | 0 0 1 0 0 1 0 | 0 1 0 0 0 1 1 | 0 1 1 0 1 0 0 | 0 0 1 0 1 0 1 | 0 1 0 0 1 1 0 | 0 1 1 0 1 1 1 | 1 0 0 1 0 0 0 | 0 1 0 1 0 0 1 | 0 1 1 ...


3

Being kind of old myself, I expect you to study like #### too. :D One question may help clarify the circuit you need : how does it distinguish between 2 successive states that are the same? Or alternatively : Is there a separate clock signal, not mentioned above? If so, the basic pattern of the circuit may become clear. Ask yourself : how many states do ...


3

That drawing is a graphical representation of a LFSR (Linear Feedback Shift Register). The whole element is a shift register and is one form of a state machine. This particular representation comes from communications theory and one application is for the generation of PN (Pseudo Noise) generators. The 7,4,1 nomenclature tells you that the 7th, 4th and 1st ...


3

The white squares are likely D type flip flops all connected to a common clock line. Basically this an additive data scrambler. Here's a wiki link. Here's a circuit of a multiplicative data scrambler and I'm showing it so you can see what I mean by the D type flip flops: - I think your scrambler is the type used in WLAN - see this article


2

First, it helps to know that the characteristic equation for a JK flip-flop is: $$Q^+=JQ'+K'Q$$ Where \$Q\$ is the output of the JK flip-flop, and \$Q^+\$ is the next output of \$Q\$ after a clock cycle. Then we derive state equations A, B, and C for every clock cycle. For the output A: $$A^+ = J_AA'+K_A'A$$ Since \$J_A = K_A = 1\$: $$A^+=A'$$ For the ...


2

Any purely combinatorial circuit which consists entirely of XOR gates will, from a combinatorial point of view, compute either the even or odd the parity function for some combination of its inputs and ignore the rest. This may be shown by induction if one observes that each input will be the odd parity function of itself, and the xor of two parity ...


2

No. Due to the both complementary and symmetric nature of XOR's inputs and outputs there is no way to configure any number of them to generate an output that does not exhibit the same symmetry.


2

I would suggest a much older chip, the CD4007. It's designed to be used in exactly the way you describe, to make CMOS inverters.


2

Just add a second NPN as an inverter. simulate this circuit – Schematic created using CircuitLab Adjust resistor values and add speed-up caps and/or Schottky clamps to meet your speed and current requirements.


2

Here are some thoughts on hardware coasts: 8 bit shift register on virtex-5, spartan-6 A slices contains 4 LUTs and 4 registers. You'll need 2 slices to store 8 bits. 8 bit shift register on virtex-6, 7-series A slice contains 4 LUTS and 8 registers. You can store the complete byte in one slice. 3 bit counter Small counters are implemented using LUTs and ...


2

You need a negative voltage to turn off a depletion mode MOSFET, they do not behave like an enhancement mode MOSFET with an inverter in front, so adding an inverter will not help you. Are you sure the MOSFET has not been permanently "enhanced" by being fried?


2

Your circuit concept will work just fine as long as you only enable one oscillator at a time. After all there are reasons that oscillators like these are equipped with an output enable/disable pin. Your application is one of the reasons. Some food for though. To ensure that both oscillators are never enabled at the same time you need to properly comprehend ...


1

Absolutely. Use a 74HC238 instead, which does what you're looking for.


1

So I've always followed this advice, for all sensitive analog sections of a design. AGND and DGND tied at a single point together under the ADC, codec, etc. For a recent high gain, hi-fidelity audio board I just necked down the GND plan under my ADC. The connection is about 100 mil wide, and 10 mil long. I've got an MCU and DSP on one side and my ADC ...


1

Sure, that chip could work. But you'd need 3 of them in a row since using only one would allow the transistors in the output stage to remain in their ohmic region, causing the device to acts more as an amplifier than an inverter.


1

1) How to get .44 of Vdda - A voltage divider and or suggestions? Yes, a voltage divider should do fine. It'll be to set the virtual ground point of the op-amps, and when using discrete op-amps I use a voltage divider for just that reason. It'll be 0.44 because the op-amps may not be rail-to-rail, so shift it down slightly to the mid point of the ...


1

The usual way to pack values is by multiplying each value with its range, so you end up with one large number that you can efficiently represent in bits. When unpacking you divide by range, the remainder is the digit, and the result is the remaining packed digits. If you have 5 values in the range of 0 to 2, you can represent that in 8 bits (you need at ...


1

One approach to parallel-to-serial conversion which can be useful if the parallel data input will remain valid during shifting is to use a shift register to generate a one-hot "use this bit" signal, and then "AND" each shift register output with one bit of of the parallel data input. Such an approach was used in the playfield graphic generator circuit of ...


1

What you are doing is not what is usually referred to as a PISO. The standard PISO has a mode input, and the shift or load function occurs on a clock. What you're doing is rather exotic. Note that what you call a "Load" is actually two separate operations. First you have to issue a reset pulse. Then you have to issue a load pulse. The wiki designs are ...



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