# Tag Info

## Hot answers tagged digital-logic

19

It's the classic undergrad question: Why learn how to calculate the deflection of a beam when there are finite element analysis programs? Why learn Ohm's law when there's SPICE? Why learn compressible flow when there are fluid dynamics programs? Here's why: As engineers, we are responsible for truly understanding how our designs work. That means ...

11

Things I tell my students: Engineers are paid to know "why". If you don't know "why" you are just a technician. When things go wrong, you will be stumped (--> fired). There are no black boxes in engineering. It's your design. You are responsible for it. No one else on the planet will (or should) know your design better than you do. That means you aren't ...

10

Two reasons: Someone has to actually make that "technology that can simplify everything for us", they have to know how it works. Knowing how a system internally works helps the understanding on a higher level. In an analogy, we could say: "Knowledge of Assembly programming helps you making C programs more efficient, although you don't really have to know ...

5

Same deal as Camil Stap's answer, but using a single 74xx00 series NAND chip (4 gates): simulate this circuit – Schematic created using CircuitLab

4

First step is filling a Karnaugh map. The first one for little bit help filling the map:  \begin{array}{c|c|c|c|c|} \text{I1}\cdot\text{I2}\cdot\text{I3} & \text{I1}\cdot\text{I2} & \overline{\text{I1}}\cdot\text{I2} & \overline{\text{I1}}\cdot\overline{\text{I2}} & \text{I1}\cdot\overline{\text{I2}} \\ \hline \text{I3} & ...

4

FPGA manufacturers don't use equivalent gate counts much any more, even in the hand-wavyest marketing materials. Like lines of code or megahertz of processor speed, it's a highly inaccurate metric for measuring the device capability, and in the FPGA markets the customers wised up enough to suppress its use. To estimate the size device you need, you'll need ...

4

Since there are 16 bytes in the RAM you need 4 bits of address information to uniquely specify one of the RAM locations. Therefore, the MAR is 4 bits wide. The MAR doesn't store anything in RAM, it just provides an address. Even though the RAM has just 4 address lines it has 8 data lines, because each "address" in the RAM holds an entire byte. So, the MAR ...

3

simulate this circuit – Schematic created using CircuitLab If your microcontroller can output PWM, then set it to a high PWM frequency, and use a low-pass filter to generate a voltage. Something as simple as a resistor from PWM output to a capacitor, and a resistor across the capacitor to ground, as well as signal into the bar graph input, will ...

3

Use a Comparator "Digital" NOT gates (inverters) are comparatively weak, since they are not designed to drive big loads. In the more general case, you want a circuit topology known as a comparator. A comparator compares the input voltage to a reference and outputs one of it's maximum extents (as close to its positive or negative supply as it can get) if ...

3

The question seems rather confused in several respects... 1) It is unclear whether you want to implement 3-state logic or an open-drain interconnection. In the former, the driving device DOES use a push-pull output, driving 0 or 1 onto the bus. The other devices, meanwhile, must abstain from driving until some separate system signals that it is their turn. ...

3

Your code will not work. In verilog, a 'z' at the input of a gate transforms to an 'x' on the output of the gate. An 'x' at the input of the gate also translates to an 'x' on the output of the gate. Therefore your code reduces to if(wr_req & !cam_busy & X & X & X) The value of (something & X) can be either 0, or X, and in both cases ...

3

Usually such gates are voltage-controlled devices, and not current controlled devices. They generally have very high input impedance, which means that very little current is drawn from the input. How much, depends on the device, so see the datasheet for that. The output side is usually meant to be likewise voltage indicator of the logic state. Whether the ...

3

Implement your debounce like this to fully eliminate the effect of the switch contact clatter. Captured courtesy of this site. Update After discussion in the comments section I am adding the below picture to help visualize the "NAND latch" in the DeMorgan equivalent of its logic to show how the latch really is a low true input latch.

3

FPGAs are more than just gates (LUTs, FFs, Block RAM, Multipliers, etc) and trying to work out how many there are is a fairly meaningless exercise. FPGA company marketing departments have, in the past, thrown numbers like equivalent gate counts equal to 1.4x the number of logic cells but I believe that they have stopped this practice. If you are trying to ...

2

A NOT gate is made up of more than than just one input and one output. You must also connect it to a power source (Vcc on schematics) and ground. When the input is 0 it is connecting the output to Vcc, when the input is 1 it is connecting the output to ground. (see pin 14 and pin 7) Here is what a NOT gate looks like internally simulate this ...

2

Your output follows this formula: output = (I1 & I3) | (!I1 & I2) A circuit would look like: simulate this circuit – Schematic created using CircuitLab For logic gates, you can use the 7400 series: AND: 7408, e.g. OR: 7432, e.g. NOT: 74LS04, e.g.

2

Instead of converting to analog, and then back to digital, just drive the LEDs directly from the MCU, keep it digital. If you don't have enough IOs to drive the LEDs, you can multiplex them, or hang them off a shift register, or off a SPI or I2C IO expander, or latch them, or... lots of possibilities, but more information is needed!

2

Have a look at IIC communications between chips here. I think this will help complete your understanding. It's an industry standard way of implementing a multi-peripheral system using common lines such as clock and data. Open-drain outputs are used with pull-up resistors to prevent power-issue problems when one device wants to drive low whilst the other is ...

2

"logic chips are always hard ON or OFF" - This isn't exactly true. They do a good job forcing inputs to either logic 0 or 1, but if you have a slow, sloppy input transition, than you'll get a somewhat slow output transition as well. The transfer of an inverter looks kind of like an S curve: I doubt that this will give your downstream circuit any problems, ...

2

The basic idea in these kinds of problems is that your D flip-flops represent your state and you need to create some combinational logic that takes as input the current state and generates as output the next state. So first you create the truth table: input output D2 D1 D0 | D2' D1' D0' 0 0 0 | * * * # actually, don't care is not quite ...

2

Think of your special counter as a state machine. Then assign the state the coded value of the count sequence that you want. In this case the states would be as following with the next state showing. State Next State 3 -> 1 1 -> 4 4 -> 7 7 -> 2 2 -> 3 Each state can be encoded into three binary bits so your design will require ...

2

What's important about a clock signal? All of it, of course! :) But seriously, there are many aspects to a clock signal and it is difficult to limit it down to just a couple of things. It also greatly depends on what you are doing with it. Below, I will give you some aspects to consider: Frequency: Some applications require more accurate frequency ...

2

I see nothing in the circuit that should stop multiple same-clock-cycle propagations if the circuit is fast enough? This is referred to as a hold time violation, and they are terribly fatal to a circuit. It doesn't happen because ASIC creators run expensive timing analysis software to check every single path in the design to make sure that the path is ...

2

In Logisim, a tunnel is just a hidden wire — all tunnels with the same name (in this case, "Tunnel"), are effectively connected together. When you try to force two instances of the same tunnel to different values, anything that tries to evalulate the value (including a third tunnel) will show an error. To create a new signal that is a logical OR of ...

2

The data that you shift in on SDI will be shifted out on SDO. You can optionally connect multiple of these devices in series: simulate this circuit – Schematic created using CircuitLab This means you only need a single data pin and a clock pin on your microcontroller to access all these device, all you need to do is apply enough clock pulses to ...

1

The interval between clocks allows signals to stabilize before the rising edge of the next clock. Between clock active edges, there may be logic devices that are not clock synchronized and need a few nano-seconds to settle on an output value before the next clock edge arrives on the logic devices that the non-synchronized devices feed. This is just an ...

1

I think you might be "in over your head" - this site is not really suited to leading people from zero knowledge of electronics to a complete solution, it's better at solving specific problems. Having said that, if you want to do this with discrete components I would look at 74HC160 (BCD counter) and 74HC4511. If you want to get something working from ...

1

Hmm, let's start w/ power first: 3072 * 20mA * 2.1 = 130 W! Your power supply can only give you about 5W. You're very much short there. If you can, greatly reduce the size of your matrix. One solution would be to use a desktop ATX power supply. Those have 5V lines through their hard drive connector and can give you lots of power. If you take the 5V you'll ...

1

You may have misunderstood some basics of electronics: The voltage doesn't define how long the circuit works. The current flowing through the circuit and the capacity of the battery defines how long the circuit will work. The capacity of a battery is defined in ampere hours. For example a Alkali-Mangan 9V battery block has a capacity of ~600mAh. When ...

1

I have two suggestions. use parallel case synthesizer directive and/or one-hot select coding. Try coding as onehot to balance the loading. This way each select signal has a ~164 fan-out load. This should help with the buffer tree and routing. always @* begin bcdIn_1hot = 10'b0; if (bcdIn<4'd10) bcdIn_1hot[bcdIn] = 1'b1; case (1'b1) // ...

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