# Tag Info

## Hot answers tagged digital-logic

20

Basically, from an electrical viewpoint, every "digital" signal is as you say, only an approximation of a square wave. In particular it will have finite rise and fall times. At high speeds, it can be difficult to ensure it looks as nice as the theory wants. To ensure that the signal is still detected as digital (i.e. the receiver doesn't get utterly ...

12

Those are small PCBs with a passive filter network in a single inline pin package potted with epoxy. The schematic on the far left within the dashed lines shows the components of a single board (notice, the pin-out for that part of the circuit is labeled 1-7), and it is not drawn for the others (presumably identical) to save space. You can replace them with ...

7

Any jellybean NPN transistor (2N2222, 2N3904, etc.) should work fine in this circuit. The manual is quite detailed in describing exactly what each circuit does. As Zuofu said, the 7-legged orange squares contain the passive circuitry shown inside the dashed line in the schematic diagram excerpt you show. One of these and a pair of transistors constitute one ...

5

The overal trick to the bi-decomposition solution is with identfying XORs. A 4 variable XOR of $X \oplus Y \oplus X \oplus W$ generates the below Karnaugh map (k-map). Notice the checkerboard pattern. Except the final row and column, it lines up with your k-map. Therefor we can use the 4 variable XOR as a base and mask the the undesired ones. With your ...

4

Digital signals are binary. They have only two states - on or off, high or low, up or down - whatever you want to call them. As you have deduced, there is some threshold above which the value is deemed to be high and another threshold below which the value is deemed to be low. Digital is very simple to do with transistors by either turning them fully on or ...

4

Can't count to 11 on 3 bits, so I presume you're actually using 4 bits. What you need to do is AND the two highest bits together, and feed that into the async reset of all 4 flip flops. This will reset the counter back to 0 very shortly after it reaches 12.

3

In effect, you're trying to recreate a color CRT controller with memory interface. This is perfectly possible, but it's much more involved than you realize. The physical implementation can be either an FPGA, as alex forencich suggests, or discrete chips. The discrete section will need something like the 74FCT series for horizontal timing, and can easily get ...

3

I'm not sure, but it seems they are used to switch off Q1 quickly. Follow my reasoning and see if it makes sense to you. First of all you should consult the datasheet for the controller chip BQ2031. It describes the chip operations and tells that its MOD pin is the PWM output that allows to control the charging cycle through (ultimately) Q1. At page 10 ...

3

Your power supply is backwards. Other than that, you are correct at an abstract level, i.e. assuming the gate voltages get high enough on "1". Every stage you have there is a NMOS inverter: IRF530 seems rated to work only at VGS above 4.5V, so in practice your circuit probably won't work with that 3.3V power supply (even if properly oriented).

3

Memories and peripheral IC's will typically have many locations that can be selected for reading or writing; in the example above, the 2K devices (EPROM and RAM) containing 2$^{11}$ (2048) memory cells require 11 address bits A0 thru A10. These are fed directly into the chip and are internally decoded to select the desired memory location or register. ...

3

Generally we design to prevent that happening. e.g. by only connecting the input of one gate to the output of another, or by only using low impedance sources to our gates. If we must allow less well defined voltages on logic inputs we can use gates with schmitt inputs (like the 74LS13), or take them to Analogue to Digital converters.

2

The Allwinner A13 does not have any Analogue-to-Digital-Converter (ADC) inputs. According the the User Manual: 2.8 I2C and SPI under Debian I2C and SPI are both supported in the latest Debian releases. There is respective kernel support for both. There is a python module called pyA13 might be found here: https://pypi.python.org/pypi/pyA13 It does ...

2

It is essentially a sort of parallel-set / serial-in / parallel-out shift register with a twist. It starts with 1000 (assuming four bits). When the comparator deems this value too low, a 1 is shifted in at the high side, when it is deemed too high, a 0 is shifted in. In both cases 1 bit of the result (the MSB) has been determined. Now the value is x100, ...

2

Collectively the network of Q2, Q3, Q4, Q5, R4, R6, R7, R8, R22, C4 and D2 are what you would call a gate-drive circuit. The purpose of such a circuit is evident in its name; in this case it is to switch the PFET Q1 by controlling the charging and discharging of its gate-source junction. Both Q2/Q3 and Q4/Q5 are wired as a Sziklai Pair in order to achieve a ...

2

Here are a few comments on the answers you got so far. Do NOT use discrete (74 family) ICs. You will need a large breadboard and a lot of wires. It will take you months to put the SRAM interface together plus the proper timing for VGA sync pulses. I did it once in my lifetime long time ago but today it's not worth the effort. Do NOT use serial bus to ...

2

I suppose it depends on where the x's are in the design. Take an example communication scheme within the chip. You may want to pass data around between two components, but lets say not on every clock cycle. You might decide then to have a data bus and a valid signal. The valid signal says when the data is valid. Because of this, whenever the valid signal ...

2

See this article Uncertain Circuits: When transistor 1 and transistor 2 are switched on, a coupled pair of inverters force Node A and Node B into the same state [left]. When the clock pulse rises [yellow, right], these transistors are turned off. Initially the output of both inverters falls into an indeterminate state, but random thermal noise within the ...

2

A more "analog" approach is to reverse-bias a PN junction into breakdown or avalanche. Doing so (from a high impedance) causes electricity to conduct fairly randomly, producing a white-noise output which is statistically quite random. This Article by Giorgio Vazzana has to say, "Avalanche noise is the noise produced when a junction diode is operated at the ...

1

The steps from diagram to circuit are: Create the state transition table state before (name, encoded) inputs (external, internal) flipflop input (T) flipflop output (Q) state after (name, encoded) Fill in states (before, after) regarding your diagram encode each state in the diagram. E.g. binary or one-hot Double all lines for each external input Fill ...

1

This is the perfect application for a small FPGA. It would be possible to implement a relatively powerful 2D drawing engine on the FPGA that can be controlled over SPI or I2C that can output full 8-bit color with a simple R-2R DAC. It would even be possible to have frame buffers that can be double-buffered or even composited on the fly. It would also be ...

1

For a good-quality computer video display, where fine vertical lines show the same contrast as fine horizontal lines, your video bandwidth should be able to pass at least the 3rd harmonic of the fastest square wave that appears in the image. The fastest square wave is alternating dark/light pixels, so its frequency is half the frequency of the dot clock. ...

1

set clk inhibit L, set Clear H, set parallel inputs. switch shift/load to L apply pulse to CLK switch shift/load to H apply pulses on CLK

1

You used the switch model to describe how AND and OR gates work. Your model just works with closing switches (closer). The switch model has also the opening switch (opener). So a NOT gate can be modeled by an opener by connecting the input to the supply voltage and the output to the gates output. To be more precise: Your two switch replacement circuit for ...

1

Consider CMOS inverter: whenever A is 'Low'/'0', NMOS is off and PMOS is ON which cause Flow of Vdd to output making it high. You are probably thinking that if input is low then how can ouput be high i.e. how gate got the input power to make it high. Answer is that transistors always has Biasing.

1

This question is all about the required input levels into a logic device The minimum value for $V_{IH}$ is the guaranteed value for a "1". In other words, if you equal or exceed this level the input circuit will definitely recognize it as a logical 1. Typically it might work a bit lower than this. As for $V_{IL}$, the maximum value is that input level ...

1

In figure (a) the part of the address bus that addresses the locations/registers inside the individual chips is not shown. For example the first two memory banks have 8K(=8192=2^11) locations that must be addressed using the lower 11bits of the address bus (not shown connected) they only show the decoding network for the chip select pin (/CS). Again, the ...

1

You've gotten confused here, a bit. This article explains things, but I'll also do it my way. The two levels you've specified are output levels. A TTL gate which is not being abused will output either less than 0.4 volts or more than 2.6 volts. But this is only half the story. TTL is only guaranteed to operate correctly for inputs of less than 0.8 volts ...

1

Does that mean the first decoder has 4 inputs and 16 outputs ? No, it means the whole circuit you are designing has 4 inputs and 16 outputs. If so why the answer to this question has for the first decoder a 2 inputs and only 4 outputs Because your instructions are to build your circuit "using 2-to-4 decoder[s]". You need to use 2-to-4 decoders as ...

1

To answer your actual question, no, the output of a gate is never "Z", unless it's specifically designed as a tristate gate with an output enable. In general, inputs to gates that are "Z" are treated the same as "X", and the output is either "0", "1" or "X" as appropriate. For the specific case of the XOR with its inputs tied together, your original ...

1

Here an explanation of an example of the SAR register circuit in page 46.

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