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6

You can implement the ON Semi circuit with only three small packages. Two 74HC74 dual D flip-flops and a 74HC02 quad 2-in NOR gate. There's a FF left over so you could also get 4MHz or 12MHz simultaneously. Recall that an AND gate is the same as a NOR with each input inverted, so just use the Q outputs rather than the /Q outputs for the AND gate. You ...


5

In circuit B, if your output voltage draws any current, it can significantly load the voltage divider and cause your output voltage to change far away from the intended value, in this case, 3.3V. Even when your output is connected to a high impedance pin, if your R1 and R2 values are very high, very small amounts of quiescent current can still change the ...


3

You can do this with an analog switch like the 4066 and an inverter like the 74LS04. As Spehro Pefhany pointed out, pullups are needed to guarantee the outputs of the 74ls93 and 74LS04 are high enough to enable the 4066. You may have some spare inverters (or NAND or NOR gates, which can easily be made into an inverter) already in your circuit, in which ...


3

What justinrjy says, plus circuit A draws no current when Vin is low / Vout is high. In many cases (example : UART, i2c...), that's most of the time: significant savings for battery-operated circuits. You can of course use circuit B with high resistor values, so that the permanent current draw is negligible; but then load impedance and electronic noise does ...


3

You can tie the input to ground, directly or through a jumper (jumper is useful if you want to change something later). Tying an input of an 'OR' gate to logic '1' would not make much sense since the output would always be high, but if you want to do that, it's good practice to use a series resistor of about 1K with LSTTL (practice from TTL days). If you ...


2

Assuming you mean that you have an analog voltage at the input to a digital gate, then (as already noted) it will sense a 'low' from Vss (usually ground) up to some threshold and a 'high' between some other voltage and Vdd (some positive voltage for most families of logic). Between these voltages the input is indeterminate; i.e. what the input is sensing ...


2

General guidelines being given are generally OK BUT You MUST NOT exceed Vdd with any sort of drive capability. The 3V9 you quote is an ABSOLUTE MAXIMUM value and your controller may well go gaga if you apply that during operation. Look at data sheet in 'typical operating conditions' section and see what limits there are. In a very few datasheets, probably ...


2

The pulldown resistors that you are using is on the high side for one LSTTL pin and probably beyond acceptable when used to pull down two pins at once (see explanation at end). A lower value of resistor should be used. However - this does not properly explain the problems that you are seeing. THe following procedures will help you establish whether the IC is ...


2

Well, I've never heard of such a gate, however Newnes Dictionary of Electronics By S W Amos, Roger Amos) has. Fine, but I also have no idea what an IF-THEN gate might be! Fortunately, they do. So, it's like a NAND gate with an inverter on input 2. You should be able to take it from there.


1

I think you need to make two changes to the circuit. Firstly to mix the four signals together, then to bias the amplifier so the signals mix linearly. 1) To mix the signals together, you can just use a resistor from each of the four digital outputs, all connecting at the base of Q1. If you make each resistor 3k9 or 4k7, you will get a similar impedance to ...


1

If a pull-down is required (I don't see a schematic) then 10K is too high a value. Maximum input voltage for a '0' is 400mV (for 400mV noise margin, as usual). Maximum input current IL is 0.1mA (see the datasheet). Therefore the pull-down resistor for a single 74LS inout should not exceed 4K. If 'n' inputs are connected to the same pull-down the maximum ...


1

The requirement for maximum +/-300nA input current means that you have to clamp the input voltage to within about +/-100mV of the supply rails (depending on temperature range). If you really need this spec (for example to ensure normal operation during input spikes) then you'll need better clamping than a few resistors and diodes can provide. I suggest a ...


1

This is all you need: simulate this circuit – Schematic created using CircuitLab this also eliminates the problem that a high voltage at the input will lift-up your local VCC. When input < -0.6 V D1 will conduct and limit GPIO to -0.6 V, R2 limits the current, your GPIO input will be able to handle this (it also has input protection diodes ...


1

It's probably caused by noise on the digital ground. One solution is to use a series diode as so: simulate this circuit – Schematic created using CircuitLab That will prevent noise on the digital ground relative to the amplifier ground of less than a couple hundred mV from being heard.


1

As a derivation of tcrosley's answer, the PIC18F2550 (24Pin SOIC or DIP) has a nice PLL block. This can take a 24MHz input, prescale it by a factor of 12 down to 4MHz (PLLDIV=111), feed that into a PLL which will step it up to 96MHz, then feed that through a postscaler with a factor of 6 (CPUDIV=11) to make 16MHz. This can then feed the Timer1 module which ...


1

Use a PLL (phase locked loop) to multiply the original frequency by 2. This allows dividing by 3 that doesn't need to be square, then followed by a divide by 2 to yield a square output.


1

I assume since your circuit says it is using 7404, and not for example 74LS04 etc then it is really classic 7404 TTL. So you are right, according to the datasheet the range for a low input is 0v to 0.8v, and a high from 2v to Vcc or 5v. So, any input up to 0.8v is guaranteed to be a 0, and any input 2v and above is guaranteed to be a 1. As you point out, ...



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