# Tag Info

13

Actually your first guess is not as afar off as some are claiming. A CPU is built around something called an "Arithmetic Logic Unit" (ALU) and a simplistic implementation of that is to have the logic gates implementing all basic operations wired up to the inputs in parallel. All of the possible elementary computations are thus performed in parallel, with ...

10

Can An Operational Amplifier Circuit Be Made Entirely Out Of Diode Nand And Nor Gates? This apparently simple-enough question is somewhat ambiguous and can be answered several ways. Spehro has assumed that you convert the input to a digital value and perform digital arithmetic on it. So he says the answer is yes. ScottMcP takes your question at face ...

8

What that snippet seems to be talking about is restricting the propagation of noise generated inside the microcontroller (or other similar clock-based chip) into external circuitry. To that end the recommendation in that document is not just to add a series resistor, but to form a low pass filter close to the chip using a series resistor and parallel ...

7

Pretty far off. A CPU is made up of real gates (not programmable LUTs). The key operations on data are done in a block of logic often known as an ALU (arithmetic-logic unit). Inside this block is a set of gates that can, for example, AND two operands together, bit-by-bit. There's another set of gates that can add them together, and so on. When you execute ...

6

Nice to see a proper testbench and code that actually matches the question for a change... There are two easy ways for a signal to be corrupted: drive it from several signal sources don't drive it from any Now A11 remains 'U' throughout, suggesting it has no driver. While A1 alternates between valid and 'X' invalid values, suggesting it has more than ...

6

Trying to define what is the "most important" element of a circuit is pointless. As for what a logic gate is, it's a circuit that operates on signals with discrete states. Overwhelmingly, this is done using two states only, high and low. There are good electrical reasons for why two states is much easier to deal with and operate on than multiple states in ...

5

A possible alternative is to use one of the newer FPGAs with high speed transceivers (5 to 10Gb/s). These are intended for fast Ethernet, SATA and other high speed serial interfaces. They are relatively cheap, common, faster than the aforementioned ECL device, and internally deserialise (presenting a serial stream of bits as a parallel word). I understand ...

5

Other answers have focused on why you might be approaching this the wrong way. Although I agree with those answers, what you're asking for does exist, so I'll go ahead and give you a straight answer. You'll likely find that this approach is more expensive than alternatives though. What you want is a 2 GHz voltage-controlled oscillator (VCO) with 3.3-V ...

4

Every transistor has a current gain, usually $\beta$ or $h_{fe}$ in the datasheet. Typical values are on the order of 100. When the transistor is not saturated, then the base current and collector current are related by this factor: $$I_c = h_{fe} I_b$$ When the base current increases to the point where collector current can increase no more, the ...

4

The heart of the operational amplifier is the difference amplifier, where a current is divided between a pair of highly matched input transistors. This is what allows high gain combined with low offsets. Logic gates simply don't have the geometry to do this. So the answer is no. That said, logic inverters (and by extension almost any inverting gate such ...

4

Just as a starting point, you may want to consider looking at "time-of-flight" range finder circuits using LASER. Considering RF and light travel at the ~same speeds, I would suspect that the time counting sections would be a good comparative match. A quick google search for "laser range finder circuits" shows a schematic on Parallax.com as the first ...

4

The most positive input of the differential pair must be within that voltage range. In the case of this chip, it varies from Vee+2.0V to Vcc, so for a 3.3V Vcc (PECL) it will be 2V ~ 3.3V. (the diagram below is for Vcc = 5.0V rather than 3.3V) I don't see Vpp specified in the datasheet for that chip, but it's usually 150-800-1200mV ...

3

As Nick states, it is a transmission gate. Think of a TG as a switch that can connect or disconnect the horizontal line. As Ignacio states, in this particular case the TG is used to disconnect the external pin from the digital input synchronizer when the chip is in SLEEP mode. Note that at the same time that input is grounded by activating the FET. ...

3

Frankly, SPI interfaces are better suited for isolation than I2C. You can set the master clock to a frequency where the timing works out reliably. I2C is a bidirectional bus which makes isolation a pain. If you insist on using isolated I2C, AN-913 from Analog Devices is an application note that illustrates how:

3

A few arguments: with HC and HCT, the fan-out (at lower frequencies) is essentially unlimited, for LS it s IIRC 10 (or was it 20)? the HC and HCT families are newer than LS, so my bet would be that they will be around longer than LS HC and HCT use much less current than LS (except maybe for a few gates that switch at a very high frequency), which eases the ...

3

First, the inversion of the outputs simply means that the output is active low. That is, for an input of 0000, the 0 output is selected, and it is driven low. All the other ouputs stay high. The NAND gates are used because, given that the active lines on the 74154 are low, DeMorgan's Theorem allows NAND gates to function as OR gates. That is, if the 74154 ...

3

Sure, if you have digital numbers for the input voltages an op amp merely does the calculation Vout = Av(Vin+ - Vin-). Easily done with gates (and either NAND or NOR gates would be sufficient). NAND and NOR gates require more than just diodes, they require transistors, of course. OR and AND gates are not sufficient. If you do the calculation ...

3

One of the simplest op-amps looks like this: simulate this circuit – Schematic created using CircuitLab And you can build it using NAND gates: simulate this circuit simulate this circuit So the answer is YES. Keep in mind that this will be crap, and will operate only over avery narrow range. The primary tool for operation that ...

3

The concept looks sound. The main thing I see is that your 5.6K resistor is way too high to guarantee a low level for a 'LS04. The 100 ohm resistors you used elsewhere are okay (but they'll get warm if the switch is held). Suggest you use ~150 ohms for the pull down resistors and maybe 4.7K for the LED resistors. It would be better to use a spare ...

3

Although you have already selected Spehro's answer, I thought you ought to learn a little about using LS series ICs. LSTTL, like regular TTL, has an input which is essentially an NPN transistor with the emitter exposed. It also has an output which, while it can drive both high and low, is much stronger pulling low than driving high. This makes sense, since ...

2

Read your error report carefully: it complains about an output, 4.Q, tied to another "output", A:5. The simulator complains because you are likely to drive your input A with some values, but flip-flop four is also quite likely to drive that same exact node with its output. What if A wants to drive a 1 while Q.4 wants to drive a 0? That's not acceptable for a ...

2

Look at this bit: Step 3: (mo + m1 + m9 + m11) * (m9 + m11 + m13 + m15) Only two possible input conditions can cause this to evaluate true: m9 (WX'Y'Z) and m11 (WX'YZ). WX'Z

2

Many TTL parts and older memory chips have active low enable inputs, so the active low outputs of this part can be connected directly to those inputs. There are probably two enable inputs because otherwise there would be two unused pins on the 24 pin package (I don't recall seeing 22 pin DIP packages).

2

The active-low output is just how the design for that specific decoder was carried out - there is also active-high varieties. As for the NAND gates, there is a function being implemented in which the gates are there to realize it. For instance, f1, will be LOW (because all non-selected outputs are HIGH) unless the decoder selects output 2, 4, 10, 11, 12, ...

2

Transistors are the foundation blocks of computers and embedded systems. TTL is used to refer usually to an electronic circuit that uses transistors for both the logic function (whether to be on or off) and the amplifying function (usable currents and voltages), or more colloquially to binary voltage levels of 0V-5V (because this range is what TTL dedicated ...

2

Positive feedback circuits (e.g. a Schmitt trigger) are in unstable equilibrium, the same as a ping pong ball on top of an upside-down plastic cup. You only have to move the cup one way or the other a little bit and it wants to roll off. Assuming the cup has a large lip and the ball doesn't roll off the end, then you can make it go the other way by moving ...

2

Control systems: OPEN LOOP CLOSED LOOP (Feedback) 2.1 Positive feedback 2.2 Negative feedback FEEDFORWARD

2

An operational amplifier must have gain. There is no way to get gain out of diodes.

2

Welcome to the forum. To begin with, I hope you know what you're doing. Messing around at GHz speeds is not for the faint of heart, or those with shallow pockets. The most obvious way to get a clock is to start with a 1.4 GHz sine wave oscillator, and use the circuit here to convert it to ECLinPS. Once that is done, you will need to look at other chips ...

1

The practical FPGA register (a set of D flip-flops) only has one clock pin so it serves exactly one clock domain. Keep this low-level hardware in mind when writing HDL code. When a signal crosses from one clock domain into another, it's common to use a pipeline of three registers, with the first stage in the source clock domain and the second and third ...

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