# Tag Info

## Hot answers tagged digital-logic

19

One line of reasoning I always used for logical AND and OR signs is their relation to mathematical operations they represent. Let's start with logical AND. It's often represented as multiplication sign, for example *. So if you have a long expression like s1*s2*s3*s4.... and one of the variables takes value of 0, or logical false, then the entire expression ...

12

The answer is the inverse of X0 i.e. $Y = \bar{X_0}$ It's clearly this because if $X_0$ is 1 then the number is an odd number. Sometimes you've just got to look at the truth table without thinking much about boolean algebra.

11

One word: Distributivity Multiplication is distributive over addition, and so is logical AND distributive over logical OR. On the other hand, multiplication is often used without a symbol (2a instead of 2*a), and logical AND is very similar. If both A and B must be true, it's simple and intuitive to write AB. It is very handy in constructing truth tables ...

10

Of course there's an external power supply. Take a look at a NOR gate chip (say, 74HC02) and you'll see it there clear as day: Logic symbols purely show the logic flow of a circuit, not the power flow. Many schematic capture programs will take the power connections as read and automatically connect them to the right nets for you. Internally a typical ...

7

In today's world with many decent choices of hardware design suites with HDLs (Hardware Description Languages) and Digital Circuit Optimization and Minimization there is no real need for small topology logic design as offered by Karnaugh maps. On the other hand there are two pretty useful areas where they come into play. A) One area is in the training and ...

7

With synchronous counters the delay occurs while the clock is inactive (unchanging, or an inactive edge). When the next active edge arrives at the clock inputs, the data inputs are already stable. Hence all outputs change at the same moment, which is the essence of the system being 'synchronous'.

6

Of course there is an external power supply (as you suspected). Here's a quad nor gate: - Notice pin 7 and pin 14 The same sort of thing is done with op-amps - they don't necessarily show the power pins because they are assumed folk know they are there: - But once you've learned about them you realize the basic op-amp has power pins (normally 7 and ...

5

simulate this circuit – Schematic created using CircuitLab You could put a little 10mΩ or 100mΩ resistor (called a shunt resistor) in series on each power input path before the diode, and use a dual package general purpose op-amp and using two of these, monitor the shunt resistors independently. When some arbitrary current is flowing through the ...

5

2B Or NOT 2B - That, is the question! Implement with a NOT gate, and a dual-input OR gate. You're welcome :)

5

Michael Shcroeder's "A brief history of the notation of Boole's algebra", Nordic Journal of Philosophical Logic 2 (1):41-62 (1997), attributes use of + to represent inclusive-or to Leibniz in his "Elementa Calculi", and discusses Boole's use of the notation, as well as some other notations. online link

5

12.5 Mhz (80 ns cycle) should be doable. Wire up your clock lines first. Pick placement that keeps them short and cut the jumpers to length so that you don't have big loopy antennas. Verify that you are getting nice square clocks before wiring the rest.

4

The other answers have addressed part of the question, but it may also be worth noting that the power supply connections are often omitted from schematics (especially conceptual rather than practical ones) such as the RS latch of the question. One also often sees OpAmp circuits where those connections are not mentioned, but rest assured that real parts do ...

4

Your circuit needs to be started in a known state, and if the default is to be with the 4013's Q low and both 4017s' Q0s high, then to that end I've taken the liberty of redrawing your circuit, below, to include the Power-On-Reset using diodes to make it compatible with the rest of your diode logic. Note that your R5 isn't needed since the diodes are being ...

4

For each 16 bit device (other than the final one) put a single D type flip flop on the output and use it's output as feed to the next 16 bit device. The d type will soak up each 17th bit or, looking in a different way, the d type makes the 16 bit device a 17 bit device.

3

It is easy to go through these circuits. Lets say that on the left side of the first inverter is a logic value of 1. This value is inverted and is 0 at the left side of the second inverter. This will become a value of 1 on the left side of the 3rd inverter. After the 3rd inverter the value is 0. this value is also on the left side of the first inverter. ...

2

You are asking for help adding an LED indicator, but there are some other problems with your circuit. The Pi can become unstable when it is given less than 5.0 volts, and the 1N4007 diodes have a 0.8 or 0.9 volt drop. One solution is to use Schottky diodes such as the 1N5820 which have only a 0.3 volt drop. An alternative to diodes that would provide better ...

2

I'm afraid your assumption is not entirely correct. If a datasheet doesn't give a guaranteed initial state, which standard HEF40** device sheets intentionally don't, there is no guarantee. The decade counters in fact hint at the fact that they start with the value you assume if, and only if, the master reset has been triggered. The only thing you can ...

2

This is normally solved by a dedicated /RESET pin on the IC that can be pulled low to bring the IC into a predictable and useful state. This line is usually driven by the power supply for as long as the supply voltage isn't stable, and can be used again if the system goes into an invalid state. This state need not necessarily have defined states for all ...

2

Gate delay causes it to ripple. While the first one is receiving the output of the last one, the middle one is propagating the output of the first one, and it will continue like this forever. The logic in general will cause this toggling, because it would go 1:0:1, or 0:1:0 and would constantly oscillate between these states.

2

No discussion of why is is common to use + instead of ∪,∩,∨,∧ would be complete without noting that printers and tranmission codes (such as Baudot, ITA, and ASCII) provided the Alphabet, Numbers, and 'common business symbols'. It's hard to imagine now, but there was a time when special symbols were not easily represented on input, and represented an ...

2

My suggestions would be (expanding on what Jeff has suggested): Make sure you run a ground from a pin as close as possible to the clock pin to another pin as close as possible to the clock pin. Twist the clock and ground wires together. Keep them as short as possible. Do you have a good high bandwidth scope to check the clock with, so you can see any ...

1

Addition and subtraction have inverted constants $C_{in}$, we can be connected to $(I_3 \vee I_4)$. Then invert the subtracting value before passing to a full adder. ADD/SUBR/SUBS can be expressed as : $$(R \forall I_3) + (S \forall I_4) + (I_3 \vee I_4)$$ Using the same xor inversion method you can mearge: AND/NOTRS : $(R \forall I_3) \wedge S$ ...

1

So you want to be able to display the ALU result both before and after it is stored in memory, and be able to load that result into the ALU's a or b input? Connect all the data lines together to form a bus. Obviously this bus can only carry one 8 bit value at a time, so each device connected to it needs an input register (8 bit latch) to write (STORE) ...

1

You can shift it like this if you don't have the center voltage already available: simulate this circuit – Schematic created using CircuitLab Or like this if you do: simulate this circuit You may recognize it as a highpass filter, which it is. In signal processing, DC (constant offset) is 0Hz, and is considered a frequency just like ...

1

In the last few pictures, it looks like you've configured the "sub flag" as an output, not an input. Since there's nothing driving that net, it's resulting in an error.

1

The solution to this problem cannot be found by just trying all possible logic gate . It might be a bit complicated to understand. POS of F(A,B,C,D)=0,3,4,7,9,10,12,15. convert to SOP. SOP of F(A,B,C,D)=1,2,5,6,8,11,13,14. when A is 1 give us total 8 possibilities out of which the 4 which we are given have the property of even number of ...

1

You must assert Reset on power up. Create a signal and call it POR. (power ON reset) It is customary to generate this with an R pull-down and C pullup to V+ to any CMOS input. Then use correct output polarity to feed all memory cells ( incl. FF) as required. CMOS is usually positive Logic, so 1 for Reset requires a non-inverting reset gate. The RC time ...

1

Without knowing the exact details regarding the circuit connections that the switch was connected to it is not possible to give a generic answer as to what semiconductor components could replace the switch. What you can do though is to select a relay that has contacts with ratings similar to the switch. Ratings being the current carrying capacity of the ...

1

There's a very compact part (generically an H-bridge or motor driver) that provides this function, but soldering it might be your Waterloo: LB1930MC (pins are 1mm pitch). It will also perform the level shifting, but if you want to drive it with a single output you'd need to add an inverter or use two port pins. It was really björn to drive motors, but it ...

1

The device you're looking for is called an H Bridge. They are frequently used to drive motors since they switch the power to either polarity which allows control of direction of rotation. Since you need very low losses, you need to find one built using MOSFETs instead of BJTs. TI's Selection Digi-Key, PMIC - MOSFET, Bridge Drivers - Internal Switch: ...

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