# Tag Info

## Hot answers tagged digital-logic

9

This may not be what you are looking for as far as getting insight into a regular multiplier circuit, but you can implement this easily with just a ROM. All you need is 64 memory loctions, each 6 bits wide. You load the ROM with answers to each of the possible 64 input cases, and the rest is a lookup. This may sound dismissive, but actually small ...

7

If you're a EE/CPE student and you're just starting to learn logic, maybe you haven't learned this yet but you will. Arithmetic and logic functions are essentially realized in circuit form by starting with a truth table and filling in the values that implement the function you want. For 2x2 bit multiplication, this is the truth table: From the program ...

6

Write the multiplication down and you'll know what to do. For example A1A2A3*B1B2B3 A1 A2 A3 x B1 B2 B3 ----------------------- B3A1 B3A2 B3A3 + B2A1 B2A2 B2A3 B1A1 B1A2 B1A3 As you see, just multiply each bit (which is accomplished by an AND) then add them together using full adders You can reference the way ...

4

When the 8085 starts up, it will start fetching instructions from address zero. It is thus necessary that the memory which is located there contain defined contents. That does not imply, however, that address zero must be mapped permanently to ROM. One could build a system with e.g. 2K of ROM, 64K of RAM, and a floppy drive, and use an I/O bit to control ...

3

Master-slave just a way of combining two gated or level triggered latches together to form an edge-triggered flip flop. A master-slave D flip flop is just one way that you can build a D flip flop. The idea behind a master-slave flip flop is that you can connect two latches back to back so the 'master' latch will update while the clock is low and the ...

2

I suspect you mean what can you do to the 2 inputs to get equivalence at the output. Well the short answer is you need also to put an invertor on the output. Thie is deMorgan's rule: - Basically, if you invert the inputs and outputs of an AND gate you get an OR gate. Likewise if you do the same to an OR gate you get an AND gate (that should be obvious ...

2

To make the NAND gate act identically to the NOR gate you have to attach an inverter to each input of the NAND gate and an inverter to the output of the NAND gate. To make the NOR gate act identically to the NAND gate you have to attach an inverter to each input of the NOR gate and an inverter to the output of the NOR gate. In order to understand why ...

2

The basic hardware sorting element is a module that has two inputs and two outputs. It contains a comparator and two multiplexers, and presents the smaller of the two inputs at one of its output ports, and the larger at the other output port. There are many ways to use such a module to sort a list of items, with a wide range of space-vs.-time tradeoffs. At ...

2

The lower K-map is wrong: A 0 0 1 1 D 1 0 1 1 c 0 1 1 1 B It can better be drawn as: A 0 0 1 1 0 _ _ _ _ 0 D 1 _ _ _ _ 0 1 _ _ _ _ 1 C 0 _ _ _ _ 1 0 1 1 0 B The goal is to have a unique combination of variables for each cell in the matrix. It doesn't really matter which variable goes where, as long ...

2

At first glance, this appears to be a power problem. It appears that your "5 V" power supply droops to less than 4 V in operation. Perhaps the power supply is inadequate. So power your circuit from some other wall-wart or other power supply that can supply at least 10 times as much power as you think you need (at least 10 times as much current at 5V). ...

1

It's just a gate to clean up the waveform (or just to indicate that there is a logic output driving the input)- it would not generally be used if you were employing a clock oscillator nearby the MCU such as this one (photo from Digikey.com). You could use a ST gate such as this one, but usually it's not necessary.

1

When you enable an interrupt on one of the 8085's RST5.5, RST6.5 or RST7.5 pins you will get behavior as follows: RST5.5 is a maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 2Ch (hexadecimal) address. RST6.5 is a maskable interrupt. When this interrupt is received the ...

1

Your question is a bit vague — can you provide a specific example? But in any case, the general concept is that an RC high-pass filter will convert a rising edge into a narrow positive pulse and a falling edge into a negative pulse. The negative pulses can be inverted to create a second set of positive pulses that's offset in time. Essentially, you ...

1

The standard adder / subtract circuit is given by the figure below.For an explanation of how it works please see my previous answer here : Subtraction using adder circuit Now notice that if you were to change the input that is tied to '0' to Cin, then the circuit would now perform the operation: A + ~B + (Cin ^ SUB), meaning that: 1) it would be a ...

1

If you use level-triggered flip-flops (without a two-phase, non-overlapping clock) then all of the flip-flops will be transparent at the same time. The input to the first flip-flop will propagate all of the way to the output of the last flip-flop whenever the clock input is asserted. By the way, I think it is better to call a level-sensitive storage element ...

1

The inputs of TTL logic gates are emitters of NPN transistors. They are current sources so when not connected they act as High level or logic "1", so your AND gate sees two high inputs, and naturally outputs a High. It is good practice to connect inputs you want to be high to the positive supply, either directly or through a resistor. For the inputs to ...

1

Well, to consider your basic question: what is the minimum number of full adders required? You have initially twelve partial products (bits), while your result has six. Each fully utilized full adder will remove one partial product (bit) and therefore you need exactly12 - 6 = 6 full adders. Then, given that you do not use half adders, there may in practice ...

1

The inputs need to be actively pulled-down for them to operate: - Notice the PNP transistor will not be turned on unless a current is taken from the base to GND. To be sure, if you are using switches, use 10k pull-up resistors (as indicated in the data sheet) and the switches should ground the inputs to activate them.

1

Why don't you look for an analogue multiplexer that can run from a 12V power supply and has low on-resistance and can take the current for one LED. You haven't stated the LED current so this approach may not yield a definite result. This one might work for you: - If you use the correct package 200mA is the max current but you might be able to current ...

1

for NAND gate implementation... simulate this circuit – Schematic created using CircuitLab for NOR gate implementation simulate this circuit

1

It's not that hard, you just have to apply De Morgan's transformations, as mentioned in the comments. Take this into account: $\overline{\overline{A}} = A$. $\overline{A+B} = \bar A \cdot \bar B$ and viceversa $\overline{A \cdot B} = \bar A + \bar B$ and viceversa From that you only need to apply these transformation until you get the result ...

1

I am not familiar with the SOP and canonical terms since I did not study electronics in English, but this seems about Boole logic stuff. May I suggest you took a look there : http://sce.umkc.edu/~hieberm/281_new/lectures/forms-of-bool-expressions/forms-of-exprs.html and there : How to convert an expression from SOP to POS and back in Boolean Algebra? for ...

1

If you are making a decimal counter and decoding it, a Johnson counter uses 5 rather than four flip-flops, but can be decoded to 10 outputs with only 2-input gates for a net saving in CMOS technology. Below is an example from the CD4017 datasheet.

1

The leftmost column, S, is the current state. The next four columns are for indicating what state you would be in if inputs x and y were to be 00, 01, 10, or 11, respectively. The two right columns are the values of outputs z1 and z2 are for any current state. Look at the diagram and see that z1 and z2 in the diagram match what z1 and z2 are in the table ...

1

Your question appears to be premised on the use of an NPN transistor as the fundamental switching element used to construct the logic gate or function. Ubuntu_noob has shown the three functions (NAND, NOT, NOR ) created with NPN-only devices. However, if the fundamental element is changed from an NPN transistor to a PNP transistor, or NMOS transistor, or ...

1

The premise of your question is false. Here's an OR gate with zero transistors and two diodes: simulate this circuit – Schematic created using CircuitLab This isn't an especially good OR gate, but it is one. It doesn't have any voltage gain, for starters. It can be the case that some logic designs require three transistors for an OR gate. This ...

1

Assuming that your circuit works, and I'm not going to bother to find out, it isn't a fundamentally different circuit from an SR latch. You've removed the !Q output, so one of the feedback paths in the latch now looks like a feed-forward path. This seems intuitively true because you have shifted the OR gate to the right, so the path from the bottom AND gate ...

1

To make a T flip-flop, you take a D-flip flop and add feedback from the output to determine the next state. The immage bellow shows the most basic operating logic of a T flip-flop. If you removed the feed back from Q and Q' you get a D flip-flop (And I know, you also have to invert the bit input on the lower and gate. Lets keep it simple, ok?) So when ...

1

The D type flip flop needs feedback from its inverted Q output to divide frequency by two. That's the short and long story: - The way a D flip flop works is simple. Positive clock edges latch the state of the D input at the time the edge rises. Therefore by the time the QBAR output has changed state (some few nano seconds later), its previous state has ...

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