New answers tagged digital-logic
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After looking at the datasheet, the part normally pulls 60-70mA at 5V, dissipates 350mW. This will be warm to the touch, not hot. Not sure why you're using an old TTL device, newer fast CMOS parts have standby currents in the 100uA range.
You mention adding a resistor to gnd, what's the other end of the resistor connected to?
You may float TTL inputs, ...
2
Implement your debounce like this to fully eliminate the effect of the switch contact clatter.
Captured courtesy of this site.
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I cannot give a detailed answer, but if you are thinking that ACFG fills a LUT and therefore you cannot combine any other term into the LUT, then I think you have to break the pattern of thinking that equates a 4-input AND term with a 4-input LUT.
To get you started : looking at ACFG, you may note that CF is shared with another term, and so is AG. So you ...
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There is an obvious simplification:
\$ C + B'CD'F = C \$
Which makes the function a lot smaller by eliminating a redundant term:
\$ h = A.B′+C+B.C′.D+B.E \$
The result \$ h \$ is not dependent on input \$ F\$.
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In Logisim, a tunnel is just a hidden wire — all tunnels with the same name (in this case, "Tunnel"), are effectively connected together.
When you try to force two instances of the same tunnel to different values, anything that tries to evalulate the value (including a third tunnel) will show an error.
To create a new signal that is a logical OR of ...
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Some ideas for you
First things first - you need to detect how fast the servo is running. This can be done in several ways. Typical solutions are:-
Optical slot (disc with hole (or holes) fixed to shaft, LED/OPTO Transistor combo to pick up rotation - output a pulse every time light passes through hole
Reflective - same sort of idea but pick up from ...
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You are right. Edge triggering is just a much narrower form of level triggering, and depends on timing. Inside an edge-triggered device, the changing clock edge is just turned into a pulse which causes it to accept the inputs: a level trigger! But the level trigger is very short. It must be so short that the outputs are not able to propagate back to the ...
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What's important about a clock signal? All of it, of course! :)
But seriously, there are many aspects to a clock signal and it is difficult to limit it down to just a couple of things. It also greatly depends on what you are doing with it. Below, I will give you some aspects to consider:
Frequency: Some applications require more accurate frequency ...
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I see nothing in the circuit that should stop multiple same-clock-cycle propagations if the circuit is fast enough?
This is referred to as a hold time violation, and they are terribly fatal to a circuit. It doesn't happen because ASIC creators run expensive timing analysis software to check every single path in the design to make sure that the path is ...
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The interval between clocks allows signals to stabilize before the rising edge of the next clock.
Between clock active edges, there may be logic devices that are not clock synchronized and need a few nano-seconds to settle on an output value before the next clock edge arrives on the logic devices that the non-synchronized devices feed.
This is just an ...
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I think you might be "in over your head" - this site is not really suited to leading people from zero knowledge of electronics to a complete solution, it's better at solving specific problems.
Having said that, if you want to do this with discrete components I would look at 74HC160 (BCD counter) and 74HC4511. If you want to get something working from ...
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Hmm, let's start w/ power first:
3072 * 20mA * 2.1 = 130 W!
Your power supply can only give you about 5W. You're very much short there.
If you can, greatly reduce the size of your matrix.
One solution would be to use a desktop ATX power supply. Those have 5V lines through their hard drive connector and can give you lots of power. If you take the 5V you'll ...
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The basic idea in these kinds of problems is that your D flip-flops represent your state and you need to create some combinational logic that takes as input the current state and generates as output the next state.
So first you create the truth table:
input output
D2 D1 D0 | D2' D1' D0'
0 0 0 | * * * # actually, don't care is not quite ...
2
Think of your special counter as a state machine. Then assign the state the coded value of the count sequence that you want. In this case the states would be as following with the next state showing.
State Next State
3 -> 1
1 -> 4
4 -> 7
7 -> 2
2 -> 3
Each state can be encoded into three binary bits so your design will require ...
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It sounds to me that when a switch is open, you have a floating logic input. Logic chips, in general, do not like to have floating inputs and this can produce results like you see (gates half-way on).
Try adding pull-down resistors to your inputs, for example 4.7K between the input and ground. This guarantees that an input always sees a valid logic state.
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You may have misunderstood some basics of electronics: The voltage doesn't define how long the circuit works. The current flowing through the circuit and the capacity of the battery defines how long the circuit will work.
The capacity of a battery is defined in ampere hours. For example a Alkali-Mangan 9V battery block has a capacity of ~600mAh. When ...
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You did not mention a few important factors:
what is the current (and less important, the voltage) you want to switch, and is your load resistive or inductive?
what is the gate voltage your FET needs to switch fully on, and does that match the voltage your 555 runs on?
at what frequency do you want to switch
A small current (let's say 100 mA) can often ...
3
Use a Comparator
"Digital" NOT gates (inverters) are comparatively weak, since they are not designed to drive big loads. In the more general case, you want a circuit topology known as a comparator.
A comparator compares the input voltage to a reference and outputs one of it's maximum extents (as close to its positive or negative supply as it can get) if ...
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"logic chips are always hard ON or OFF" - This isn't exactly true. They do a good job forcing inputs to either logic 0 or 1, but if you have a slow, sloppy input transition, than you'll get a somewhat slow output transition as well. The transfer of an inverter looks kind of like an S curve:
I doubt that this will give your downstream circuit any problems, ...
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I have two suggestions. use parallel case synthesizer directive and/or one-hot select coding.
Try coding as onehot to balance the loading. This way each select signal has a ~164 fan-out load. This should help with the buffer tree and routing.
always @* begin
bcdIn_1hot = 10'b0;
if (bcdIn<4'd10) bcdIn_1hot[bcdIn] = 1'b1;
case (1'b1) // ...
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The code you have will create 167 10-1 mux with an output enable, which means you will have 2 CLBs for each bit of your output bus. Since most FPGAs have 5 or 6 input LUTs, you will need at least 2 of them for each mux, which means you will have close to 400 LUts just for the mux and probably much more because of the routing congestion inside an FPGA.
What ...
3
The question seems rather confused in several respects...
1) It is unclear whether you want to implement 3-state logic or an open-drain interconnection.
In the former, the driving device DOES use a push-pull output, driving 0 or 1 onto the bus. The other devices, meanwhile, must abstain from driving until some separate system signals that it is their turn.
...
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Have a look at IIC communications between chips here. I think this will help complete your understanding. It's an industry standard way of implementing a multi-peripheral system using common lines such as clock and data. Open-drain outputs are used with pull-up resistors to prevent power-issue problems when one device wants to drive low whilst the other is ...
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RTL only implies the transfer of data with a loose guide on the gate level implementation. A case statement is a look up table and could easily be synthesised as a tree of muxes. May be create smaller look up tables broken up by flip flops.
The timing problem here is with the width of the bus getting all the bits to with in an equivalent ripple delay is ...
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I think the issue is not that you're selecting between 10 busses, but rather that your select signal has to fanout to several hundred multiplexors (~4 * 164 bits).
Driving a large fanout of several hundred pins will either create a huge capacitive load (if you have dumb synthesizer), or a large buffer tree (if you have better synthesizer). Using a buffer ...
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Since you are dividing by a constant this is a trivial 5-bit -> 4-bit (actually 5-bit -> 3-bit as @OlinLathrop points out) combinational circuit.
If you are feeling too lazy to work the 5-variable Karnaugh maps by hand then get yourself a copy of the Espresso heuristic logic minimizer. (If you google "espresso logic minimizer" you may be able to find a ...
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Your code will not work.
In verilog, a 'z' at the input of a gate transforms to an 'x' on the output of the gate. An 'x' at the input of the gate also translates to an 'x' on the output of the gate.
Therefore your code reduces to if(wr_req & !cam_busy & X & X & X)
The value of (something & X) can be either 0, or X, and in both cases ...
2
Instead of converting to analog, and then back to digital, just drive the LEDs directly from the MCU, keep it digital.
If you don't have enough IOs to drive the LEDs, you can multiplex them, or hang them off a shift register, or off a SPI or I2C IO expander, or latch them, or... lots of possibilities, but more information is needed!
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simulate this circuit – Schematic created using CircuitLab
If your microcontroller can output PWM, then set it to a high PWM frequency, and use a low-pass filter to generate a voltage. Something as simple as a resistor from PWM output to a capacitor, and a resistor across the capacitor to ground, as well as signal into the bar graph input, will ...
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First step is filling a Karnaugh map. The first one for little bit help filling the map:
$$
\begin{array}{c|c|c|c|c|}
\text{I1}\cdot\text{I2}\cdot\text{I3} & \text{I1}\cdot\text{I2} & \overline{\text{I1}}\cdot\text{I2} & \overline{\text{I1}}\cdot\overline{\text{I2}} & \text{I1}\cdot\overline{\text{I2}} \\
\hline
\text{I3} & ...
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Same deal as Camil Stap's answer, but using a single 74xx00 series NAND chip (4 gates):
simulate this circuit – Schematic created using CircuitLab
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Your output follows this formula:
output = (I1 & I3) | (!I1 & I2)
A circuit would look like:
simulate this circuit – Schematic created using CircuitLab
For logic gates, you can use the 7400 series:
AND: 7408, e.g.
OR: 7432, e.g.
NOT: 74LS04, e.g.
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This is true, no current when 0, current when 1, but logic gates have power supply's that make the logic work. So a NOT gate has 4 pins: power supply, input, output, ground (negative).
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Let's take this one step at a time. You seem to be confused about the term "clock skew". Clock skew is the amount of time by which the clocks as seen by two different flip-flops can be different.
For example, if you take the clock at FF2 as your reference, the rising edge of the clock at FF3 might occur anywhere from 0.2 ns before the same edge at FF2 to ...
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Without having very much else to go on, I'm going to suggest the range of devices that Digilent offers. I just recently bought their Atlys board which has been more than adequate for my DSP needs. It has video, audio, mostly a bit of everything. It also comes with Xilinx Webpack and some examples to get you started.
The Basys 2 has 8-bit VGA, a Spartan 3E ...
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I will address your last paragraph:
" If it does mean this then i have a question. When the input of NOT gate is 0 i.e current is not flowing into the NOT gate then how can the output be 1 i.e current is flowing out of the NOT gate."
All logic gates require a power supply, in addition to the logic inputs and outputs. We generally think of logic 1s and 0s ...
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As others, e.g. @angelatlarge, have mentioned, logic gates are typically voltage controlled. The mapping between voltage and logic varies quite a bit between families. If you look at, e.g., a 74HC04 data sheet:
http://www.nxp.com/documents/data_sheet/74HC_HCT04.pdf
you see in section 9 (Static characteristics) a lot of details on this. The key parameters ...
3
Usually such gates are voltage-controlled devices, and not current controlled devices. They generally have very high input impedance, which means that very little current is drawn from the input. How much, depends on the device, so see the datasheet for that.
The output side is usually meant to be likewise voltage indicator of the logic state. Whether the ...
2
A NOT gate is made up of more than than just one input and one output. You must also connect it to a power source (Vcc on schematics) and ground. When the input is 0 it is connecting the output to Vcc, when the input is 1 it is connecting the output to ground.
(see pin 14 and pin 7)
Here is what a NOT gate looks like internally
simulate this ...
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Things I tell my students:
Engineers are paid to know "why". If you don't know "why" you are just a technician. When things go wrong, you will be stumped (--> fired).
There are no black boxes in engineering. It's your design. You are responsible for it. No one else on the planet will (or should) know your design better than you do. That means you aren't ...
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For unidirectional data flow, although there will be shifters more suited to lower voltages, you should be fine with this chip. On page 6 of the ST datasheet, there is a High voltage vs Low Voltage graph which indicates a minimum combination of ~3V for Vcc and 5V for Vdd:
If you are using both Rx and Tx, then you will need a bidirectional level shifter, ...
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It's the classic undergrad question: Why learn how to calculate the deflection of a beam when there are finite element analysis programs? Why learn Ohm's law when there's SPICE? Why learn compressible flow when there are fluid dynamics programs?
Here's why:
As engineers, we are responsible for truly understanding how our designs work. That means ...
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Two reasons:
Someone has to actually make that "technology that can simplify everything for us", they have to know how it works.
Knowing how a system internally works helps the understanding on a higher level. In an analogy, we could say: "Knowledge of Assembly programming helps you making C programs more efficient, although you don't really have to know ...
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If "five 12-bit partial products as outputs" desired, then reg [4:0] b11 [0:11]; should be reg [11:0] b11 [0:4];.
Your b11 calculation is likely incorrect. There are missing elses before many of the if statements. Therefore, all except the final if condition with fall into the final else condition. You need to nest the else-ifs. Alternatively ,you can use ...
1
At the desired clock edge (rising or falling) the input at D appears at output Q. This takes a finite amount of time (Clock to Q delay) and assuming there are no timing violations, D will only pass through one FF at a time (i.e if there is another FFs input connected to Q, the second FF will pass the FF1 Q value before it changes.
To include timings in ...
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There's always some propagation delay through the flip-flop. It's often called "clock-to-Q" delay.
That means your inputs are captured on the edge, and you outputs change on the same edge, but just a few nanoseconds later. This few nanoseconds delay is enough (if your flip-flops are designed with "zero hold time" as they are in most FPGAs) that the changes ...
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(Broad question gets a broad answer)
I don't think there's much of a worry about damage provided your voltages and directions are correct and current isn't going where it shouldn't. If you're passing the connection outside a case over some sort of connector you should consider ESD protection.
(I'm going to assume your interface is "short", ie up to a few ...
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@Vicky Rao I think the reply by @Arslan Abbas is very relevant..
use the formula :
ADC bit resolution = (log ((VD * E) / (R * Vs))) / (log (2)) + B
here VD is full scale I/P voltage range of ADC.
Vs is full scale O/P voltage range of measured signal.
E is value represented in engineering units that Vs represent.
R is the resolution that ...
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After Brians suggestion I changed the input pin pull-up to a Tristate and it solved the problem!
Apparently the problem appeared when I changed from input pins to a timer capture pin and it was setting the pull-up as default.
Thank you for pointing it out.
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I don't think there is a job title for this, but it can happen that people end doing all of that, even though probably not everything at the same time.
For an example I worked for a company developing stereo-camera systems ("3D cameras"). There was a lot of math for the stereovision part, of course for the implementation of the algorithms there was a lot ...
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