# Tag Info

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Digital signals inside computers and other digital equipment are usually voltages that are nominally at the power supply extremes, like 0-5 Volts or 0-3.3 Volts. Of course this voltage is still ultimately analog, but two things are different for digital purposes: The circuit that drives the signal is specially designed to slam it either fully high or fully ...

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I'll try and describe the path the electricity takes from the wall to say a computer. First the power passes through a transformer to reduce the voltage from 120V (or whatever come out of the wall in your country). Next the voltage is rectified and filtered. Picture the AC voltage as a sine wave. Rectification is flipping the negative lobes over the x axis ...

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You could use a decade counter like the CD4017. The CD4017 has 10 outputs and it turns them on in sequence on the clock transitions. How many outputs are you looking to generate? If you need more than 10, then a series of shift registers would probably be a better idea. The trick is getting just one bit that runs around in a loop. I would suggest ...

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You can use a counter and then a decoder. The input to the counter will be your clock and reset (which can be omitted if you don't care what the state of the system is initially). The output of the counter will go into the decoder, which converts the binary number into a 'one hot' representation, where only one of the decoded outputs will be '1' at once. For ...

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Historically, some processors have used transistor gate capacitance as a means of storing information because it reduces the number of transistors required to hold each bit. A RAM with separate read and write ports would require three active transistors (one of which should have a large gate) and no pull-up devices per bit. By comparison, a RAM which ...

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A true digital signal is a list of numbers. Consider digital signal processing which has, as input, a list of numbers and, as output, a different but related list of numbers. When one uses a spreadsheet to find a moving average of the DJIA, one is doing digital signal processing. Also, remember that, abstractly, the contents of computer memory is just a ...

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Power Conversion The input voltage to a computer power supply is 120V AC in the US, where the "AC" stands for Alternating Current. It alternates 60 times per second, or 60 Hertz (Hz). You could say that this is an "analog" source, because viewing it on an oscilloscope or a graph over time, it's a sinusoidal wave. If you measure the instantaneous voltage at ...

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I'll try to go through the question section by section and explain mistakes shown in the logic, if there are any. We know that the 120v from the wall is analog And the digital one that the components will use (transistors, diodes, etc.) will look like this: Yes, that could be considered correct. That would imply that an ADC circuit must be ...

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Your logic is somewhat sound in assuming that an Analog to Digital conversion is happening, but there is a big set of steps that you are missing. Suffice it to say that this answer section is not sufficient to describe fully how a computer takes a 120VAC signal coming out of a wall and turns it into the webpage you are looking at. Turning the 120VAC signal ...

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1) you have a gate resistor of 1k when the datasheet is cited for 10R (for datasheet-like results) 2) you are putting a 2V signal on the collector of a 600V device whose Vce_sat is ... 2V IGBT's are funny devices, their actual characteristics do not manifest themselves until you get reasonable voltage across then and reasonable voltage. A typical 3rd Gen ...

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Use the clocked output from the switch as the clock to a control flop. simulate this circuit – Schematic created using CircuitLab A human pressing a button should be considered a separate clock domain. Therefore, two flops should be used to sync the input for CDC (Clock Domain Crossing). More about CDC here.

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To use the D-FlipFlop as a toggle switch, you need to convert it to work as T-FlipFlop. To do the conversion, connect the Q~ (pin 6) to the D input (pin 2). Change the switch S2 from D to CP (pin 3). That should turn the counter on/off in the present configuration.

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Since you have/want two independent inputs, you'll need to use a SR latch to store enable state. Since you're using an asynchronous latch, you won't need to debounce the buttons. simulate this circuit – Schematic created using CircuitLab

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simulate this circuit – Schematic created using CircuitLab When V1 < 3.3V, Q1 OFF, V2 = 0 When V1 = 3.3V, Q1 ON, V2 = 5

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Let x = ab'c + bc' x' = (ab'c + bc')' By DeMorgan's theorem, x' = (a' + b + c')(b' + c) x' = a'b' + a'c + bb' + bc + c'b' + c'c x' = a'b' + a'c + bc + c'b' Employing DeMorgan's theorem again, x = (a'b' + a'c + bc + c'b')' x = (a + b)(a + c')(b' + c')(c + b)

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What have you tried so far? What is your application, do you only want digital data to be multiplexed?< To be honest, I only tried to figure out how that thing works. Found a good website meanwhile explaining that. I want to switch 2 I²S lines and 2 MCK lines (24.576 MHz).

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YOu just have to add another 74HCT151, with its address lined in parallel wiht the existing '151s.

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I'm a bit rusty on these things but this should help as a start: - P'VST + PV'S'T + PV'ST'+ PV'ST + PVS'T' + PVS'T + PVST' + PVST becomes (P'VST + PVST) + P(V'S'T + V'ST' + V'ST + VS'T' + VS'T + VST') which becomes VST + P(S'T + ST' + V'ST + VS'T') etc..

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For a beginner this is best done with a 4-variable K-map. See here: http://en.wikipedia.org/wiki/Karnaugh_map http://www.ece.rice.edu/~kmram/elec326/Notes/notes-326-set5.pdf

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If we break the terms apart, we have 8 (P'VST -> 1000), 6 (PV'S'T -> 0110), 5, 4, 3, 2, 1, and 0. From those we can combine (via Q-M, which combines values with single-bit differences): 3, 2, 1, and 0 (00XX -> PV) 5, 4, 1, and 0 (0X0X -> PS) 6, 4, 2, and 0 (0XX0 -> PT) 8 and 0 (X000 -> VST) Putting those together we get PV + PS + PT + VST, which can be ...

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The '163 is a synchronous counter (with synchronous reset), so there's absolutely no excuse for trying to use it with a "ripple"-style clock. Instead, you should have the clock inputs of both counters connected to your clock source, and you should use the "Enable P" and "Enable T" inputs to control when the second counter advances.

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The way I see it, you're causing problems for yourself by using multiple clock domains, and worse, deriving a clock from data. The problem with data is that it has to settle. That's why we have separate clocks. A combinatorial circuit which evaluates some variables and then drives a clock invites trouble. Secondly, if you're going to kludge it, at least do ...

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I must add to the answers that a D-type FlipFlop is short for "data." These FlipFlops are designed to be very simplistic. The information you wish to be placed at the output is what you place at the input of the device. i.e., if you want the D FlipFlop to hold a logic HIGH, then place a logic HIGH at its input and clock the device. Changes can only be made ...

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If you're having problems with switching speed on a slow switching circuit, the simplest solution is to slow it down. I would suggest using your original idea, but add a series RC lowpass filter (series R, then shunt C to GND) right before the clock input pin with a time constant (R times C) on the order of a milisecond or so. This should filter out any ...

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I would highly recommend looking at the Spartan 6 series of FPGAs from Xilinx. They are actually quite affordable, and you could buy a pretty sizeable FPGA for less than the price of 750 7400 series gates. And it would likely run an order of magnitude faster while taking up a heck of a lot less space. Last time I checked on digikey a decently sized ...

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can someone explain what happens to the voltage at one end and the other end of crystal? Yes, the author(s) of the relevant Wikipedia articles made an attempt at explaining what happens. A piezoelectric disk generates a voltage when deformed A crystal oscillator is an electronic oscillator circuit that uses the mechanical resonance of a vibrating ...

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Performing the conversion using off-the-shelf discrete logic would be possible, but would probably require somewhere between 6 and 12 chips. One could also easily use a pair of 32Kx8 ROM chips (or a 32Kx16), observing that the LSB of the input value doesn't participate in the result; the only advantage of that over a microcontroller is that its output would ...

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For others looking for a better answer to this, the Invoke command works like a charm. The main culprit is actually the chosen component. Pick "Single Bus Buffer Gate with 3-State Outputs" instead. You'll get a op-amp like schematic. Use Invoke on this one and a pop-up window will show up that gives you the option to request a PWRN element. Choosing this ...

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You can do it with logic chips, but it's not going to be fun. If the digits are A, B, C, and D, you would need to calculate A + 10*B + 100*C + 1000*D. This can be expanded to A + 2*B + 8*B + 4*C + 32*C + 64*C + 8*D + 32*D + 64*D + 128*D + 256*D + 512*D. Power of 2 constant multiples are just bit shifts, so all you need is a whole bunch of adders. Or a ...

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As you're very unlikely to find an off the shelf chip that solves a specific (but not very common) problem the chances are you will have to build something. The conversion of the BCD to binary is a simple but repetitive task and is suited to a small micro controller but the number of input/output pins required is quite large so converting the code to a ...

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The circuit that you are using with only the buttons is perfect. My recomendation is the next: If the simplest works, use it and don't make your life complicated.

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If one input is high and the other is low, then the NAND gate attached to the "low" input will see at least one "low" signal and thus output high. The other NAND gate will see two "high" inputs and will thus output low. If the input that had been low goes high, its NAND gate will still have a "low" input [from the other NAND], and its output will thus ...

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A simple circuit for flip flop can be implemented by two transistors like this: This Flip-Flop can be changed by pushing one of the buttons. But how it works? Think there is no push button. and we just have two transistors and four resistors. When the circuit turns on, One of the transistors gos to On mode and then Saturation mode (rapidly) and when it ...

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Try starting to think from the second line. If you put 0 to S port, it would go to 0 in the output regardless of the other input because it is an AND port. But its output is inverted since it is and NAND port, so when you put 0 in S signal, its output will necessarily goes to 1 regardless of the other NAND input. Therefore, one of the lower NAND port ...

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First, as alluded to earlier, learn about state machines. That's really what you have here and diagramming it as a state machine will make it simpler to understand and to program. Next, I disagree with the speed and floating point comment. If you need floating point, use it. Speed is not an issue with this controller. However, it looks like you're applying ...

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In section 27.0, "ELECTRICAL CHARACTERISTICS", under "Absolute Maximum Ratings", the third entry states that the voltage on any pin (with a few exceptions) may not be higher than VDD+0.3V. This means that the inputs on a 3V3 device are not 5V-tolerant. You will need to use a level shifter of some sort if you want to connect the GPS to the device.

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You need to understand that a D type flip flop is a 1 bit memory element. When you give it a set signal it'll store its D input and will output it from the Q output on the fallowing cycles, until the set bit is raised again or the reset bit is set. So, by putting 2 or more flip-flops together, with the same clock, set and reset inputs what you get is an n ...

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In a typical asynchronous FIFO design, both sides of the FIFO can act as slaves to the external device connecting them. It may be necessary for either side to wait for the other, but such waiting need not be "precise". If the device that wants to fetch data polls the FIFO and finds that none is available, it need not poll again until it's possible that the ...

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I'm not familiar with the specifics of the devices you referenced, but in a general async FIFO there is a "pushing" side and a "popping" side. The side which pushes into the FIFO is usually called master, and the side that pops from it is a target. I don't understand why do you have difficulties in identifying the master without clock - the side which ...

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You've been looking at incorrect components: D type flip-flop is used to sample the D input on each clock cycle, but you want to use load signal in order to enable sampling. Please note that the signal set which you wanted to use as load has different funtionality - it causes the output to go high (regardless of the value of D). What you are looking for is ...

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It's not easy to do with T flip-flops if they don't have reset inputs. Basically, what you want to do is when the counter hits 9, the next cycle will reset it back to zero. Or alternatively, when it his 10 you immediately assert the flip-flop resets to set it back to zero. So you will need a 4 bit comparator to compare the counter outputs with either 9 or ...

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Use a decade counter like the 74xx90. If you need two then choose the 74xx390

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The number of gates per unit area is a function of many parameters, including the particular design rules for each manufacturer. If one manufacturer has more layers of interconnect than another then the effective gate density may be much higher even if the transistor geometry is very similar. The architecture and structure of the chip can also be a factor. ...

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