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First learn digital design basics. Mealy/Moore machine, combinatorial logic, truth table, karnaugh map and so on. Start creating a simple design in schematics (7-segment counter) and then learn a HDL. In Europe VHDL is used, in the US Verilog. Finally timing is important, be aware that signals have delays which are component instant and temperature depended ...

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Each bit in a bitstream functions as: a multiplexer/demultiplexer select, a storage element for a LUT, a pass transistor control bit (routing), or an enable/disable of some feature of the FPGA. e.g. you may have a bit sequence of 1001001110000111, giving a k-map of: cd 00 01 11 10 ab 00 1 0 1 0 - 1001 first 4-bits of sequence above 01 0 ...

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It's a bit complicated and involves a lot of software. Initially, you write code in a hardware description language such as Verilog or VHDL. This, along with timing and location constraints, make up the input of the FPGA toolchain software. The toolchain is a series of software programs that transform the HDL description of the design into a binary ...

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If you are using Xilinx FPGAs, the LUTs can be configured as 32-bit shift registers (SRL32), each with one adjustable tap. What I would recommend is using 6 of these 32-bit shift registers as three 63-bit registers in parallel, one fixed at 63 bits and the other two for the variable taps. With a bit of additional logic it should be possible to implement ...

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Your problem can be solved "easily" - that is, in a straightforward manner - but it will suck up considerable resources and cut down maximum frequency. What you do is to feed each input to the XNOR gate from a 256:1 multiplexer, with each register stage feeding one input to each of the two muxes. A 256-bit mux will have several levels of gates, so the total ...

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The quick, dirty and cheap way is to incorporate a UART in the FPGA and use the built-in matlab serial object to transmit and receive pixel data. You can crank up the baud rate to near megaHertz speeds.

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This answer can be considered as a candidate for the Software Recommendations section of SE, but here goes: you could try one of the 3rd-party packages that offer a library of target-specific drag n' drop Simulink blocks to simplify the development. For instance: http://www.mathworks.com/products/connections/product_detail/product_35635.html?s_tid=srchtitle ...

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It all depends on your budget and your level of knowledge of FPGA and HDL. IF you have a few k$, then I would suggest you purchase a board with an integrated PCIe on it, SoftIPs are expensive and hard to use, but if you just want to learn, many of the companies give non-production example designs that you can use. For altera you have a list of supported ... 1 I've used this Cyclone IV Board before. Altera has something called "hard IP" in certain devices that provides silicon for the pcie front end which saves space and power. This is supported in their tools without a license (last I checked). If you don't know anything about FPGAs or PCI (and PCIe) it's going to be a long way to your goal. But it's doable, ... 0 The following tutorial, making use of a miniSpartan6, is very detailed and worth a look: http://zerocharactersleft.blogspot.com/2015/04/diy-fpga-based-hdmi-ambient-lighting.html 1 You're probably seeing two things here: EMI pickup on the scope probe ground wire coupled with crosstalk in the ribbon cables. Try a measurement with a short (5mm) ground wire - take off the scope ground lead and remove the witch's hat (retractable clip), then wrap a piece of bare wire around the exposed metal sleeve. Measure across some bypass cap on one ... 0 This question has been stuck in the back of my head for a while and I just stumbled across the answer in the Virtex 6 configuration guide and then cross-referenced it to the Spartan 6 configuration guide. See the IPROG reconfiguration section in UG380 on page 128. This page includes the sequence of words to write to the ICAP_SPARTAN6 interface to emulate a ... 2 It should be possible to unroll this, but it will require 64*16 = 1024 MAC operations per clock cycle. Think about it like this: y[n] = a0 * x[n] + a1 * x[n-1] + ... + a63 * x[n-63] That's the filter operation that you need to do. Let's simplify that a bit and only consider the first 3 terms: y[n] = a0 * x[n] + a1 * x[n-1] + a2 * x[n-2] Each -1 is ... 1 The two broad flavors of testing are directed testing and randomized testing. For directed testing, you design each test. You might vary the order of the tests, but there are no new tests unless you write them. This is good for go/no-go testing or system emulation where you create a lot of complex directed tests. Best case in this scenario is to ... 3 You don't need much. Here's a list of what you might need: FPGA itself FPGA configuration source SPI flash + some method of programming it (direct or indirect via JTAG) (cheapest) JTAG programmable FPGA config flash (more expensive, but quite convenient) Parallel or serial load from external controller For some FPGAs, small config flash + load core over ... 6 Microprocessor-based dsystems, and later Microcontrollers, have been able to achieve an enormous degree of functionality by their ability to use many of the individual pieces of circuitry therein to accomplish many different tasks at different times. I think it's instructive to compare the arcade machine Tank, designed in 1976, with the game Combat which ... 9 The best use of silicon for a job is an ASIC, nothing wasted, but they have huge learning curve, NRE, and inflexibility. There are two ways to build flexibility into a chip. a) Have a space-optimised ALU, and use it over and over again on stored data. This is called an MCU, and requires a vast area of silicon that 'isn't doing anything', the program ... 2 Implementing USB on an FPGA is painful and very often not worth the effort. You'll probably do well to use one of the really common FTDI chips that do USB to RS232 conversion and then implement RS232 support on the FPGA, which is a lot easier. FTDI also has pretty decent driver support for windows and linux. 3 I would recommend either a USB UART chip or a USB FIFO chip. The USB UART chip will use 2 I/O pins, unless you want to add flow control on top of that. There are quite a few good USB to serial options out there. USB FIFO chips require a few more pins, generally 12 pins for 8 data and 4 flow control, but they have some advantages compared to USB UART ... 41 One distinction that I haven't seen elaborated upon here is that FPGAs are used, and behave, in a completely different way to processors. An FPGA is really good at doing the exact same task, over and over again. For example, processing video, audio, or RF signals. Or routing Ethernet packets. Or simulating fluid flow. Any situation where you have a lot of ... 5 Just to add to the other very good answers, I think the adoption of FPGA is also a matter of domain: for instance, for neuromorphic devices, FPGA boards are becoming quite ubiquitous because there is a huge need for parallelism, which is a strong point of FPGA. If you extrapolate the trend we see for neuromorphic devices, one can imagine that other fields ... 9 In terms of power consumption and silicon utilization an FPGA is very poor compared with a microprocessor. An FPGA consumes much of its silicon area in the logic configuration circuitry something that does not apply to a micro. There have to be many more interconnects available than would be needed on a dedicated implementation of a microprocessor. The ... 20 As Olin says, something like a micro is more efficient for many tasks, and you'll almost always find a micro used wherever an FPGA appears. The acreage of silicon used (which translates into cost in a nonlinear fashion) and the power consumption are much less. For that reason, it's not uncommon to implement a 'soft' MCU on an FPGA- but the cost and ... 84 You are ignoring a lot of factors that go into making design choices: Cost. FPGAs are more expensive than micros for the same complexity of logic. Logic complexity. Executable code can implement far more complicated logic than the same number of gates in the micro used directly. Ease of development. It's easier to write executable code than to define ... 5 It's entirely the cost. When a micro can be as low as 30 cents, a cheap FPGA is in the$5 territory. The cost may not seem that high, but when you make a million of a farting novelty toy to sell at \$10 then the price of the FPGA kills your bottom line.

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As Brian commented, you need to know what your computation needs. You actually have that problem with a processor too - it may have a theoretical peak number of GFLOPS, but if your particular usage of it doesn't allow the operations to be parallel, or bounces all over the memory so the caches don't work very efficiently, you won't get anywhere close to that ...

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Basically, no microcontroller, even the raspberry pi, is fast enough. The raspberry pi has an onboard GPU that generates the HDMI output. And other than that, the I/O capability of the raspberry pi is incredibly limited - the highest bandwidth interface aside from HDMI is USB. Many of the HDMI conversion projects involve taking another video stream in a ...

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A FPGA is very flexible and can be tailored to many use cases. So it depends on the use case which "performance indicator" is the main indicator. For CPUs, frequency was the main indicator for a long time. But it changed to number of cores, number of memory channels, cache size, instruction set, .... and of cause frequency. The best way to find a suitable ...

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I think you need an OBUF on the end of your ODDR. The ODDR cannot drive a pin directly. No doubt there is a warning in there somewhere, but hidden amongst thousands of trivial warnings :)

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