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@Paebbels, if TX_Clock is the transmit logic reference clock (i.e. the block is built around always @(posedge TX_Clock)) then the ODDRs (in SAME_EDGE mode) should use its 90-deg shifted version, i.e. TX_Clock90, not vice-versa. But you wrote: The normal clock is used for ODDR registers and the phase shifted clock is send to the PHY device. Is it ...


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Maybe it's not a direct answer to your question, but i want to draw your attention on the following possible workarounds: skew rate is controllable both at RGMII PHY and FPGA IC Typically RGMII PHY implements a de-skewing mechanism (e.g. KSZ9021 can absorb skews up to 1.8 ns, very near to that what you need), therefore (if your phy has it, of cause) you ...


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I found out what the problem was and why I wasn't able to pipeline this. Vivado HLS found a way to treat sum += ias a constant multiplication and so the latency remained constant. Therefore, if the latency is constant, the pipleine didn't make sense.


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Click on the Windows start button In the search box, type in: regedit and press the enter key on your keyboard Navigate to the registry key named: HKEY_LOCAL_MACHINE\SYSTEM\CurrentControlSet\Services\sermouse On the right hand side of the registry editor window you should find subkey named: start Double click on the "start" subkey and modify the value of ...


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You might be looking for an CPLD or a PAL which are programmable logic devices of less complexity than a FPGA and a quick search on digikey for CPLD shows that they are available in easy to use DIP packages from 20 pin to 44 pin


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What you describe would be to output 'Z' on the else branch, which translate to High-Impedance. If one driver outputs XYZ and all other drivers connected to it output 'Z', the result is XYZ. The 'Z' translate to a tri-state buffer inside the FPGA. However, tri-state buffers don't exist anymore on modern FPGAs for anything else than output drivers (i.e. on a ...


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The naming scheme on the primitives in your image suggests that this design is intended to be implemented in an FPGA. If this is the case, gating a clock network is not recommended. Clocked logic elements in an FPGA can usually only be clocked by dedicated clock networks. These networks are only available in very limited numbers (i.e, perhaps a dozen on the ...


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Here's how I understand this should work. I knocked this up and tested in Xilinx ISim. This synchronises the valid flag across the domains, holding it in the A domain until it is seen to arrive in the B domain, and using edge detection in the B domain to regenerate a single cycle strobe. The data bus is registered from A into B domain when we know it has ...


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You do not drive LEDR output at all. You need an assignment like: assign LEDR = M; You probably wanted to achieve that by assigning LEDR[3:0] to M (i.e. assign M = LEDR[3:0]), but this two assignments are not equivalent in Verilog.


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If some branches in the process are not explicitly assigning some net, it is implicitly assigned with the previous value with an inferred latch. So there is no situation the process won't drive this signal (unless explicitly assigning hi-Z to it..). Update: The possible solution, as states, is to mutually disable the driven net (put it in tri-state) in two ...


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You must supply VccInt for all pins named "VccInt". This is internal operating voltage and is not available on the outputs. The same applies to all Vccout I/O banks as well. All Vccout pins must be provided with voltages. Each I/O pin is designated to one of the device's banks, and each bank can have a different voltage, based on your needs (but, of course, ...


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I've had some success using a similar technique to what you have proposed above, which is to essentially create multiple registered duplicates of the high-fanout nets. You can use one per destination as you have, or what I have done in some cases is to duplicate them so that there is one registered duplicate for every n destinations. In theory, you should ...


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There's no need for any such book. The reason is that "all of the different Logic devices that can be implemented with basic logic gates" is just all the possible truth tables that can be constructed with any particular number of inputs. So a book of all the possible gates would be the equivalent of a list of all the numbers between 0 and 2n-1. In FPGAs, ...


1

Licensing they usually try for a large licensing fee plus royalties, then you negotiate from there. Sometimes they'll give you a break on upfront cost if you agree to larger per chip royalties. Upfront is usually always required since they need to provide you with support to get going. Keep in mind just an h.264 encoder may not be all you need in your ...


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Simply bending a pin up won't damage the chip. It's a common technique for troubleshooting and repairing a board with a layout error. However, those pins are extremely small and will break off very easily. Be gentle and don't bend it up and down more than one or twice. It'll snap right off. I try to find a narrow, sharp instrument (a sharp pick or the edge ...


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20mhz qpsk is easy. you can easily accomplish a 20MHz baseband with 2 GPIOs from a modern ARM processor and an IQ modulator. essentially, GPIO A sends 0 or 1 for the I channel. GPIO B, sends 0 or 1 for the Q channel. The IQ modulator will combine this to give you the 4 symbols for QPSK. your bandwidth is directly proportional to your symbol rate. something ...


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matlab to vhdl code conversion requires that you create a matlab function code and a test file script that test the matlab function, or you can create a simulink model and convert that model to vhdl or verilog. here is one tutorial- matlab to vhdl conversion but there are situations where it is not easy to convert matlab code to vhdl, for example if your ...


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My approach to this would be to get the ADC working by reading values in the Altera debugger first. It looks like the chip spontaneously takes samples and declares itself "ready" every 100ms. So you need to build a system which looks for that signal and starts shifting in the data at the appropriate speed (1MHz SPI). There's a slight wrinkle in that you have ...


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What kind of data am I reading? Similar to SPI. The datasheet details it. Where/how do I connect it? Absolutely anywhere. It's up to you to designate what pin is which on an FPGA (within limits). Is it possible/feasible for a beginner Yep, shift register systems are pretty simple to implement. ...use Verilog HDL or MIPS Assembly Language You ...


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When done in simulation, this type of testing would be called "directed testing". In other words... If I put in data A, I expect result B. If I out in data C, I expect result D. etc... (where all of the sets of data (A, C, ...) and results (B, D, ...) have been determined beforehand. Normally one would try to find a way to eliminate the human (that's ...


1

A DDS/NCO is basically a sample rate converter that has a fixed output sample rate and a variable input sample rate. In your example, setting the input frequency control word to 4 instead of 1 increases the frequency of the output waveform by increasing the sample rate of the input waveform (stored in the table) by a factor of 4 while simultaneously ...


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This technique is generally called Direct Digital Synthesis (DDS). How can the frequency be varied without effecting the number of samples present in the wave? It doesn't; The sample rate is fixed. I.e. the synthesizer/oscillator outputs some number of samples per second, this does not vary, the sample value varies. Lets say you used a sample rate ...


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the second you need to know is who are you (your future device): a master or a slave? An AXI master can initiate transactions but the slave cannot, it can only respond to a master initiation. while the first is what it is very probable that you (should) use the AXI as an IP block in your design therefore the cyclone handbook will not help you but the AXI IP ...


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This kind of design is pretty uncommon, but you are on the right track. To do delay-line type work you will probably need to force both the instantiation of resources you've mentioned, and the placement, otherwise results may not be the same across tooling runs. You've then got the problem that the results will not be consistent across parts, and will be ...


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It is possible to generate a structural gate model of a D latch in VHDL. Take a page out of PLD design where we find it requires a consensus term: library ieee; use ieee.std_logic_1164.all; entity not1 is port ( in1: in std_logic; outp: out std_logic ); end entity; architecture foo of not1 is begin outp <= not in1; ...


2

Latches and flip-flop can't be modeled with logic gates in VHDL, this is for analog simulators only! The feedback logic doesn't bode well with the VHDL simulator. Furthermore, no synthesiser would recognize it as a latch/flip-flop. To instantiate a latch/flip-flop, you can either instantiate your vendor's primitives or use this generic code: LATCH: ...


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No, an ALU is not in any sense an FPGA. All of the functions of an ALU are hard-wired (predetermined), and the desired result is selected by the instruction decoder. In contrast, the logic elements of an FPGA are very simple and general-purpose, and can be configured to produce any function at all.


3

Simply put, you're not transmitting valid UART serial. Serial comprises of one start bit, 7 or 8 data bits, 1 or 0 parity bits, and a stop bit. In total that's 10 bits. The most common arrangement of that is 1 start, 8 data, and 1 stop. Note that the UART has an "idle" state - HIGH in this case. The start bit is the opposite of the idle level, and the ...


0

I have thought about using an FPGA, but I don't have any experience with it, so I don't know what to look for. Pretty good idea. A FPGA will do that, but a FPGA will be overkill for your needs. You can use cheap CPLDs though. They are like a small FPGA, fewer pins, easier power supply and easier PCB layout. You also don't need external storage for the ...


1

Here is a programmable clock chip that may satisfy your requirement: http://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351-B.pdf You can also purchase a low cost PCB module with this part already installed and ready to use with a microprocessor interface: http://www.adafruit.com/products/2045?gclid=CIyi-r-1k8QCFYE7gQodvZ4Ang


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Try looking up Analog Devices range of direct digital synthesizers. Here's one: - Picture taken from here. Features and Benefits Programmable frequency profile—no external components necessary Output frequency up to 25 Mhz Predefined frequency profile minimizes number of DSP/µcontroller writes Sinusoidal/triangular/square wave outputs Powerdown mode ...



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