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6

Yes, you can use a delay and ignore the response, but if it is a response to sending the actual SMS itself, then that could take some time. You would have to send several SMS messages by hand to judge how long it might take the OK to come back, and then add on some margin to the longest delay seen. It would be much better to actually look for the OK ...


3

If your VHDL description exhibits combinatorial dependency cycles, then the synthesizers will generate the exact same circuit. If you want it, you get it. However, warnings will be emitted, because it is difficult (but not impossible) to tell whether the circuit will oscillate or not (that is : will behave as pure combinatorial circuit circuits or sequential ...


1

RSA is not suitable for directly encrypting large amounts of data. Not only is it way too slow, but it is also weaker than some other algorithms against an opponent who has a large number of known plaintext/ciphertext pairs. To guard against this, data which is encrypted using RSA is usually padded with random bits beforehand. As a consequence, RSA ...


2

RSA will not be easy to implement and may require a very large FPGA. RSA is far better suited to running on a general purpose CPU than an FPGA. I have seen some implementations of RSA on an FPGA that use a softcore to run the algorithm and the FPGA to accelerate some of the math, but the complete algorithm is not implemented in Verilog. And generally when ...


0

This is pretty challenging and unless you use an open source or readily available rsa implementation, 2 weeks is a stretch. If you use some ready library for implementation it is possible to wrap up the the library to suit your needs. This assumes you have a proven devkit you can use.


1

ISE sorts the hierarchy out for you. Once you've instantiated a lower block, it will appear under the top block, not at the same level of hierarchy.


1

counter2 is reset to state 11. When the trig rising edge occurs, it starts counting down. Your code shows no way to ensure that the trig edge is syncronized with your clk signal. In your simulation, trig goes high very shortly before a clk rising edge. So on that edge, counter2 starts counting down --- going to the 10 state. But in between the trig edge ...


1

OK, so after some try and error, here is how I managed to do it: First an AREA_GROUP which spans the part of the design which shall be constrained must be declared (in the projects UCF file). INST "my_module/*" AREA_GROUP="pblock_my_module"; This creates an AREA_GROUP containing everything in the design hierarchy "below" my_module. Now a range for the ...


0

One thing that is really key is you want to be sure you sample them together, but you keep all of their clocks rock steady without interruption. If you had four i2s channels carefully configured that would work. I wonder about an fpga design that would divide down a 4x clock from a micro, collect data from the microphones at that rate and pass it on at ...


1

Without the Ethernet, I'd say implement your algorithm on a FPGA in pure VHDL/Verilog. In general, that's going to be way better, in terms of power consumption, than running code on a processor. But as soon as you toss UDP/IP (or even worse, TCP/IP) into the mix, you've basically got to have a soft processor running on the FPGA. At that point, it makes more ...


1

From the schematics, it looks like it is driven directly from a FPGA digital out pin (presumably via PWM) through some op-amps to form an active filter for reconstruction. It doesn't look like you can hook up a passive speaker directly, I would just try getting some amplified "multimedia speakers" such as the USB powered ones that come with desktop ...


4

Generally FPGA designs start out similar to ASIC designs - it's all in the simulator. You can get far better visibility for debugging in a simulator than you can ever get in hardware. You do need to build testbenches and functional models, though, which takes time. For complex implementations it's a requirement as you will never work out all the bugs by ...


5

It depends on the kind of work you're doing. Some FPGA designs have massive amounts of effor in the functional logic, none of which really depends very much on critical timing or device-specific hardware. For that you'd usually use a simulator and develop/test things on a PC without going near any hardware. As a basic rule with FPGAs, if you design ...


4

If the new speed grade is slower than the old one, you should resynthesize to make sure that the timing requirements are met. The FPGA will be routed differently to meet the slower timing characteristics, and it is possible that you will have to make adjustments to the HDL source code to get timing closure. This is not necessary if you are moving to a ...


2

My suggestions would be (expanding on what Jeff has suggested): Make sure you run a ground from a pin as close as possible to the clock pin to another pin as close as possible to the clock pin. Twist the clock and ground wires together. Keep them as short as possible. Do you have a good high bandwidth scope to check the clock with, so you can see any ...


5

12.5 Mhz (80 ns cycle) should be doable. Wire up your clock lines first. Pick placement that keeps them short and cut the jumpers to length so that you don't have big loopy antennas. Verify that you are getting nice square clocks before wiring the rest.


0

Breadboards are crap for high speed. You should look in to making a custom PCB. Install some sort of layout software (kicad, eagle) and then send your design off to OSH park. Probably will cost around $30 and you will have far fewer problems with signal integrity.


0

Ken Chapman (Xilinx employee) provides a simple and lightweight UART module as an external I/O device for his 8-bit processor (PicoBlaze). These UART modules (RX and TX) can be used on every Xilinx FPGA. Each module has a simple byte interface. This processor and it's periphery comes with a lot of documentation and examples :) => Search "PicoBlaze" on the ...


2

I would suggest either writing a UART module from scratch or finding one online. Then all you would need to do is write a wrapper that interfaces the UART to your registers. Here is one possible open source Verilog UART module that I wrote a while ago: https://github.com/alexforencich/verilog-uart This particular module uses the AXI stream interface, so ...


2

First, when designing FPGA's we mostly just think about "resources" rather than "space". Resources are things like routing resources, logic cells, RAM blocks, multiply-add blocks, etc. It looks like you're concerned about minimizing the use of routing resources, and willing to use more logic cells to do that. Really, the best way to answer your questions ...


1

The FPGA layout will not really care about your modules at all, but rather create one big conglomerate of gates and then try to find an optimal layout. Enable signals in FPGAs are usually used only on the registers, which have a dedicated enable input. If you disable a module by pulling its enable signal low, you are close to the lowest possible power ...


2

Majenko's answer is correct but not entirely complete. The whole thing rests on ARM's "TrustZone". This is a stronger version of the normal concept of "ring 0" security found in operating systems, or a "hypervisor". It's a top level operating system that boots from the incorruptible ROM, configures the MMU, and then boots the "user" (phone) operating ...


2

The Secure Enclave is a separate CPU core within the CPU. It has its own RAM, ROM, etc, and consequently runs its own separate OS. You can think of it as a computer within a computer, and that "inner" computer is heavily firewalled off from the "outer" computer so only certain data can pass from one to the other. The theory is that your especially secure ...


3

I haven't worked with IIR filters yet, but if you only need to calculate the given equation y[n] = y[n-1]*b1 + x[n] once per CPU cycle, you can use pipelining. In one cycle you do the multiplication and in one cycle you need to do the summation for each input sample. That means your FPGA must be able to do the multiplication in one cycle when clocked at ...


2

I've done this a few times myself. Generally, the design tools will choose between a fabric implementation and a DSP slice based on the synthesis settings. For instance, for Xilinx ISE, in the synthesis process settings, HDL Options, there is a setting "-use_dsp48" with the options: Auto, AutoMax, Yes, No. As you can imagine, this controls how hard the ...


0

A Logic Element (LE) is made up of a number of gates. Exactly how long it takes to propagate data from the inputs to the outputs depends just on the combination of gates that the signals pass through, and that depends on how the LE is programmed. The main controlling factor of the LE is the Look-up Table (LUT). This has 4 data inputs and 4 data outputs, ...


1

It was really a faulty cable. I don't know if the problem is the chipset itself or a wire. Anyway, I bought a new cable with a different chipset and everything is ok now! This is the faulty one Bus 002 Device 008: ID 1a86:7523 QinHeng Electronics HL-340 USB-Serial adapter This is the one that worked Bus 002 Device 006: ID 067b:2303 Prolific Technology, ...


0

Xilinx has a good build-in help on synthesis, map, P&R and bitgen options. You can open them by opening syntheses/map/P&R or bitgen properties and then clicking on help. This help gives a short overview on every selectable option, it's values and the commandline name. There is also UG628 - Command Line User Tools which explains the bitgen options ...


0

I'd use both a transistor between the FPGA and the relays to reduce the currents through the FPGA, and add a flyback diode across the relays to protect the transistor.


1

The estimate given in the description of the IP core is just that: an estimate. Actual size and layout may vary during synthesis, depending on other components stuck signals timing constraints optimization level and possibly a few others. The estimate given for a particular FPGA architecture is usually not that far off in absolute space used, but ...


10

You need to use a transceiver when you want to bring out high speed signals from inside the FPGA and interface with the real world. Typical examples are to communicate with other high speed parts on the same board (for example another FPGA or ADC) or to interface off board (for example using PCI, HDMI or ethernet). In order to send these high speed ...


2

TL;DR: There's nothing which makes it technically impossible, but there are a number of limitations, and "real" ARM CPUs do a better job of this anyway. The biggest difference between the older CPUs that were often paired with these MMUs and modern Cortex-M microcontrollers is that the memory bus was fully external on those CPUs: all memory reads and writes ...


6

The key difference between FPGA's and microprocessors/microcontrollers is that a µp is a specialized circuit, and an FPGA is a general circuit that can be 'run-time' configured. In a fair comparison (same die size and process parameters) a µp/µc will win for what it is designed for: running vastly different sequences of instructions, with little repetition ...


8

See When can FPGA's be used and Microcontrollers/DSPs not? Microprocessors will nearly always win on throughput/watt. For total throughput, you can get quite good results with DSP chips, larger microcontrollers, or ARMs with onboard graphics cores. Although it may be hard to repurpose the graphics cores to other applications if the platform doesn't ...


0

Is there a special conversion happening?! Your image for slide 25 corresponds to figure 9.10 found on Page 506 and slide 27 corresponds to table 9.3 found on Page 507 in the book "Digital Arithmetic" by Miloŝ D. Ercegovac and Tomás Lang, 2004, ISBN: 1-55860-798-6. If you look in the book the text below figure 9.10 (b) on Page 506, Example 9.2: The ...



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