# Tag Info

2

What can be replaced by a FPGA? Entire rooms full of hardware have been replaced by FPGAs. Pretty much anything a 7400-series ICs can do, a FPGA can also do: Any digital function can be implemented with FPGAs. By "digital function", I mean something where each input is either "0" or "1" at any one instant, and each output is either "0" or "1" at any one ...

7

FPGA's can emulate all sorts of devices (CPU's, Ethernet controllers, Encryption stuff), but that is not where FPGAs shine. The cool thing about an FPGA is that it can do all sorts of things that don't currently exist! You could emulate an ARM CPU in an FPGA, but why do that when you can buy a real ARM for 10% of the cost? You could emulate a GPU in ...

4

FPGAs can replace digital logic as well as (in mixed-signal FPGAs) a few analog components (mostly larger bits like ADCs/DACs, comparators, PLLs, etc.). The analog/passive equivalent is the FPAA, and there are a few examples already in existence such as Lattice Semiconductor's ispPAC line.

1

I would say generally no, don't do that. However, only you know what your design constraints and goals are. The upsides are that PERHAPS you save power and your design's timing constraints may get easier to meet/faster to process. However, this may not be that much different than nearly equivalently designed clock enable logic. There are big downsides: ...

3

You can create as many clocks as you want, and you can use PLLs or DCMs to create arbitrary clocks. The question is whether you need to, or if you should be doing it a different way. I find that I end up running as much logic at a common or "core" clock frequency, say the 54MHz that you are using, but I need to trigger certain processes to run periodically. ...

1

It's certainly possible to use multiple clocks in any current FPGA. Most have a "digital clock manager" or similar hard-ip block available to generate multiple frequencies from a single input frequency. If this is a relatively straightforward design, it would be a good opportunity to learn how to use the clock management features in your FPGA. However ...

3

Let me quote Donald Knuth (his target was software developement but it applies in FPGA too): Premature optimization is the root of all evil I wouldn't really pay too much attention to lowering clock until there is a real need. I don't know what FPGA you use, but in case of Xilinx devices, 54 MHz is not very high frequency and XST shouldn't have problem ...

3

The best tool I know for linting Verilog is Verilator. Check the --lint-only option if you don't need the simulation.

1

As everyone else is pointing out, the Hardware User Guide is the documentation that talks about this. Additionally, you could look at the Board Schematic itself. You might also look at some of the reference designs that Xilinx provides. That being said, SW3 and SW4 are not the switches you are looking for. Instead, you'll want SW5 through SW10, which are ...

0

You can find all the information you need at Xilinx's web site for the board: ML605 13.2 and Earlier Documentation You can find the "ML605 Master UCF (rdf0041) (ZIP)" which is the 3rd one from the bottom of the list.

3

The hardware user guide for the board documents all of the I/O connections to the FGPA. In particular, the switches and LEDs are documented in chapter 17, which starts on page 49.

3

A processor such as the AVR is implemented using digital logic so it's also possible to load a similar design into an FPGA that behaves the same way. They are often referred to as soft processors and no doubt the original design for the soft processor would have been done using a traditional HDL. Once someone has 'done the hard work' you can load up the ...

0

In order to access the DDR memory on the board, you must use a memory controller. There are some good tutorials that can help you with that such as: Memory Interface Solutions User Guide And ISE In-Depth Tutorial And one that is specifically useful for you is the ML605 Reference Design User Guide You can find the files for ML605 on Xilinx's ...

2

Unless queueing and dequeueing are both controlled by a single clock (perhaps with separate enable signals, so that not every clock cycle will enqueue and dequeue data), it will be necessary for the FIFO to carry information across clock domains. This will enable tradeoffs between queue latency and resistance to metastability. In many ways, the cleanest ...

2

I haven't used Altera, or the FIFO you are using, and the signals you have in your picture makes no sense to me. But I have designed many FIFO's and maybe I can still give some insight into what you are seeing... Many FIFO's have a strange notion of "full". Specifically, "full" is when there is one less words than what you think there should be. A ...

1

The speed of your communication depends on many different items such as: The speed of your SRAM module The type of interface you are using The routing of the board For the first one, you can get the info from the datasheet of your IC, many SRAMs have acess between 8ns to 120ns, so find that information and if the device is not very fast, then you can ...

3

When you create a constraint for your clocks, the synthesis and P&R tools of the FPGA use that as the guideline to route your design. It is not only for the In/Out signals, but for every flip flop in your entire project. If you have multiple clocks in your design and you have regions where signal cross different clock domains, you have to explicitly ...

0

Practically, the main difference is that a SRAM controller is something you could write yourself in HDL. A DDR2 controller is orders of magnitude more complex, and so no one writes one themselves. After you learn more about DDR2, You'll need to learn about Xilinx's Memory Interface Generator (MIG). This is a tool that is part of Core Generator, which is ...

3

You can try to generate a single period the sine wave in matlab first, extract the samples, store them in the RAM (or BRAM) and let the FPGA play it the cyclic way, sending the data to the DAC. In matlab you should do sin(2*pi*F*n*T) Where F is the required sine frequency, T is the period time of the generating clock and n may run from 0 up to the number ...

1

Given the lack of detail in your question, here is a brief generic overview. SDRAM, like SRAM, is a memory. To write to it, you present an address and some data, and to read from it, you present and address and get some data back some time later. However, unlike SRAM, SDRAM requires both initialization/configuration at startup as well as ongoing refresh ...

2

The MCP23S17 is really meant to be connected to a microcontroller. I have used it successfully in a Blackfin-based project. It has a number of internal registers, just like the GPIO ports on a typical microcontroller. Each 8-bit port has a direction register, an input register and an output register, plus registers for input polarity and interrupt-on-change. ...

1

Have you simulated your VHDL to verify that it is doing what you expect it to? Your FPGA should be acting as the SPI master but it does not generate the SPI CLK signal. The VHDL process is also clocked from the same SPI CLK signal (sck) and because there is no clock on this signal your process doesn't do anything.

2

According to Altera's knowledge base, it's a bug in their simulation library, which incorrectly has the parameter names defined only in lower case (it should, apparently, be able to accept either). http://www.altera.co.uk/support/kdb/solutions/rd04192000_5867.html Searching directly for the error message didn't turn it up, because the text of the error ...

0

I think it stems from the memories. They were 18-bits already (to allow a parity bit per byte) and had been for a generation (of FPGAs, not engineers!) or so before multipliers came into the picture. And given one of the big uses was for FIR filters, then for applications where parity was not needed, having 18-bit coefficients is better than only having ...

11

Why not? Really, it's completely arbitrary. The cost in terms of chip area for 18×18 bits vs. 16×16 bits is negligible when compared to the area used for all the other resources (especially routing) on an FPGA. If you don't need the extra bits, just ignore them. However, I think the common practice of making multiplier blocks 18×18 bits ...

2

The answer from W5VO tends to focus on the back-end, and this is a major difference between ASIC and FPGA flows; but it misses out the digital design verification part. When getting a design onto silicon can cost a million dollars and more, and you can pack many more usable gates on an ASIC compared to an FPGA, then you spend a lot more time away from the ...

1

In VHDL (and HDLs in general) a for loop does not denote sequential execution like it does in a software programming language — it denotes the construction of multiple parallel instances of the hardware described in the body of the loop. In your case, you have many assignments to the same variable BCD/bcd, and these are conflicting with each other. If ...

0

Santa Cruz appears to be an Altera codename; like a lot of codenames it's based on a placename, probably Santa Cruz in California. Maybe they have an office there. Spec from Google: ftp://ftp.altera.com/outgoing/download/support/ip/processors/nios2/nios_cyclone_1c20/nios_santa_cruz_connector_spec.pdf

2

Since you want to know places to look for FPGA boards. Try this wiki page that is usually uptodate! Joel Williams - Cheap FPGA Development Boards

1

If you are familiar with the Arduino and are interested in (fairly) simple FPGA development, then you could give this a look. I personally don't have experience with it, but SparkFun tends to make/carry good products. It even has some interesting accessories for VGA and other connectivity. Hope this helps!

4

One additional problem is that if you find an FPGA the packages aren't typically suitable for breadboarding. Some smaller devices will have SMT packages such as TQFP that you could potentially remove and install onto a TQFP to DIP adapter, but some are just about impossible to deal with at home coming in high density BGA packages. For reference a TQFP ...

1

Here is a similar question: Cheap/old consumer devices to recover FPGA boards from And a slashdot thread with some similar discussions: http://hardware.slashdot.org/comments.pl?sid=2086242&cid=35835256 If you are willing to buy new but cheap take a look at digilent (especially their educational prices) and papilio ($38 as of now) here : ... 1 Ask your local FPGA distributor. They make have some older ones that are cheaper than the current generation of parts. But if you are "poking around on", you probably want an evaluation board. 5 FPGAs are rather hard to find in the wild, since once the prototyping phase of a project is done, the company will usually switch to an ASIC instead. The best place to find them would probably be discarded FPGA evaluation boards. 1 you can opt for something like HD video boards. then use some vide peripherials to connect it. But it depends on how you define cheap. according to your hackaday link, that device the guy uses is found in video hardwares, i think it has something to do with the matrix in television. http://www.amazon.com/electronics/dp/B00BUUV4X6 you can buy one for 15$. the ...

1

The best place that I can think of, especially as a student myself, would be http://www.digilent.com EDIT: Added specific boards. I would go for a device based on a Spartan 5 or 6, so one of Digilent's Nexys or Atlys series'.

4

FPGAs are definitely the way to go here. I have an Atlys board ($349,$199 for students) that I use for my personal development and it's definitely suits my needs at the moment. There is even open source hashing firmware for bitmining that you might be able to hack or use as a starting point for your own firmware. Using an atlys, you can get about 3.2 MH/s, ...

1

Come at it the other way - it sounds from other comments like you have a module already sorted out. Feed that to the FPGA tools - even the no-cost ones will give you an estimate of LUT/BRAM/FF count from the synthesis. Multiply that up by your instance count, add some slack and there you have a usable LUT count for sizing the FPGA. Of course, you may have ...

5

Why not look for a generally available existing crypto IC that does what you want? Example family of secure authentication ICs using the SHA-256 hash algorithm with a 256-bit key length There are development kits. Sparkfun produce a breakout for it. It communicates using I2C or 1-wire. (caveat - I've no idea if this particular chip can be ...

3

You want to match the right hand side width with the declaration width to avoid tool warnings? First use a 1-bit wide zero constant, this will be expanded using the Verilog expansion rules, which will give you an appropriate width zero: wire [width-1:0] a_net = 1'b0; If that generates a simulator/synthesiser warning your tools are outside of the Verilog ...

0

You can do this with parameters is you want it just in one module: parameter width = 8; wire [width-1:0] a_net = 0; For more than one module it's easier to do it with a define: define WIDTH 8 wire [WIDTH-1:0] a_net = 0;

7

If your budget is less then 10-20 thousand dollars (or more realistically 100K+), you have no hope of getting an ASIC made. The common device used instead of an ASIC, in situations where you cannot afford the NRE (non-returnable expenses - basically the cost for producing the masks for etching your asic, as well as the design costs), is to use a FPGA. ...

3

As you have surmised, you get errors when you have incompatible IO standards in the same bank. It's best to know exactly how this stuff works, because the tools will gladly give you a bitfile that ends up burning out your FPGA due to incompatible IO. As you posted above, we can consult the Xilinx datasheet for the device family, DS312. Supported IOSTANDARDs ...

2

For starters, you have some errors in your pin assignments. LEDs<2>, Pin P7, is bank 2 and not 3. spi_si, pin B2, is Bank 3 and not 1. spi_so, pin A3, is Bank 0 and not 1. spi_cs, pin J3, is Bank 3 and not 1. spi_sclk, pin B5, is Bank 0 and not 1. I never encountered a problem with the software defaulting to 2.5v, as Brian Carlton said. It may be a ...

1

2.5 V is the default. If you don't define the voltage, that's what the software uses. Multiple voltages in a bank is not fixable. You must use the same I/O voltage for all the pins on a bank. Also all I/O power pins for a bank are connected together.

3

FPGAs are more than just gates (LUTs, FFs, Block RAM, Multipliers, etc) and trying to work out how many there are is a fairly meaningless exercise. FPGA company marketing departments have, in the past, thrown numbers like equivalent gate counts equal to 1.4x the number of logic cells but I believe that they have stopped this practice. If you are trying to ...

4

FPGA manufacturers don't use equivalent gate counts much any more, even in the hand-wavyest marketing materials. Like lines of code or megahertz of processor speed, it's a highly inaccurate metric for measuring the device capability, and in the FPGA markets the customers wised up enough to suppress its use. To estimate the size device you need, you'll need ...

2

With a little luck, brute forcing can sometimes be faster than pulling out your oscilloscope or logic analyzer (or your only option when you don't have this kind of equipment). I have a USB<=>Serial cable lying around that I use for these challenges. I just connect GND and RxD wires from it to the circuit and just try to capture data. I usually start at ...

Top 50 recent answers are included