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5

If you just want to multiply two numbers and they suit the DSP block then the * operator should infer a DSP block. If not, send the synthesis tool back :) However, to take advantage of the more complex combinations of the DSP functionality often requires a direct instantiation of the block and configuring of its parameters. Examples of things which may ...


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If there are DSP blocks present, you should use them if you can because it will be more efficient than using LUTs to do the same thing. Unless you don't need a high performance multiplication, in which case you should implement, say, a pipelined adder and shift register to save space. However, I would look at inferring DSP blocks before going into the GUI ...


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It depends how much optimisation you need and how much portable should be your design. It is a bit like software, optimising using a bit of assembly or letting the compiler choose the instructions. You may have also some size/speed tradeoffs so that you could not afford a combinatorial double precision multiplier. I didn't know there where hardwired FP ...


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This should be possible with some careful design. Firstly as @Qui says you should generate a synchronised clock signal inside your FPGA at 60 MHz to allow you to read the data. Create a PLL which locks to the clock signal provided from your FT2232 and outputs a 60 MHz clock at a phase of 0 (synchronised). The FT2232 clock must be connected to a ...


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I strongly recommend adopting an existing Instruction Set Architecture (ISA), unless you are very keen to write your own C compiler. A related issue is, should your machine be 'self hosting'? Do you want the machine to be able to run the compiler, and compile programs, including the OS on itself. The implications of that decision constrain several choices. ...


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If you're asking what would be involved in building such a project: First step is to select what processor architecture you intend to build, then find an actual Linux distribution from Red Hat or SuSE or BSD that runs on that architecture. For example, i386-32bit or ARM-32bit might be a place to start. I doubt you will find any (modern) distribution that ...


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Altera offers a complete development system under Linux using VHDL. We have done a complete MAX-II CPLD under Ubuntu without the need to touch a Windows machine. They also include NIOS toolchain in linux too (although the latter I have never used).


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Select the generated report for "Top Failing Path", and then right click on one of the failing path, as shown in: The three "Report ..." options can then generate a report over all the elements in each path. Selecting the first "Report Worst-Case Path" given the report below:


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I think for beginners, the aocl getting started and aocl programming guide are enough, plus the aocl optimization guide @Jan suggested.


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Since the FPGA gpio pins only will be used as outputs an easy solution would be to use N-MOS transistors as a simple low side switches to control the relays.


5

I've designed over a dozen FPGA based boards that employed a wide range of different types of FPGAs from low power Lattice Mach X02s to high performance Virtex 6's with 24 SERDES channels. The normal steps I follow are: Find a COTs board (similar to MarkU) and get a rough idea of the internal FPGA resources you will need, in particular I pay attention to: ...


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I ran into a similar issue. My problem was that I had disconnected the sub-module outputs from the main module while debugging. When the optimizer sees that the outputs aren't connected, it assumes that the module is not needed so it removes it to save space. As a result, the inputs are left floating; this will cause the errors that you are seeing. If you ...


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I don't understand all the discussion about specs, chips, development boards and building a converter from scratch. Just go to Amazon and buy one -- there are several, for example: Sewell Hammerhead VGA to HDMI Active Converter 1080p Compact Size OREI XD-600 VGA PC/Laptop to HDMI Video Converter -Upscaler Up to 720P/1080P Converter with Audio Jack HDE ...


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I just found this VGA to DVI converter (Hackaday article). It converts VGA-compliant R/G/B and sync pulses into DVI, which basically uses the same signaling as HDMI. You'll need the ability to generate a reliable pixel clock, as well as to be able to send bits at 10x the pixel clock. Using an FPGA's DCM (digital clock manager) you should be able to ...


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You can create a small project with tour IP and create a wrapper arroind it and run it through your synthesis tool. That will give you an estimate on how much space it will take. You can "play" with different optimization to find the right choice for tour project. In Vivado, you do not need a wrapper. You can use the "out of context" option for the IP. ...


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At my company, we've previously designed some custom FPGA boards, and have recently started using commercial off-the-shelf ("COTS") FPGA boards with custom FMC daughterboards. Prototype stage If you're still in the early project definition stage, plan on buying at least one COTS FPGA board for prototyping. You can wire up one of your sensors to the I/O ...


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I think a good starting point for a custom PCB equipped with a FPGA will be the reference design boards from the FPGA vendor. You can inspect these designs for example for the power supply, but be aware that reference design boards are sometimes undersized. We had many trouble with Xilinx ML605 boards loosing there configuration, because of an undersized ...


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You're very close, so I'm going to give you the answer here. Let me know if you have any further questions. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; ---------------------------------------------------- entity counter is generic ( width: natural := 27; max_count: natural := 100_000_000 -- 50 MHz / 0.5 Hz ); port ...


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Thank's for your answer. Your answer is rignt of course. But the main problem of my project is in using IIC_Clock signal as clock for counter registers. This discussion on AlteraForum helps me to solve my problem. http://www.alteraforum.com/forum/showthread.php?t=45998


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For synchronisation you need at least two flipflops between the pin and the logic that uses it. Those flipflops need to be very close together (in terms of the delay between the first Q output and the second D input). You also have to ensure that the second flipflop does not get replicated (which it might if it feeds various other logic) - if it does you ...


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So I think I found some answers to the problem and want to share them. I started to simulate the GTXE2_CHANNEL hardmacro. The simulation is behaving as "false" as the hardware. So I tried to simulate the MGT in Verilog and used an instance template from here: ...


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XST can automatically infer RAM blocks. Read Xilinx's "XST User Guide" ref. UG627 "Dual-Port RAM With Synchronous Read (Read Through)" architecture syn of rams_11 is type ram_type is array (63 downto 0) of std_logic_vector (15 downto 0); signal RAM : ram_type; signal read_a : std_logic_vector(5 downto 0); signal read_dpra : ...


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One thought - it sounds like the AXI bus may be waiting for the peripheral to respond (by acknowledging the write) and it isn't. This can be caused by a variety of things, but having the addresses wrong would be one to check. Can you add a Chipscope and see what bus transactions are taking place?


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It looks to me like you are not actively driving the SCL/SDA pins. They are probably configured as high-impedance by default in the bitstream and therefore simply show adjacent pin clock noise as others have suggested. It looks like the scope is showing 500mv per division so the magnitude of the noise seems large to me but that doesn't rule it out when in ...



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