New answers tagged

1

The Theseus logic NCL has been mentioned, there was also Handshake systems (Philips spin off) as well as Fulcrum Microsystems and Caltech. There was a asynchronous ARM processor called Amulet as well. And SUN Microsystems had a processor design team for this as well for a clockless SPARC. I would call these clockless designs to avoid the confusion between ...


0

An FPGA is the right hardware. But you won't be able to use the synchronous-focused synthesis software, because it makes the wrong transformations. For example, an FPGA is perfectly capable of forming an oscillator built with an inverter chain. But if you define that inverter chain in e.g. VHDL and use one of the standard compilers, "NOT-gate pushback" ...


1

There is no problem now. I can make it look better by adding the .vhd file of the nios system into the project. Right click on it and choose "create symbol file for current file". It looks nice now.


0

The thing I didn't have in mind, is that SPI communications suggests that you should send as much data as you want to receive, not more, not less. So my buffer was noisy because of that. By setting m_length to 1 : err_code = nrf_drv_spi_transfer(&spi, m_tx, m_length, m_rx_buf, m_length); I am successfully transmitting one byte, while receiving ...


1

MOSI (Master Out Slave In) is an input on the slave, so it is always high impedance. The slave won't be able to tell if the MOSI line is high impedance at the master, but then it doesn't need to. If the slave is selected (SS low) then it expects to see 1's and 0's on MOSI. If it is deselected then it doesn't care. The reason for having high impedance on ...


0

By design a FPGA is digital. So the input camera has to be deserialized before being re-serialized.I have provided further information here. I have provided further information here.


0

Solved the problem, should have posted it a while ago... Anyway, fount some omnifets, which are a pair per IC works well in tests, havent actually put the whole circuit together. Also placing a capacitor between the power terminals solved the debounce issue. Here is a link to the mosfets: http://uk.rs-online.com/web/p/intelligent-power-switches/8773144/


1

No, it is not possible to access the SRAM of the Cyclone V GX Starter Kit directly from Quartus II. From page 37 of the User Manual, the SRAM is only connected to the FPGA. Thus, the user application in the FPGA will need to be responsible for writing the desired data into the external memory. As mentioned by Zuofu, the Terasic "C5G Control Panel" can ...


7

No, this is not safe behavior. The weak signals are intended for simulation, and during synthesis they are interpreted as strong signals. After all, you need the physical resistor to be there, and FPGAs only have internal pull-up resistors on the I/O pins.


1

Our PoC-Library can run Xilinx XST from command line via Python3. We are using template files for XST, because each target device can have other XST options. Here is a *.xst file for a 7-Series XST run: set -xsthdpdir "xst" run -ifn {prjFile} -use_new_parser {UseNewParser} -ifmt {InputFormat} -ofn {OutputName} -ofmt {OutputFormat} -p {Part} -top {...


6

The simple answer is maybe, but probably not. It really depends what is using the memory. It is important to consider the structure of the memory. The M9K memory modules are true dual port. This means that they have two independent read/write ports. Each of these ports has one address bus, one read data bus, and one write data bus. What that means is that ...


0

The "Control Panel" application provided by the actual manufacturer (Terasic) should let you do this: Cyclone V GX board


1

Your are passing 64 bits as input (63 downto 0). You can select/work with any number of bits by using the signal name and changing the downto parameters: temp1 <= input(7 downto 0); -- This maps 8 LSBs of input to temp1 temp2 <= input(15 downto 8); temp3 <= input(63 donwto 56); --This maps 8 MSBs of input to temp3


1

This is basic HDL — if you want to work on a subset of a signal, just specify the range you want to work on, such as: input(3 downto 0) input(7 downto 4) input(11 downto 8) . . . If you want to do the same thing to different subsets, there are various looping constructs that you can use to simplify the source code.


3

Just connect it up directly with a wire (you will see a little blob appear to show it is connected). Then, name the bus something like name[msb..lsb], and then name the wire name[whichbit]. That will tell Quartus to connect them because they both have the same name and tell it which bit it should connect to. You will get errors if you choose a whichbit which ...


4

Your problem is in your choice of test equipment. An oscilloscope is generally not intended to be used as an accurate frequency-measuring tool. An oscilloscope can be used to verify that a signal is of approximately the correct frequency, but because frequency measurement in an oscilloscope is usually done by measuring the period of one cycle of the signal, ...


0

Depending on your install, your simulator resolution may be picosecond by default. Check your modelsim.ini and look for the Resolution variable under the [vsim] header. Alternatively you can force the resolution on the command line. Your are very close with your example. The syntax is vsim -t ns for nanosecond resolution. Note that the Verilog timescale ...


0

Ensure that your timescale and time precision are set appropriately for your design. If the system clock is 50 Mhz, you do not need 1ps resolution. By reducing the time precision the simulator will evaluate fewer events and it should help the simulation speed. For Verilog, use the timescale directive: `timescale 1ns/100ps The first argument is the ...


2

This is a really common issue for all FPGA developers. Here are my advice (there are probably many other). First you can decide to watch only few signals, so that the calculation will run faster. You just need to separate your design into smaller modules (or only look at one process after one). Or you can define different constants for simulation like this:...


0

You can get the vendor specific tools. The two main FPGA vendors are Altera and Xilinx. I am familiar with Altera only and Quartus is their development package. Quartus has a free version. You can compile and synthesize HDL and simulate it in ModelSim. You will need to write your code so it is synthesizable, which is always a good thing. Alternatively, you ...


1

Aside from things that you will never be able to afford as single person or small company: As it is now, FPGAs pretty much pose a vendor lock-in. You buy an Altera FPGA, you're damned to use Quartus. You buy a Xilinx FPGA, you're going to use Vivado (or ISE, if the FPGA bought is not among those supported by Vivado). Pretty much everyone hates something ...


5

The simple answer is that they don't on their own. The synchroniser is there not to ensure the data gets across, but the ensure you don't end up with metastable signals feeding lots of other signals and causing problems. The second FF as the diagram shows catches the metastable first FF output and prevents it propagating further through the design. There ...


0

1) Using your drawing as an example, aclk and bclk are asynchronous to each other. In other words, they have different clock sources. They are showing adat as valid data but synchronized to aclk only. This is where the bclk synchronizer comes into play.2) This drawing assumes a worst-case scenario, where bq1_dat is a messy output because the bq1 FF caught ...


0

I worked in a company who wanted to design a 4K camera at 300fps using a low cost FPGA! The project was unrealistic because of many issues that they did not count into their product planning. The difficulty of designing a camera, specially a 'high-end' is mainly the memory bandwith and the amount of memory you have acess to. If you want to capture a ...


0

I see where you are coming from, though profiling isn't really the right term here. FPGAs aren't programmed in the same sense as a computer is. You describe what hardware is required using code, then synthesize it using the toolchain from the specific vendor whose FPGA you are targeting. You then get a synthesis report that will tell you the resource ...


3

The data bandwidth you mentioned is certainly part of the calculation, but only the beginning: the FPGA and the camera module need a compatible interface that can reach the required speed. Whether your processing pipeline can be realized depends very much on your definition of "basic image processing". Ideally your algorithm is parallelizable so you can ...


1

I think i understand your problem , i had similar problem when starting making circuits in HDL (verilog or VHDL) and coming from programming C++ , python or other languages. What you need to understand is that in verilog , your variables represent wires(bits) or group of wires (vectors).... so you cant assign same variable as output from 2 parts of your ...


1

Normally there should not be any scaling to be done.. Just make your filter In/out 18 bit wide... also , do not forget the anti-aliasing filter at the output...


4

When your program makes the synthesis of your VHDL, plenty of reports are generated. Normally you can see detailed logic resources usage per VHDL block, component and so on. This is the way I do it in Quartus.


0

Generally when there is a need to modify a single bit a read-modify-write approach is the safest. First read the register in question. Next modify the bit that needs flipped. Finally write that register back. This way unnecessary bits don't get flipped.


1

Two thoughts: Making sure you can use powers of 2 (and a suggestion to do so); Helping the synthesis tool. A. Making powers of two. Unfortunately a simple change to powers of two makes you change from 2228 to 4096 and from 68 to 128. That would require almost four times the memory range ... . You could split 2228 in 2048 + 180 resulting in 2048+256, ...


0

How important is it that you use those specific addresses and put all of that in one RAM? Consider partitioning things differently so that you can replace all of the constants in that equation with powers of two. This will remove the need for hardware multipliers and you will actually be able to run the computation in a single clock cycle. Also, partitioning ...


0

As mentioned by others Smartfusion2 devices do not have analog functionality. However they have many differential pins which are internally connected to a comparator. A comparator is a one bit ADC. Many including myself have used this comparator a differential pair and an extra pin together with a resistor and a capacitor to implement a SAR or sigma-delta ...


2

Yes the pin is called "ADC_xx" but as Richard pointed out it doesn't appear anywhere in the documentation. Note though in the "connects to" column there it says they connect to the FDDR and GPIO pins. My guess is that the naming convention is standard across their breadboard areas and it's part of some scheme to help developers keep consistent across their ...


1

The SmartFusion device supports analogue, the SmartFusion2 does not Link From that information, it appears you cannot do this with the kit you have. This evaluation kit does support ADCs.


1

I see NOTHING in the block diagram that suggests that it has ANY kind of analog inputs or analog-to-digital conversion. Just because the name of some of the pins use the letters "ADC" does NOT imply it is an analog-digital converter. If you see something there that we missed, please identify it explicitly.


0

It looks like the max clock speed is 1.33 GHz for the ARM. But I'm not sure you can can clock the PL that fast. I imagine you can take advantage of the parallelism in the FPGA to do many MAC operations simultaneously. If the FPGA can access main memory though DMA, it can fill up the memory then send a flag to the CPU to offload the data when it's done. ...


0

regarding functionality MB vs ARM Cortex-M3, basically the Cortex-M3 contains a ARMv7-M CPU and that means it's based on ARMv6-M. Check out some screenshots showing off mainstream features. MB will definitely be better integrated on Xilinx FPGA fabric and its 'in the field' since many years. For more info on MB, search UG081 - MicroBlaze Processor Reference ...



Top 50 recent answers are included