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The required clock speed/efficiency (calculations per second) of your processor is based on the complexity and efficiency of your program. A simple but poorly programmed application could need a super computer compared to how another programmer can do it! The complexity, and things that need to be done are the main factor to dictate how fast it needs to be. ...


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Your coding style needs a lot of work. The main problem is that you never use your hardware reset signal rst to initialize anything other than up_counter2. This means that all of your state variables can start up holding random values. Your trigger code can be separated out into its own process, like this: process (clk) begin if rising_edge(clk) then ...


1

NIOS2_CPU_IMPLEMENTATION and other undeclared identifiers are defined in system.h file, generated with BSP. It looks like you forgot to include this library in your code. Problems with implicit declarations are caused by not included sys/alt_timestamp.h library.


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If you look in package LPC_pkg you have constant num_coefficients:integer:=3; constant num_samples_per_window:integer:=1; While in the entity signature_extract_1 header: Generic( num_coefficients: integer:=12; num_samples_per_window: integer:= 80); You have a basic disagreement on how many coefficients and samples per window are in ...


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The correct answer is, of course, "with wires". I assume you've read the WiFi module's datasheet? A quick look at the XBee website shows that their WiFi module communicates over either UART or SPI. Implementing a UART or SPI master on an FPGA is (relatively) simple and, if you've never done much FPGA work before, a good learning experience. If you don't ...


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Answering your comment question here where I have more space. Let's say you have an application you've designed on a linux box, and it runs an algorithm you wrote for counting the number of cat pictures on the internet. Now it runs but it's slow because there is a lot of cat pictures to go through, so you want to accelerate it in hardware. So you use ...


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Shouldn't that be 'lazy lout'? The adapteva website has various bits out of date and it can be a bit confusing. The Epiphany based Parallella boards from adapteva have canned bitstreams for the various product configurations available for download from github. Presumably the documentation would tell you how to get it loaded. (See Latest Technical ...


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On the Stratix IV GX FPGA Development Kits web page, you'll find the Stratix IV GX FPGA Development Board Reference Manual (PDF) where you'll find the documentation for the MAX II CPLD EPM2210 System Controller beginning on PDF page 15, and the FSM bus flash write enable (FLASH_WEn) in table 2-6 part 3 of 4 on PDF page 18, showing both the MAX II CPLD ...


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I have an Atlys board and have a couple of different solutions that I use to validate data, depending on the application and datarate: I use a UART for low-speed transfer and connect it to my pc using a USB cable. I think the nexys has an onboard FTDI chip converter so you just need to use the USB cable. There are a number of uart opencores, or it's ...


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Most of Digilent's FPGA boards, including the Nexys3, implement a simple parallel interface which can be accessed over USB. The interface is documented at: http://www.digilentinc.com/Data/Products/ADEPT/DpimRef%20programmers%20manual.pdf See also: Implementing the Digilent EPP You can interact with this interface using code libraries provided by Digilent, ...


4

Xilinx has an in-system debug tool called "ChipScope". It uses spare FPGA resources (mainly block RAM and counters) to create a logic analyzer that can connect to any node in your design, capture waveforms and display them on your host PC, using the same JTAG interface through which you program the chip.


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In the end the decision was to group them by 4 as @spehro-pefhany suggested in comment, and connect them to a bunch of MCUs, which can then communicate on SPI bus. The main advantage is less cable mess, as I can place the MCUs close to the encoders.


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One solution is to use a demux to reduce the ADC sample rate, and take advantage of the large number of pins on the FPGA. For example, the ADC could be clocked at 500 MHz, and the FPGA at a more reasonable 125 MHz. Then a 4:1 demux can be used - collecting 4 ADC samples for each tick of the FPGA. The bus becomes 4 times wider, so at each tick the FPGA needs ...


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If you're only dealing with a single, digital output, and generating square waves, the simplest way to do this is to have two (or n) counters at each desired frequency, and XOR their outputs together before outputting them to the pin. This produces an equivalent result to Kaz's toggling approach.


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Two ways (that I can think of): With a DAC Multiply signals individually to get different individual amplitudes. Sum the signals you want to combine Output n bits to the n-bit DAC You can make a simple R2R DAC yourself using only resistors. Without a DAC, using a single pin and a low-pass filter Add the two signals Modulate the output using delta-sigma ...


0

Well, I am currently responsible for a project which performs hand tracking recognition using a SoC (FPGA + ARM Processor). We have not started to develop the solution in the PCB yet, but I think some considerations we have taken in the beginning may help you. Yes, FPGAs are very interesting to perform this kind of recognition algorithms because it allows ...


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One simple way is to take each output of the counters, pass it through a resistor, then connect the other end of the resistors together. Now the individual counter outputs would be attenuated while the final output would be the sum of the counter outputs.


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When I was a teenager in the 1980's, I had an Apple II+ computer, which had a speaker output similar to the IBM PC speaker. Accessing a memory-mapped I/O port location had the effect of toggling an output connected to the speaker. I wrote a machine-language program which played triads: three simultaneous notes. A look-up table converted note values (indexed ...


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It depends a lot on the type of hardware you have. If you only have a 1 bit output on the FPGA, you can oversample the audio signal (1MHz or more) and use a PWM or delta-sigma modulator, effectively generating a variable amplitude signal (you may add a low pass filter, a simple RC circuit is sufficient). You can then add your synthesized signals (sine, ...


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It could be usefull to know the working frequency to know the duration variation in cycles units rather than time. How are you retriving the outputs from the calculator ? Maybe this non constant time is induced by the protocol you're using.


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The most useful thing about using a soft core CPU is the fact that it's customisable. Most microcontroller chips come with a set number of on-board peripherals: I2C, SPI, GPIO, PWM channels are all limited to however many they give you. In a soft core processor, if you need 10 I2C channels and nothing else, then you can design your soft core to do only ...


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If the ONLY purpose of the MCU on the old design was to load the FPGA, then on the new design, you're going to be using one of the self-configuration methods for the FPGA, and you won't need an MCU at all (soft or otherwise). But if the MCU was doing anything else at all, then your soft-core CPU will be doing those other things. It just won't be loading the ...


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The absolute maximum voltage permitted for Cyclone IV devices is 4.2V, but the recommended maximum operating input voltage is 3.6V. To ensure reliable operation you should reduce your signal voltages to 3.6V or less. If you don't need high speed and/or the drivers are strong enough then you might get away with passive resistor dividers (eg. 33 Ohms in ...


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This solution is very extensible, but it creates a big mess of wires. You can interface one encoder with two 74HC193s and use a bunch of I2C GPIO extender to read them. This will allow you to add as many encoders as you like.


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A small FPGA is the way to go here. You would need a very large CPLD to manage this many encoders - they are not useful for much more than glue logic. Generally a CPLD gives you one flip-flop per pin. An FPGA has logic resources that are specifically designed for building things like accumulators and shift registers, and far more of them than a CPLD with ...


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Why not use quadrature decoder chips? The LSI LS7366R is a 32 bit quadrature decoder that also supports the index signal if needed. Everything you need is inside that chip and read via SPI. There is also the old standard Avago, previously Agilent, previously HP HCTL-2032-SC. It uses an old school parallel bus interface and is in a large PDIP package. I am ...


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I haven't communicated with the AD9910 over parallel, but to use the serial communication from my FPGA I set all the jumpers to specifically not use the eval board FPGA. Along with setting those jumpers to disable the onboard FPGA control, I had to jumper several lines that I wasn't using to ground (IO_RESET, EXT_PWR_DWN, RESET). Maybe trying to control the ...


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All of the DCM blocks (digital clock managers) in FPGAs I've worked with can scale up and shift clock frequencies cleanly. Ensure that your input base clock arrives on a specific clock pin if you can, as this will introduce the least skew routing to the dcm. If you want more specific guidance, which part are you targeting and what frequencies? If you are ...


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Using the terminology found in the datasheet (see Figure 1): blue arrow: CLB (configurable logic block). This contains four "slices", where one slice comprises two LUTs (lookup tables) and two flip-flops (see Figures 11 and 12). white arrow: This area contains both BRAM (block static RAM) and multipliers. yellow and orange arrows: IOB (Input/Output Block) ...


1

Once you start incorporating specific primitives into your design, that design is no longer portable — it is locked into the technology in which those primitives appear. In order to simulate such a design, you need to have the manufacturer's simulation library for those primitives. Such libraries are often delivered as encrypted binary files, in order ...


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For the most part, the synthesizer is good at inferring primitives. However, there are primitives that cannot be inferred. Sometimes it as simple as a dual port RAM with different port widths or a FIFO with no extra fabric logic. There are also things like DCMs and PLLs for generating and managing clocks that can't be inferred with pure HDL. FPGAs in many ...



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