# Tag Info

0

You can't think of them like that. FPGAs use hardware description languages, meaning you are building a concurrent circuit. You can put sequential statements in your code, but those will implement as components that run concurrently. Arduinos, on the other hand, are microcontrollers. They are run in loops with sequential code. FPGAs read your code and ...

1

I doubt that this is possible purely with programmable logic as the NEON SIMD engine accesses internal registers and the instructions come from the main instruction stream. There is no way to access either of these from PL. However, what you might be able to do is set up the NEON load/store instructions to read from and write to PL mapped address space and ...

2

The answer to this is: "sort of, but it's a lot of work". The PS and PL on the zynq are interconnected using a number of AXI4 interfaces, with varying speed and coherency capabilities. These interfaces can be used as a mechanism to implement a register interface, or transfer data between the PS and PL. There is no inherently native way to pass-off ...

1

One answer that isn't here is Data Acquisition. If you would like to use a ADC to sample a signal (for example, a RF signal) at 200Mhz and process it, a microcontroller is simply not going to be able to process the data fast enough. A typical DAQ FPGA board will receive, filter, perform a DDC and pass the RF data to a CPU at a much lower frequency. FPGAs may ...

0

Don't output from the DAC until you have added in the compensator. Input the output from the buck boost through another ADC and add internally. Then output through the DAC. Make sure to take care in noise compensation when dealing with the buck boost. Properly decouple and smooth the switching noise then route the secondary ADC and addition block on the ...

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It can be a difficult argument to make when people like GUIs. However, take a team using graphical entry, and then live through the horror of having to change tool, target, or even tool version that breaks the existing file format. In our case the tool vendor got bought up, and the next version was incompatible. Their 'auto-migrate' tool did exactly what ...

1

My question is therefore for seasoned EEs how they were if ever persuaded to use plain-text entry? I'm not a seasoned EE, not by a long shot. But I do have VHDL experience and one of my jobs consisted of using a combination of VHDL and Python, much like you describe in your question. GUI-style development was simply not allowed. It took some time to get ...

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Despite the fact that Vivado assure a PULL UP on the selected pins it is a WEAK PULL UP, adding an external PULL UP resistor has solved the problem.

0

Like many have pointed out that FPGA can be tough for learning the DSP algorithms themselves. I think one of the main reasons you would use an FPGA is to reduce the processing time. But implementing an algorithm on the FPGA does require you to learn an HDL. Even if you use pre built IPs you still need to connect and perform inter IP communication if ...

2

Whether you use a microcontroller with DSP functionality, a DSP chip or an FPGA is (at least theoretically) not as important as what algorithms and filter coefficients that you use. So once you make the leap to digital processing, it becomes a matter of whether you need the performance that only an FPGA can give you or not. Even within an FPGA design you ...

0

FPGAs are more expensive, more complex, have less user-friendly software tools and are harder to debug. I would say that the easiest way to get started in DSP is in PC software, starting with higher-level tools like Matlab, intermediate difficulty languages like Python (with numpy this is quite fast enough for mere audio), down to C. Once you have an ...

3

Take a tip from which way the professional industry is moving. Some organisations program the DSP parts of their FPGAs by writing a MATLAB or C program, then use a synthesis tool to compile it to VHDL. Much the same as most people stopped writing machine code or assembler, when compilers became accepted as the way to do it. However, these tools are usually ...

1

There are often standard ip cores that can do floating point logic furnished by the manufacturer. For example, Altera have megafunctions that can do floating point operations, and pipelinable. See this document: https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_altfp_mfug.pdf

1

If you really want to take your hands of the keyboard often, then quartus has a symbolic editor with gates already made. Video Example. I'm sure some of the other synthesis tools have symbolic editors like this but it is so much easier to code it in with verilog or vhdl.

7

You need to re-think your approach to Verilog. Being able to say c <= a + b; (adder) or i <= i + 1; (counter) on signals that can have arbitrary bit widths is much more concise and less error-prone than wiring up 4-bit chunks of 74xx logic. Let the synthesis tool take care of all the low-level details for you!

2

The issue you have is the CPU in question is as old as the pyramids in technology terms. It doesn't support common interfaces like PCIe - only PCI when connected to the correct north bridge. It is possible to get motherboards for these things off well know auction sites and whatnot (it is a socket 478 processor), which would simplify things, but would still ...

5

If you have a spare processor, I think the best way to go about adding an fpga to it would be to buy a motherboard that has a PCIe slot and add in a pcie fpga card. Done and done. Trying to redo the work of hundreds to thousands of people working full time for years is borderline insanity or more probably simply engineering mis-estimation on a gross scale. ...

4

50MHz/4.16666MHz = 12. You are counting to 6 twice, not 5 twice as you think you are. The classic off-by-one error :) If it seems muddled, try simulating your code, and that ought to clear things up.

4

Seems fine. Three suggestions/recommendations: Use non-blocking assignments for registers Use an if-else instead of the case. You are missing the reset clause - how does it know what value to take when in reset. So the code would become: always @ (posedge clk) begin if (rst) begin Busy <= 1'b0; //Reset busy with the reset signal? end ...

1

I answered a question here that details some of the different types of FPGA file formats: FPGA: Bitstream vs. SRAM Object File Basically, right now, you're flashing just the SRAM with the SOF (SRAM Object File) -- this is volatile, and will be lost at power down or reset. SRAM FPGAs generally load their configuration from a configuration memory on-board, or ...

3

40 MHz corresponds to a wavelength of 7.5 meters. So long as you limit your driving rise and fall time to avoid exciting high harmonics, you should be able to transmit over 10 inches (~25 cm) without thinking too much about transmission lines and controlled impedance. Are IDC ribbon cables sufficient at 40MHz? For this distance, I'd say yes. Provide ...

0

The FPGA does not have internal flash memory, just SRAM. Instead, it loads the configuration from an external flash chip after reset. Typical Altera developer boards have two programming headers, one connected to the FPGA's JTAG connections, and the other connected to the flash. If you want to write a persistent configuration, you need to connect to the ...

3

For part (2) - if the sensitivity list of a process contains other signals, and there is activity on those signals while clk = '1' then the process will operate multiple times per clock cycle. If it's a counter, that would be bad... Worse, synthesis would ignore the extra events (because there is no hardware feature to implement them) so simulation and ...

0

I was using a module that was not supported by Vivado. Apparently the machine I was working on had an old ISE installation and the cores got mixed up. That's why some modules were impossible to simulate and others worked perfectly from the get go. I think it should've worked, but maybe the licenses didn't match or the sources were unavailable for Vivado. I ...

2

Write the whole thing yourself, gives more control. Stop thinking frequency, and start thinking motor phase. What is the angle of the motor, and what do you want the angle to be shortly? Change in angle is frequency. Change in frequency is acceleration. Have a register that represents the motor phase. The top few bits of this will map onto the stepper ...

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If it is removing them, they are in fact unused, but it is not always obvious why. I think in your case, the reason is: .sample_in({8{sw}}), The synthesiser is clever enough to realise the bits in each word of your memories (smp_buf and vga_buf) are identical. As a result, it decides there is no point duplicating the hardware, it might as well just have ...

2

The problem is that pdm_clk isn't a port, it's a wire, and so won't be found by the get_ports search. What you should instead do, is target the actual register driving the signal. You can do this with something like (haven't checked): create_generated_clock ... {pdm_clk_div|clk_out} Where in this case clk_out is the name of the register inside the ...

2

I thought again about your inversion problem. The problem is that you or your PCB or your device swapped the RX+ and RX- wires for the transceiver input. Your GTXE2 is configured to a 20-bit bus and no 8B/10B encoding, so the direct inversion of each bit seen in your measurement is caused by the wrong polarity at the input pins. You can enable polarity ...

3

Simple answer. No, I don't think it is. There is a very useful online reference/help document which has pages describing Verilog constructs and syntax. It has a page on the $realtobits function, which state Conversion functions are not synthesizable. I can't vouch for the accuracy of the source, but it makes sense. The Verilog$... functions tend to ...

0

Either use multiple low pass filters and switch between them based on frequency, or have a single one with a high enough cutoff that the waves at 1MHz are not overly distorted. Your square wave would be the hardest, I would recommend using a separate circuit for it. Update: uint128_t Had a good explanation of how the LPF will affect your waves, also this is ...

2

First of all, the whole point of JTAG is that it allows test software to manipulate the pins of the device in order to test their external connections to other devices on the board. The ability to manipulate the internal state of the device is a secondary function. So, it should be obvious that it will be possible to cause the pins to execute the protocol ...

0

There are several ways the FPGA can get its configuration: The Spartan 6 LX9 FPGA has the ability to actively read its own configuration from the EEPROM via SPI. See dataseheet: p.4 The Master Serial Peripheral Interface (SPI) and the Master Byte-wide Peripheral Interface (BPI) are two common methods used for configuring the FPGA. The Spartan-6 ...

2

can a FPGA be re-programmed on the fly while a computer program with offloads to the FPGA is running? That is called partial reconfiguration, and is possible, under rare circumstances, namely, that you use the right tools (with pricey licenses), and partition your FPGA design accordingly, have made provisions that clocking the used parts runs on, and ...

5

In my experience, it's usually one or two seconds or at least 100's of milliseconds. It depends on how big is the FPGA and what interface (serial, parallel, etc) you use to program it. The time remains relatively constant as FPGA technology improves because as the FPGAs get bigger, they also add new higher-speed programming interfaces. To know for sure, ...

1

One solution is to write an XDC file including the required constraints and attach it to the entity name of the imported netlist using the XDC file property SCOPED_TO_REF. (Attaching it to a specific instance with SCOPED_TO_CELLS should also work.) When using the SCOPED_TO_REF property, it must be set to the original (top-level) entity named stored within ...

1

Figure two in the datasheet shows that analog value from 7 clock cycles ago is guaranteed to be on the output pins on the falling clock edge. As long as you stick to the clock requirements in Table 3, that's all you should have to worry about.

5

I have used daisy chained Xilinx devices with no problems. The key to programming the daisy chained devices is in the Xilinx iMPACT tool. I think the tool should discover both of the devices in the chain and give you the chance to assign a configuration file to each device. You can do this by right clicking the device and assigning a configuration file. ...

0

Hm ok, your question is 3 years old, I'm searching for something similar. I have a n unmarked CCD sensor from a HP scanner. This looks a bit like your device: http://pdf1.alldatasheet.com/datasheet-pdf/view/14892/PERKINELMER/LC1917.html And just came across this info: http://forum.arduino.cc/index.php?topic=136921.0 You could build a spectrometer with it: ...

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