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0

I had a similar issue with the cable not being found, no matter what port I would use, after I uninstalled/reinstalled the cable drivers and the numerous reboots (as recommended). In the end, I solved the problem simply by going back to an older version: instead of Diamond 3.3 that I was using, I installed Diamond 2 (good thing I had a setup of that version ...


2

If you don't have a PLL, you need a divide by 5 counter (to 20 MHz), a 1.5 cycle delayed version of the same, (use the opposite clock edge for 0.5 cycles) and an XOR gate (with the corrected version, an OR gate will suffice as both signals are never '1' at the same time) This will give you a 40MHz signal with consistent 40% (but not 50% ... edited!) ...


1

The best way would be a PLL as mentioned by the other answers - multiply by 4, then divide by 10. You could do x2,/5 but that doesn't get you 50% duty cycle (may not be an issue). But to add to those, there is a second option if no PLL is available, which is not recommended as it relies on asynchronous logic. It would go something like this: wire ...


2

Yes, there is a trick to do this. It's called fractional clock division and it's often done with a dual modulus pre-scaler. Here is a web page that gives example code in VHDL (sorry, no verilog): fractional-clock-division-dual-modulus Using these techniques you'll be able to get a 40Mhz signal out of your 100Mhz clock, but be aware that the jitter will ...


3

The simple prescaler you've implemented follows the formula $$ fout = fMaster \div (2 * (1 + prescalerN)) $$ where fMaster is the 100MHz master clock input and prescalerN is the prescaler reload value. There's not a whole-number divisor of (100MHz/2) that produces 40MHz. This is a limitation of implementing the prescaler in general-purpose programmable ...


6

The materials declaration is used if your product needs to comply with RoHS or other regulatory restrictions on material content. RoHS not only requires that your product not contain certain materials, but also that you document this fact. Typically, in order to do that, you need to request the vendors of all the components in your design to provide a ...


1

If you need real interaction at real speed, then no there is no alternative. You can get quite creative with the testbenches, but if you need to send to a display then you're not going to be able to do that in software. In some ways, FPGA is the simulator you're asking for; it's a simulation of an ASIC. (If it's part of the curriculum it really ought to be ...


0

I believe what you are talking about is having a Test Bench, a virtual environment used to verify a design. It can be done with any simulation software, like Multisim. You can either code a virtual approximation of what your inputs and outputs are in Multisim/etc. and have your FPGA simulation interact with it, if you're lucky this may already exist and ...


0

Based on your (very incomplete) schematic, you're supposed to use: an SPI master a controller for the ADXL362 that talks to the SPI master controller reads acceleration (X, Y, Z) and temperature (TMP), does necessary conversion and has the converted acceleration and temperature at its outputs along with a data_ready signal indicating valid output data. ...


0

I don't have an answer, as I don't know the internal details of Xilinx slices. I do have some pointers. First, you can't save data in a LUT6. You can only save data in registers (which are numbered 2/LUT6) and distributed RAM/blockRAM. Which somewhat annul your LUT6 = 64 bits assumption. Distributed RAM and shift registers are somewhat unrelated to LUT6 ...


0

If it's a video signal it will follow some format such as this VGA format: So you'd have to detect the sync pulses and generate a clock to drive the ADC to read the RGB video signals and store the ADC results (perhaps 3 bytes per pixel) in something like a bitmap (using counters controlled by a a master clock and reset by the sync pulses to address the ...


1

After taking a look at the SASEBO-W documents we find out that JP6 on the board is for FPGA Core Power and it must be Open to make this LED on.(The LED1 is specified with word Core on the board also.) Note that this is not mentioned in the Quick Guide manual, but you can find it in table 21 of Side-channel Attack Standard EvaluationBoard SASEBO-W ...


0

Anything higher than 300 MHz needs optimal design and environment conditions. Even if frequencies higher than that are observed on the Oscilloscope they would be attenuated and not of the right voltage level. To achieve higher clock speeds you need to get faster FPGAs (Kintex Series etc.)


0

Your device is a Spartan-6. In this family, the DCM primitive is DCM_SP or DCM_CLKGEN http://www.xilinx.com/support/documentation/user_guides/ug382.pdf. I have used: Library UNISIM; use UNISIM.vcomponents.all; I_DCM: dcm_clkgen generic map ( clkfx_multiply => 3, clkfx_divide => 8, clkin_period ...


3

You can use the memory IP cores to create a memory with initial mif content. You can check the IP core user guide for more information. Another solution is to use VHDL attributes to initialize the content of your variable. You have to be confident that your code is indeed interpreted as a ROM by altera, otherwise the attribute will be ignored. This is the ...


0

I think you're on track so far. The milf file should be used as intended. The cyclone II's digital to analog converters are possible with IP core.


1

You set a pretty high bar by looking for both cheap and high performance in terms of data rate. The only way I can think of meeting those goals is to use an inexpensive FPGA dev board to do the heavy lifting. A $30 board that would do the job is here: http://parts.arrow.com/item/detail/arrow-development-tools/bemicromax10#22zM But this would require writing ...


0

Here is a sample implementation of an Ethernet CRC in VHDL, suitable for a test bench: TYPE arr_byte IS ARRAY(natural RANGE <>) OF unsigned(7 DOWNTO 0); CONSTANT CRC_POLY : unsigned(31 DOWNTO 0) := x"04C11DB7"; FUNCTION crc (data : arr_byte) RETURN arr_byte IS VARIABLE r : arr_byte(0 TO 3) := (x"00",x"00",x"00",x"00"); VARIABLE c : ...


-1

It took me a few hours of guess and check to figure out what exactly is needed and what isn't. The project I inherited used the project directory as the implementation directory (where it dumps most of the temporary files). See below with what I came up with. Note that this is by no means complete, there are lots of features to Diamond that I am not ...


0

Wireshark will capture it unless your NIC drops it due to the bad CRC. Also, I think the FCS of that packet should be fdd0f69b. Don't forget that there are some odd bit reorderings that you have to do for the CRC to work out correctly. Note that there are also open source implementations of this that you can use for reference, for example ...


-1

A gitignore file isn't that hard. Why don't you just add the files/directories you don't want git to track to ti. .idea/ estc_modules/__pycache__/ reg_files/__pycache__/ *~ *.pyc *.pyo *.swp *.bak


3

There are several possibilities: You can use ChipScope. That's an on-chip logic anaslyzer, which is synthesized into your design. You can implement (or use) a FPGA to PC communication like UART to write numbers and read results. You can implement a testcase in hardware (like your testbench) that enlights a LED if the testcase is passed. ...


0

About power consumption. You are comparing microcontroller and programmable logic devices. That's absolutely wrong, because, FPGA consumption depends of a lot of points, as frequency, occupancy, etc. Habitually FPGA software packs provide a tool to estimate the power consumption of a programmable logic design, but to know the real consumption you must ...


0

In use many years ago a manual technique existed called "The Algorthmic State Machine Method",(ASM) Dr. D.H. Green of the Univesity of Manchester Institute of Science and Technology authored a book on it. Not sure if the book is still in print, I doubt it. The technique was based on designing finite state machines but an intrinsic part of that was the ...


0

I think you are confused about what a LUT (Look Up Table) is. A LUT is just a memory initialized with fixed values that do not change during normal behaviour. In a FPGA architecture you have basically LUTs combined with registers. These LUTs are initialized with the values of a truth table to define a combinational output logic of some inputs. In the case ...


0

Best practice is not to use clk_slow as your state machine clock. Use clk for your state machine and make clk_slow a sort of flag. always @ (posedge clk or posedge rst) begin if(!rst) state <= S0; else if (clk_slow) state <= state_n; end (I don't usually work in Verilog so please verify the syntax)


5

Your measurement is not correct. The duty cycle is measured at 50% (\$\frac{1}{2}V_{dd}\$). So measure again at 1.65 Volt, if \$V_{dd}\$ is 3.3V. The 'real' high and low times: - above 90% of \$V_{dd}\$ is high - below 10 % of \$V_{dd}\$ is low does not matter. If a circuit has special requirements for the clock or data signal, it defines rising and ...


6

The warning you are seeing is most likely WARNING:PhysDesignFules:2410 - This design is using one or more 9K Block RAMs (RAMB8BWER). 9K Block RAM initialization data, both user defined and default, may be incorrect and should not be used. For more information, please reference Xilinx Answer 39999. I just got this warning myself a couple of days ago and ...


3

always @ (posedge clk_slow or posedge rst) //state changer begin if(!rst) state <= S0; else state <= state_n; end If you want an asyncronous active-low reset, this always block should be sensitive to negedge rst instead of posedge rst. If you want an active-high reset, then the condition in your if statement should be rst ...


3

There are three ways todo this (forth listed for completeness) and it comes downto space-time tradeoffs: Do you do the calculations ahead of time (storage space) or do you do the calculations on the fly (time tradeoff) 1) Look up table. Do the calculations ahead of time & store the information in a ROM/table. By realising you only have to store 1/4 of ...


1

Generally the way you do this is with a lookup table stored in a block RAM. For example, you could use a 1024 entry table with 8-bit entries. The entries would be calculated with sin or cos and stored in the RAM in an initial block. Then you would use a phase accumulator to read the samples out of the RAM at the correct times and send them to the DAC. If ...


2

The LUT is loaded with data with the internal configuration logic. Extra logic inside the FPGA (hard logic, not LUTs) reads the configuration bitstream (sof or bit file) from an external flash chip or from the JTAG interface and then stores it into the correct locations inside the FPGA. This includes LUTs, block RAM, clock management components (PLL, DCM, ...


2

A two input LUT (lookup table) is can be represented generically like this: A LUT consists of a block of SRAM that is indexed by the LUT's inputs. The output of the LUT is whatever value is in the indexed location in it's SRAM. Although we think of RAM normally being organized into 8, 16, 32 or 64-bit words, SRAM in FPGA's is 1 bit in depth. So for ...


7

A LUT, which stands for LookUp Table, in general terms is basically a table that determines what the output is for any given input(s). In the context of combinational logic, it is the truth table. This truth table effectively defines how your combinatorial logic behaves. In other words, whatever behavior you get by interconnecting any number of gates ...


1

Examining the resulting core with PlanAhead I have discovered that synthesis report files generated by XST synthesizer of 13.2 and 14.4 versions provide erroneous occupancy values. This bug is resolved in 14.7 version and the real occupancy value is 36%. In fact, always have been 36%. Jonathan, thank you for the advice of using PlanAhead!! Best regards


0

I see two (similar) paths: use an FPGA programming tool, like Xilinx ISE or Vivado (WebPack is free for both), entering your initial expression in Verilog (for example) and seeing its optimized version as RTL schematics after structural synthesis (first step of compilation, optimization must be enabled). http://www.xilinx.com/support/download.html use a ...


2

There was a small market for PCMCIA based FPGA addon cards, but PCMCIA is dead. I can't find any references if these cards got updated to Express Card. If you are seeking for FPGA boards with USB 3.0 support there are some exemplars like this: https://www.opalkelly.com/products/xem7350/ If you want to do "high-performance computing" with FPGAs you will ...


1

They tend to have PCIe form factors because it is a modern bus used in many high speed applications - I'm currently developing a PCIe Gen3x8 application around an Altera one. But if you don't need the PCIe capability, it is possible to use these boards stand-alone. They tend to have external power supplies which can be used if not connected to a ...


0

Buy an express card to PCIE adapter. The express card slot in any modern laptop has a 1x PCIE bus. All you need is the right adapter to connect the board. Usually they are made for using an external video card, but the type of device shouldnt matter.


1

The memory read needs to be registered to be recognised as a block RAM: process(clk) if rising_edge(clk) then ctr <= ctr + 1; cos <= SINE_TABLE(to_integer(unsigned(ctr))); end if; end process; I would also make ctr of an integer type - then you don't need to faff around with the conversions.


3

Move the take lookup right next to the increment so the output is registered. That is a gigantic lookup table, though. You may want to consider using a compressed lookup table to save on the block RAM. The trade-off is you may need a couple of multipliers. Here is an example of a pipelined, compressed sine lookup table: ...



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