# Tag Info

7

The bitstream that controls the functionality of your FPGA is normally called the "configuration", not the "software". The configuration bitstream is generated by using FPGA synthesis tools to compile the Verilog/VHDL source code. There are a number of different ways that the configuration can be transferred into the FPGA each time it "boots up". Roughly, ...

1

Unless the attacker can reprogram the logic, read the flash/eeprom/boot rom or access your programming files on the computer the answer is no. There really is no way to fully determine the switch settings in the layer of cells that contain the configuration setting unless you have direct access to them through the JTAG / programming port. You may be able to ...

0

Looks like it is a problem with Quartus II software. I am using version 13.1, other versions may have this issue resolved. Same question posted here and solved it by configuring the waveform editor to use Quartus II Simulator rather than ModelSim (which is the default).

1

The practical FPGA register (a set of D flip-flops) only has one clock pin so it serves exactly one clock domain. Keep this low-level hardware in mind when writing HDL code. When a signal crosses from one clock domain into another, it's common to use a pipeline of three registers, with the first stage in the source clock domain and the second and third ...

0

The difference between a CPU and FPGA is parallelism. FPGA's are very good at performing a number of (logically) simpler tasks at once with minimal delay. More complex logic and sequences of operations are better catered for by the CPU's ALU (Arithmetic and Logic Unit). If you are interested in a common software emulation of gate design, which is typically ...

0

Other answers have addressed the specific questions at a nuts and bolts detail level, but I think there is an opportunity here to look at it from a different angle. Processors today have many millions (billions in current generation desktop CPUs) of transistors implementing a comparably large number of gates. While only a few of those gates are actually used ...

0

As you have observed, the contents of the lookup table determine whether a certain LUT is an OR gate (0, 1, 1, 1), and AND gate (0, 0, 0, 1), an XOR (0, 1, 1, 0) etc. The lookup table itself is implemented using hardcoded gates, i.e. the result is (lut[0] AND NOT a AND NOT b) OR (lut[1] AND a AND NOT b) OR (lut[2] AND NOT a AND b) OR (lut[3] AND ...

12

Actually your first guess is not as afar off as some are claiming. A CPU is built around something called an "Arithmetic Logic Unit" (ALU) and a simplistic implementation of that is to have the logic gates implementing all basic operations wired up to the inputs in parallel. All of the possible elementary computations are thus performed in parallel, with ...

1

The CPU doesn't just have 'a number' of pre-build logic gates. A modern processor has between around 50 million to several billion transistors, corresponding to many millions of gates. The CPU already has all the resources needed to execute your C++ program. The resources provided fulfill the instruction set defined by that hardware platform, be it x86, ...

7

Pretty far off. A CPU is made up of real gates (not programmable LUTs). The key operations on data are done in a block of logic often known as an ALU (arithmetic-logic unit). Inside this block is a set of gates that can, for example, AND two operands together, bit-by-bit. There's another set of gates that can add them together, and so on. When you execute ...

1

I would use a shift register - use a constant to initialise it to your desired pulse train when reset is asserted and then just clock it out. Your top-level entity will only need three pins, clock, reset and the output.

2

A concurrent signal assignment statement of the form: OUTPUT <= CLK AND VAR; Has an equivalent process (how it's simulated) of the form: process begin OUTPUT <= CLK AND VAR; wait on CLK, VAR; -- wait on 'sensitivity list' end process; With the wait statement the equivalent of putting both right hand side signals in a sensitivity list. ...

10

Yes, it's because you are using the "silicon" oscillator. The basys2 board also provides a socket for a crystal oscillator. If you plug in a crystal oscillator and use its clock signal the jitter is gone and the VGA image will be fine. I have tried it myself. BTW: The manual tells you about that: The primary silicon oscillator is flexible and ...

2

Physical layer Are the 64 GPIOs all you have or do you have any other connections between the FPGAs? As indicated by Martin Thompson, for bandwidth you'd be better off using high speed serial connections if available. Assuming your original post contains all the relevant data and you only have 64 GPIOs then you'll need to think about how you're going to ...

1

As it's Xilinx, you could look at using Aurora to interface between the FPGAs - you'd have to implement your own memory access protocol over the top of it, but it allows you to easily get very high bandwidth between chips using the inbuilt SerDes (GTP) pins. It will handle all the lane matching and channel bonding and save you from the pain of trying to ...

2

You can right click on a warning message, then go to "suppress", then choose between various "quick" suppress options or pop open the Message Suppression Manager that allows you to visualize, edit, import and export all the rules you want. As OP says in the comments below you can also use the * wildcard, so to suppress all pcie messages he wrote *pcie* and ...

1

This absolutely depends on the mouse. I have a USB Microsoft mouse that comes with a similar USB to PS2 adapter. The mouse can sense the difference and reconfigure itself to produce the different protocol but the mouse is marked as such. 99% of the time these adapters are wiring only - there is no intelligence whatsoever within them. Two things to bear in ...

1

You need something like this. However, the device must have a VCO in order for this to work. The circuit works by changing the frequency of a voltage controlled oscillator (VCO) based on the phase difference of two clock signals. The first signal of the two, $F_I$ in the diagram, is the reference signal and in the case of a PLL it is generated by dividing ...

0

There really isn't one answer as there is so many different ways to instantiate a synthesizable design. One way would be to use your synthesizable RTL and resynthesize it with another tool and target a different library. For hand counting, you just need to look at your Mults, FFs and LUTs. The slices are organization hierarchical blocks and taps are ...

2

Implement a DDR controller on FPGA B. Attach the DDR controller to a shared memory interface controller. Attach shared memory interface bus A to FPGA B internals. Attach shared memory interface bus B to FPGA B I/O pins. You may need to make some compromises, of course - 32 bits for data, 31 bits for address, 1 control line probably isn't going to work; ...

1

If you cannot connect the FPGA A to its own bank of memory, then I would venture to say that the 400 MHz GPIO lines between the two are your best bet. Using them in basic SPI configuration or something. If the board is routed properly, you could attempt to do some sort of PCIe communication between the two but that is very circumstantial. You could ...

5

Considering your request a classic serial interface will do the work perfectly. From a HDL perspective a serial transceiver is easy to implement, so I think you should start from here. Your board has no RS232 connectors, but you can easily use the expansion headers in order to connect a FT232 chip, that convert your serial interface to USB. With a ...

2

Yes - you should be debugging in simulation rather than using chipscope on the hardware. For complex designs you will almost certainly save time in the long run by simulating. Xilinx provide some help for simulating PCIe, you should first try and simulate the example designs (see here for Virtex 7 or this Answer Record for 6 series). Since you are ...

3

If you want to do it all in hardware... Good luck. You need to implement the USB standard, or at least a part of it, then find a way to translate whatever your ADC sends in usb packets. If you can integrate a processor in your FPGA that would be so much simpler. With altera you can integrate the nios II processor, so I believe xilinx has its own processor. ...

2

Vivado 2014.1 allows for the usage of .tcl scripts to regenerate projects. To do this, with your project open, go File -> Write Project tcl. Basic Projects I usually store my sources and .tcl script in a location outside of the project directory. The xilinx IP cores generated within the project may be copied elsewhere by right clicking on the core and ...

1

Async FIFOs are characterised by their static latency, expressed as a number of complete cycles in the source domain (before the crossing) and in the destination domain. The crossing itself introduces jitter if there is not an exact phase and frequency relation between the two clocks. In your example you say the phase wanders, for this to happen the clock ...

0

I agree with @Martin Thompson answer, but I would like to add that: VHDL is not a computer language like "C" or "java". You cannot convert sequential code to hardware description language. Of course, you can describe a piece of hardware that does the same function than the posted code. But in any case it won't be "VHDL code running on the FPGA". If you ...

4

If you're struggling to catch the VHDL concepts, don't start with that kind of project! Start smaller. First, flash an LED at 1Hz. Now build a simulation for the same code. Normally, you'd build the simulation first, but I know that most people really want to see some hardware working ASAP! Now wire up a pushbutton switch to the FPGA and use it to ...

0

There should be an answer to this question in the manufacturer's data sheet. I know it's a large document, but I suggest you dig through it. Also, jitter is not the right word to describe what you are talking about. Jitter refers to random variations in clock frequency on a single clock. What you are talking about is clock offset (which will vary based on ...

5

'retiming' logic usually refers to inserting pipeline stages to make timing constraints. From your description, some of the pipeline stages are made optional controlled by this parameter. If you can't close timing in the area of this core, enable it.

0

image if you had a signal sequence in time like this 0000000000000000000010101010111111011111111111111 how might you detect the transition from 0 to 1 once, but since it could eventially go back to 0 some time, this must be only ignored within a given window. Think of the signal changing as an "event". You might also have a "hardware input" and a ...

5

Generally speaking the way FPGAs are designed if your data were stored in a RAM style memory and the processing done with a simple micro controller the only increase in processor size you should see should be your addressing width and related signals/modules (IE cache). Controllers are generally designed to scale nicely with increasing memory spaces, after ...

12

I'm assuming that you are performing a data processing operation on 1500 16 bit words. In general FPGAs allow the trade off of reduced area for decreased speed and increased complexity. Let's say your algorithm was autocorrelation which is something that has n2 complexity, and would fly at 100 elements but take forever at 1500 elements (225 times longer). ...

2

Developing an FPGA is a knowledge based skill. There's a delicate balance between abstraction and understanding, and the reason tutorials tend to be so long is based on the least common denominator for understanding by their audience. No one teaches the process in abstract before 'practical' experience because of some ingrained believe system people have ...

2

I'll go for the "low hanging fruit" here. I'm not going to type out an entire tutorial but I will link you to here: http://micro-nova.com/mercury/examples/getting-started The guide uses Xilinx's ISE development suite to show how to blink LEDs for a "Helloworld" application. This guide specifically applies to the Mercury FPGA board. If you have some other ...

Top 50 recent answers are included