# Tag Info

4

This is normally called ringing and is common. If there is just single pulse then it is referred to as overshoot. As you surmise it is caused by unintentional LC elements in the wiring being excited by the fast edges of the signal. Even one or two inches of wire may create enough inductance to cause this effect. Often it is exaggerated by bad grounding of ...

5

How long is the ground lead on your scope probe? your scope probe should be in the X10 position and be properly compensated. Remove the long ground lead that came with the scope probe and also remove the probe grabber hook from the front of the probe. Grab some #22 or #24 bare wire and wrap 2 or 3 turns around the exposed metal ring at the front of the ...

0

your scope says 10Mhz right on the front; that's the 3dB bandwidth. So the 1Mhz fundamental gets through without much distortion, but only up through about the 9th or 11th harmonic... so the square wave will appear to have some ringing at the edges. this is normal. a higher bandwitdh scope would show the 1Mhz signal with crisper edges, but there will always ...

0

Sorry for posting this late. I have finished the project I'm working on months ago. The code above worked, there is nothing wrong in my code and in the pin assignments. The problem is on my hardware connection. During my testing, wherein I used the code above, I connected the GPIO pin for input to an LDR (light dependent resistor). That being said, since ...

3

It's a big question, much too large to answer here, but here are two elements: different building blocks: neuromorphic chips wouldn't be useful without a theory behind them. So they're made with the aim of transfering neural network models to them, and they try to offer the best building blocks for that: neurons, synapses, etc. Typically a pure hardware ...

0

After working around, I finaly find out how. Synplify Pro is the synthetize but you don't need to open it. In Diamond, you see this panel when you are in the workspace: Click on the second tab "Process", in my case it was hidden from my screen resolution The following window will open and as you can see there is the ouput file generator. In my case, the ...

0

You are talking about a task that would take an experenced embedded software engineer weeks to acomplish if not provided by the vendor (Lattice) unless they are very experenced with both embedded Linux (most are) and Lattice (most are not). The tasks involived would include: Implementing a micro-processor (either Lattice supplied, or opencores probably has ...

1

The problem is, that your program doesn't really end. After you've executed your two instructions the picoblaze will continue executing. Eventually the instruction pointer will overrun and your program restarts from address zero. You need a way to halt your picoblaze. You can either do this by adding additional logic to gate the clock or put an endless loop ...

0

Make a vhdl component that halts MicroBlaze until it is finished counting to whatever size the DDR3 memory is, and each count it fills the area with either a (others=>'0') or a (others=>'1') to fill that byte, word, or quad of memory. hope this helps..

1

The absolute maximum input voltage for LVCMOS33 on spartan6 is 4.1V, anything higher than that (even for a short time) may damage your FPGA permanently. Check out the info on: Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Use a resistor in series or a voltage converter before connecting 5V source into any LVCMOS33 input of your FPGA.

3

Yes. There are ESD protection diodes to Vccio and these will turn on if the pin is supplied with a voltage higher than Vccio. It may be possible to add a series current limiting resistor and use the ESD protection diode is a clamp, but this is not recommended. You should look in to using some sort of external level shift circuit to prevent damage to the ...

1

The presented four-phase synchronizer is a good and correct implementation. It has only one disadvantage: It has a V input, to notify the synchronizer of changed inputs. This can be automated by a n-bit register in the source clock domain and n-bit comparator: if input changed, assert V=1. Input_d <= Input when rising_edge(Clock); V <= '1' ...

2

As I interpret your diagram you can connect each group of 4 input/outputs to the I/O pin group [1..4] of your choice. That is a crossbar. But in FPGA1 you can't choose to which I/O pin within the group your A connects: the connections within the group are fixed A->1a B->1b C->1c, D->1d. In FGGA2 you can (probably) switch the lines within a group, but you ...

6

USB is much too complicated SPI and I2C can't be interfaced directly to your PC. A serial interface (UART) is quite simple to implement in a FPGA. You just need to add a level-converter (e.g. MAX3232 3.3V ↔ RS232) hardware. In case your PC doesn't have a RS232 interface you can add an off-the-shelf RS232-USB converter (5 EUR) or use a ready-made 3.3V ...

0

I highly recommend the Open Workbench Logic Sniffer from Seeed Studio. Note the triple 'e' in Seeed. Cost is US $50 and the board includes a Spartan3E XC3S250E-VQ100 FPGA as well as a PIC18F24J50 used to talk to the FPGA. There are 16- Input-only pins buffered with a M74LCX16245DTR2G (tolerant from -0.5V through +7V) and 16 more i/o pins brought out to ... 1 Mirics has a nice chipset for FM SDR that includes the RF front-end, tuner and A/D and exports I/Q samples over USB. Here's a nice discussion about the part: http://www.reddit.com/r/RTLSDR/comments/2yjhvr/information_on_mirics_chipset_for_general_sdr/ I understand that this product uses the Mirics chip, but I have no experience with it myself: ... 0 Most FPGAs contain internal ring oscillators for managment purposes. Things like configuration loading on startup (where do you think clock for master SPI and master selectMAP comes from on Xilinx FPGAs?). In some cases, it is possible to access this oscillator. Looks like this is possible at least on the Virtex 6 and Spartan 6. On these devices, the ... 1 For constraints, do something like this: NET "clk_P" LOC = "K15" | IOSTANDARD=LVDS_33; ## 6 on U5 EG2121CA, 4 of U20 SI500D (DNP) NET "clk_N" LOC = "K16" | IOSTANDARD=LVDS_33; ## 5 on U5 EG2121CA, 5 of U20 SI500D (DNP) NET "clk_P" TNM_NET = "clk"; TIMESPEC "TS_clk" = PERIOD "clk" 5 ns HIGH 50%; You only need to constrain the P side, as per ... 1 Here's a better picture: From the name it's an Excalibur board which is from Altera. It came as an Excalibur Development Kit. You'd imagine the board was available separately. It dates from 2000. Silicon is still available albeit at a dear cost. The place to look for support would be on the Altera site. The place to begin might be on the Excalibur ... 1 This smells like something could be wrong with your user logic that results in a lot of it being optimized away. 4096 of anything should take up a LOT of logic resources. Does the 4096 element design function correctly on the actual FPGA? 1 As integrated circuits get smaller feature sizes they get less of a risk from failure from single event upsets (SEUs). This is because the single transistor area is less, reducing the chance for a hit by a energetic particle. This makes modern FPGAS less vurnerable to SEUs. FIT is usually specified as expected failures per billion hours of operating time. ... 2 Is this at all possible? Sure, but you'll need a frame buffer in order to increase the frame rate. This would be in the form of external SDRAM, since few FPGAs have enough on-chip memory for a megapixel image (3 MB minimum). The up-scaling in resolution is relatively easy, since 3840×2160 is exactly 3× the size of 1280×720 in ... 1 You could look around for an old ML506 or ML507 from Xilinx, but really$1300 is a reasonable price for these boards. There is one other option I can think of: the Raggedstone 2 from Enterpoint, at prices from about \$400 upwards according to the FPGA (Spartan-6, different sizes). They have a range of other options with up to 25 FPGAs, but probably outside ...

3

For a PLL Clock multiplier, where does the new clock come from? Usually it comes from a voltage controlled oscillator (VCO) - it runs at the higher speed and then there is a digital divider that reduces this frequency to what would be nominally (say) 50MHz to match your reference crystal frequency. The PLL has a frequency/phase (PFD) detector that ...

0

A PLL is a normal voltage controlled oscillator (VCO). This VCO first generates a wave that is roughly the right frequency, and then the feedback mechanism is used to tune it. For tuning, the phase of two (slower) clocks, generated by dividing the input and the output clock, respectively, is compared. Multiplication works by dividing the output clock ...

5

If this is a "white box" design, i.e. you already know the hardware design (schematics / netlist, or Boolean design equations) then you can begin by translating the hardware design directly into Verilog or VHDL hardware description language. (Both of these HDL languages are open-source standards, and for most purposes either one will be fine.) If the ...

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