New answers tagged

1

You can send a signal on to many many other destinations (the number of destinations is called the "fanout" of the signal). The more destinations it goes to, the longer your critical timing path potentially becomes though, so the fmax of your design may suffer. The tools will usually replicate the logic that drives those many nets if the timing becomes ...


1

The *.lpf file does indeed describe the pinout of the FPGA, however before explaining the lines, you should know that there is an easier way to assign them using the Lattice Diamond design software and there are some great tutorials out there showing how to do this, I've just found this one: https://youtu.be/SmdEP_ZsBgM He starts assigning pins at about ...


0

The second part of your question (2D array vs. RAM) really comes down to the resources available on your FPGA. Usually storing something as large as an image or frame of video in logic elements isn't recommended, the logic that is created during synthesis will be huge and your compiler will take an age to fit it in the FPGA if it fits at all. You should be ...


1

What you have to do is package sub modules as IP. Then you can use the IP as sub modules in a bigger design. The problem is that you can only package a whole block diagram. What you have to do is create a new block diagram, insert the blocks making a sub-module, package it as an IP and then add it to the main design. Repeat for all sub modules. Created IPs ...


1

See code below to combine 3 files together. --- top.vhd library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity top is port ( clock : in STD_LOGIC; clear : in STD_LOGIC; sel : in STD_LOGIC; y : out STD_LOGIC ); end top; architecture beh of top is signal freq1 : std_logic; ...


2

The majority of routing looks like MUX selections based on a fixed bitstream. Below is a fuse chart for a Manhattan-style FPGA that I made that was very similar to an older Xilinx 4000 series (Choices made because I have the graph router). The CLB contains 4-BLE blocks. The truth table from the LUT has 16-bit with inputs form the MUXes on the input lines ...


-1

There is actually some memory that controls the mux, in most FPGAs it's sram, some CLBs use eeprom and some low power CPLDs use flash, it's the memory that's being programmed when the chip is configured, it's not really user accessable as each manufacturer uses their own special way of structuring the configuration files but the configuration files program ...


3

Looking at a more detailed description of the slice (on page 204 of this UG) will provide us these details. As you can see, the select signal for the FiMUX comes from the BY input to the top half of the slice and the F5MUX is controlled by the BX input to the bottom half. These two inputs have additional functions and are described on page 207 of that same ...


0

Something important to remember is that sometimes FPGA development boards (buttons, LEDs, etc) are active-low. Meaning, the buttons are at '1' when they are unpressed, and '0' when they are pressed. The LEDs in this FPGA seem to be active-low as well (so they switch on when they are assigned '0'). This is my conclusion from looking at the schematic for this ...


2

If nothing else, you want to write out "PASSED" or "FAILED" to STDOUT or a file, which means that you need add some amount of checking to your testbench, not just stimulus. This way every time you make a change to your design, you'll have a quick way of knowing how the change impacted the specified functionality. As your design becomes more complex, you'll ...


5

There are tons of reasons to do this. Waveforms are often not enough, especially if say you are doing some behaviour modelling, or you need to see the impact of your implementation,or there is just too much data ... One example might be you're designing a video processing circuit that needs to implement a specific output and you need to make sure your ...


2

I had to do it in a test bench of a small processor. Basically, I was providing a file containing the instructions, the verilog/vhdl was reading the file and executing the instructions. Then there was a special processor instruction, used at strategic locations, that dumped the current registers values in an output file. When the execution was over, I was ...


1

The structured procedural statement 'initial' is not synthesizable. To initialize the value when your fpga powers on, you can give initiate the value of the register by giving the value at the time of declaration. eg. reg [3:0]shift_reg= 4'b0000;


1

Alex, my advice is: double double check identifiers of bottons and LEDs. Use combinational logic if you have no specific requirements of behavior modeling. If you do want to have a behavior-modeling procedure, make sure that default electrical level is correct.


2

I will make some assumptions: since this is mixing audio, you will want to sequentially read all of the ADCs at some fixed synchronous rate (like 96kHz), and sequentially write all of the DACs at the same rate. I think the PRU will be the easiest way to implement a fast data-pipe to/from an FPGA. There are two PRU processors in a AM335x Sitara processor, ...


1

The Virtex-5 XC5V110T is for example mounted onto the Xilinx XUPV5 board. This board is equivalent to the ML505 board: same pin-out, same external devices, but a "bigger" FPGA. All Xilinx references regarding the XUP5 board are listed here. The undocumented and incomplete Master UCF Pin Constraints file can be found on the same website. Our PoC-Library ...


4

There is no such thing as a "default UCF file" for a Xilinx part. The names and functions of pins are entirely dependent on your board design. Use the Xilinx ISE Constraints Editor or PlanAhead to create a UCF file.


2

In many cases FPGAs don't support power-on initial values of anything but 0. I know that all the Altera FPGAs I've worked with don't. In fact according to the datasheet for your FPGA, this is indeed the case: Each DFF also connects to a global reset signal that is automatically asserted immediately following device configuration. Global reset suggests ...


1

I have successfully driven both the Xilinx ISE and Altera Quartus toolchains from makefiles in linux. Occasionally I have had to use various gui tools to generate configuration files for various components and then use makefiles to drive the generation of the actual hdl/netlist from that with makefiles (coregen, megafunctions, qsys, etc.). Vivado is a ...


5

The state of FPGA EDA tools is awful, in my opinion. That said, here's my tool-flow for each of the major vendors: Design / initial work is done with the GUI they provide. No way around this, especially if you want to use IP Cores. This is on Windows. You can run the GUIs on Linux as well, but in the past, the Windows versions have gotten the most ...


4

For Xilinx FPGAs, the Answer Record AR# 44174 confirms that: Timing violations can occur with flip-flops and SRLs since GWE is releasing synchronous elements with respect to the configuration clock instead of the user's system clock. Propagation of the GWE signal means SRLs and flip-flops might be released at slightly different times which results ...


1

If I understand your design correctly, I think you have a design issue that needs to be addressed first. You are grabbing data from one of several UART receive buffers and shovelling it directly into a UART transmit buffer. This will have the impact of mixing up bytes from each of the incoming buffers into the output stream with no apparent way of unmixing ...


4

You should assume the clock input to your flip-flops is toggling unless you can prove otherwise (by a guaranteed power on or post configuration delay). All the flip-flops on a given clock domain are not guaranteed to start on the same clock edge based on GWE or GSR. Both act like an asynchronous reset and cause potential problems for some logic (counters, ...


1

I wrote this TPG for a project of mine. Maybe it can help you. Create a new Vivado Project. Import the code and generate a IP. Now you can import it into our project. The output is raw Bayer, but it can easily be adopted to output RBG or YUV. ------------------------------------------------------------------------------- -- Entity: testpattern_axi -- ...


4

A clock and a counter. Where you enter the wait state, you set the counter, then decrement it on every clock cycle, and when it reaches zero, you exit the wait state.


7

Because this line: last_clk_val <= count_clk; is outside of the clocked process, both signals will have the same value in hardware (and also in simulation after a delta-cycle1). Thus, this condition within your process if (last_clk_val = '0' and count_clk = '1') then will never be true and the process will be equivalent to: process(clk, reset) ...


0

I have found a satisfactory answer and need input for it. I feel we should use Nonblocking statements for both combinational and sequential statements. For sequential it is pretty clear y we should use. I will describe the reason for Combi Blocks. For eg. take the following code module block_nonblock(output logic x,x1,y,y1,input logic a,b,c); always@* ...


2

I haven't tried to understand what your code is trying to do here, but your error shows a misunderstanding of one of the fundamentals of how your code will run: v_clk := sys_clk; -- '1'; You have assumed that because your process works from the rising edge of sys_clk, that when your code reaches this point, sys_clk will have the value of '1'. This will be ...



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