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Variable sample rate is different then skipping samples, i was thinking the same way as those replys, and trying to find out the same as the topic starter. link as proof its different : http://www.electricdruid.net/index.php?page=info.wavetableoscs


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You could always just use the enable line on a DFF instead of mucking about with the clock frequencies and perhaps forcing the a signal not routed to be a clock to be used as a clock. Count the 100MHz pulses, and every time it hits 2 (or any divider), turn another signal on. This other signal then enables your DFF. This way you have your stable 100MHz clock ...


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During normal operations, CLK is always driven, whereas CMD and DATA are bidirectional. CMD must be pulled-up as frames begin with a low start bit and end with a high stop bit. DATA[0] is used as a busy signal and must also be pulled high. The other data lines DATA[1:3] could be left unconnected, but it is better when CMOS I/O are not left in high ...


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Constraints file is only used to apply various constraints on the design. But the code which generates 50 MHz clock needs to be written by you.You can use a frequency divide by 2 code wire clk_50MHz; always @(posedge clk_100MHz) clk_50MHz <= ~clk_50MHz; But to let xilinx know that this clk_50MHz is not a normal signal,you need to let xilinx know that ...


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Have a look at the following part ECLAMP2410P which is a protection devices intended for microSD cards with pull-ups included. There pull-ups are on DAT[0..3] and CMD but not on CLK.


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For primitives, absolutely no benefit performance wise. The only use is it means you don't need to create files with your own primitives in, but if you rely on the Altera ones then migrating to something from another manufacturer would be harder. Some things like FIFOs may contain Altera specific inline timing constraints or other synthesis directives for ...


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Refer to Chapter 4.1 of the User Manual, "Configuring the Cyclone III FPGA". Specifically you want to be looking at the section on configuring the EPSC4 module in AS mode. For reference (and in case the link becomes invalid), what you need to do is power up the board, connect the USB cable as normal, and then switch the "PROG/RUN" switching into the "PROG" ...


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Altera makes special eproms they call "Configuration devices" that can be used to store the FPGA configuration, and will be read by the FPGA on power-up. Using these things will be discussed somewhere in the Altera FPGA documentation.


3

As you said it has an arm core, they also tend to have a smaller amount of fpga resources compared to a similar price fpga only part. It's neat that it allows the a direct access to the fpga fabric and if remember right it can also share a DDR interface between arm and fpga section. It's nice if you need to run part of your application in software like ...


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I am not familiar with your environment (Nexys 3, etc), but I think the following should be correct in general. When you add the IP core, it creates a block of logic inside the FPGA with the ports being the interfaces internal to the FPGA. Most of the interfaces, you need to connect to internal logics that you define. Parts of the interfaces, you may map to ...


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The configuration of an FPGA is stored in special SRAM cells (less transistors and lower static current) or in flash memory. This memory needs to be 'read' at every time otherwise the path transistors won't work. DRAM can't be read continously. Producing normal CMOS logic and DRAM logic are different processes. DRAM needs other machines and materials. This ...


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What you require is Espresso heuristic logic minimizer radically different approach to this issue is followed in the ESPRESSO algorithm, developed by Brayton e.a. at the University of California, Berkeley.[7] Rather than expanding a logic function into minterms, the program manipulates "cubes", representing the product terms in the ON-, DC- and ...


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For implementation of a complex boolean function it is normally done either by putting in an FPGA in which case the FPGA software will do the minimization (not necessarily into gates but more likely into LUTs) or you can directly put the table into a memory (FLASH, RAM whatever appropriate). For the memory implementation the binary input signals form the ...


1

I have implementations of double-precision, floating-point multiply and divide. The multiplication takes 13 clock cycles and the divide takes 109 clock cycles. Both are pipelined for 100% throughput (one result per clock) and around 200MHz operation on a Xilinx V5. I don't know how many fewer clocks you could get at 100MHz, but dividing by two would be a ...


1

The highest external reference clock I know of is 200 MHz with differential signaling. There are 2 ways to increase this frequency: As descibed by Tom you can use a Clock Modifying Block (CMB) in the FPGA like PLL, DCM or MMCM to generate a high frequency clock that is a multiple of your reference clock. Some FPGA boards are shipped with programmable ...


2

You do not necessarily need another FPGA board for this purpose. Most FPGAs have clock multipliers as primitives (for example, Xilinx FPGAs having DCMs and other tools that allow multiplying and dividing clocks, and Altera having PLL modules). You can configure these primitives to multiply your input clock to the speed you need (even non-integer multiples, ...


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PLL - you feed a low frequency clock in, you get a high frequency clock out. Even with PCIe Gen3 as an example this is how it's done - you use a 100MHz reference clock and use a PLL to increase it to 4GHz. So really any board which has I/O buffers capable of the frequency you require (150MHz) and a clock that is of a nice multiple of it (50MHz could be ...


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Sure, there is a stripped version of Linux named ucLinux that is optimized to run on micro controllers without memory management units. It will run on a soft core processor in an ecp3 such as the Lattice provided Mico32. It will not have anywhere near the performance of the dual core arm 9 in the Zync though.


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I would discourage you from trying to MUX the clocks like you show. You are already seeing that there are issues of trying to use gated clocks. My suggestions - Find a larger FPGA that is not so resource constrained for your design. There are a lot of good choices out there that are economical. Find a way to combine your clock domains into one so that ...


3

The problem I see is you have declared count_max as a 1 bit wide wire and then assign a 32bit constant to it - this will essentially get truncated to 1 bit. This will then mean you are doing additions and comparisons between 32 bit and 1 bit values on line 29, thus you get the issue of it saying truncated 32bit down to 1bit. Then by extension your ...


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Init your count reg to zero and specify the correct width for the count_next wire. Should work just fine once you make those changes.


2

Your count_next wire is implicitly declared. That means it is one bit wide therefor count[31:1] never get assigned and you never reach your max count which also needs to be declared as a 32bits rather than 1 bit as Tom pointed out. wire [31:0] count_next; localparam count_max = 32'd50000000; //you can use a wire but a parameter is a better description for ...


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Most likely the problem is the pins assignment, make sure they are assigned correctly. Posting the pin assignment here might help us find the problem. Anyway, Please test it without a clock and let us know. module gpio_test (CLOCK_50, GPIO_0, LEDG); input CLOCK_50; input [35:0] GPIO_0; output [7:0] LEDG; assign LEDG[0] = GPIO_0[0]; endmodule


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It's not the includes but the linker command line. If you have a dependency to libstdc++.so, then probably there is a -lstdc++ there. First, you need to check if that library is really necessary, so remove that option from the link command. If you're still able to link the program, the problem is solved. If not, then you really need it and have to put it ...


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This answer was given by a member of Xilinx staff to the same question on the Xilinx forums: In http://www.xilinx.com/support/documentation/user_guides/ug191.pdf, apge 18, the HSWAPEN pin if pulled to ground, will enable the weak pullups on all IO pins prior to configuration. After configuration, a pin may be set to pull up, or pull down, or to ...


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Width of buffer length n: This is exactly what you think, the largest transfer in byte the IP can perform with a single command. 18 bits may be enough, but it's likely you need 19 bits to represent 2^18, check the datasheet to make sure. Memory Map Data Width This is on the AXI side. You can put what you want (AXI will upsize/convert as needed), but in my ...


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It is likely the double-subscript is causing synthesis to infer distributed memory rather than memory blocks. I would combine the selecting bits from N_int and sine_counter_d1 into a single signal addr and use this as the index within SINE_TABLE(addr). A synthesis report (not even P&R) should show the improvement. I don't know VHDL, in verilog I'd do ...


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The USB port can be used to communicate with a design running on the FPGA, as well as for programming it. The Digilent Adept software can be used to interact with a design which implements this protocol; it's also possible to use the Digilent libraries to write your own software which uses this protocol. (I've also written a Perl module, Device::Digilent, if ...


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No, you don't have to worry about meta-stability, but you do need to make sure you constrain the clocks appropriately. Many modern FPGA Static Timing Analysis (STA) tools have commands to help constrain related clocks. You didn't mention which vendor you're using. For the sake of example, the process for Altera would be to specify a clock constraint on ...



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