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Check the pinout file, make sure your inputs and outputs are where you think they should be. Check your reset signal is connected, and the right polarity Check the input clock has a clean waveform at the right frequency. If it's still not working and you have internal clock multipliers/dividers (DCMs/PLLs), remove them and reduce your logic to something ...


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Although the lines look like matched pairs, they are not (by the look of it) matched between themsleves, so the delays on each of your databits is likely to be different. This will eat into the margin that your interface has (unless you are making a custom daughterboard, in which case you can compensate for the differences in delay on by making your traces ...


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@alex.forencich gave the right answer in the comments: the black color is registered outside of the visible area, and since for my test setup I had wired every analog input to maximum luminance (0.7V) the black was registered as the same signal which was sent in the active region => black. I measured the input impedance of the monitor (apparently this 100ohm ...


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Your approach is perfectly legal. The commas are not, however. Getting rid of them should solve your problem, unless there are other issues that are not clear from the code you posted. Note that there are side-effects to moving your code out of a clocked process, though - the value of blank will change 1 clock earlier, and your timing performance will be ...


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Xilinx has a very good applications note with supported C code you can use as base for your code. For your controller to work you must have 4 free GPIOs and connect them to the FPGA (and the other JTAG devices in the chain) as shown in this image: You might have to change it a bit to adapt it to your own environment but basically you need to go trough ...


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You may want to look at http://opencores.org. I can't speak to the quality of the designs there, but there are a large number available in both VHDL and Verilog. And given that it is open source you can look at the code.


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I am currently learning VHDL as well in school. For examples of well written simple code, I would definitely recommend this website: http://esd.cs.ucr.edu/labs/tutorial/.


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Depends on how you're connecting the FPGA to the host. If you're using the Xilinx JTAG cable, you're pretty much stuck with Impact. However, if you have a different interaface to the host, then it would not be too difficult to, say, write a loader interface that can accept a bit file and overwrite the configuration flash. Then all you need to do is reboot ...


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The GPMC should be the way to go. Basically, what you need to do is write an FPGA configuration that implements a port that acts like a GPMC compatible SRAM. However, instead of accessing an SRAM bank, the port can access various registers and memories inside the FPGA. If you use the correct pins for the data side of the port on the FPGA, then you can use ...


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The pixel clock rate needs to be adjusted to achieve Vsync rates and Hsync rates that are acceptable for your multisync monitor. Since 40Hz is not a common Vsync rate, try 30, 50 or 60 or higher. 640*480 * 40Hz = 12.3MHz so it seems pixels are pushed out at 1/2 of 25MHz clock rate The NTSC timing for V Sync , front porch (480~494) , Hsync, back ...


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You may check out Microsemi SmartFusion at; http://www.microsemi.com/products/fpga-soc/soc-fpga/smartfusion These have FPGA, uP, and programmable analog all on one chip. I used these in a school project and utilized all those parts sucessfully.


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Good single mode fiber has a loss of around 0.2 dB per kilometer. Generally, fiber optic transceivers of this sort have a link budget of around 10-15 dB, so you can put about 50 km of fiber between them and still be within the loss budget. You have to make sure that you're using the right transceivers, though. The long range stuff is all single mode, 1550 ...


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I think it should work. These connectors seem to have relatively low capacitance. If you are really worry about this - you may try to pass 125MHz or even faster signal from lab generator and see what is going on oscilloscope. These connectors were used for ATA hard disks, and they were working with pretty long ribbon wire with bus speed up to 33MHz, so ...


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If you are asking "can I create my own blocks for use the System Generator" then the answer is yes. It can be hard work, especially if you want to make it parameterisable in some way that means the actual logic included changes (rather than just the widths of certain data types for example). I ended up writing a Matlab script which generated the content of ...


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I would suggest a LFSR (Linear feedback shift register). This is a pseudo random number generator. See wikipedia for details about what a LFSR is. The only thing you have to store is the initialization vector that has to be different for each game. For instance: You have two LFSR of 32 bits. (The LSB of each LFSR register are the output of the LFSR ...


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Since the sequence of lights/tones is going to be different each time you play the game, you should be thinking in terms of storing that sequence in a memory (block RAM inside the FPGA), so that you can read it out repeatedly, both for prompting the user and for checking their response. You will also need a state machine, but this machine will be more about ...


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The advice to use the SPI clock to handle the SPI shift register is correct and saves you the bother of trying to oversample properly. One gotcha is in how you transfer that parallel register into another domain. DO NOT use a simple two stage FF synchronizer for each bit as you would for a solitary signal. If you use the FF synchronizers there is a real risk ...


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I think you have to synchronize the loading of the data slot with the SYNC signal from the AC97. Also you need to wait until the codec is ready before sending it data. The codec sends a ready signal in bit 15 of slot0.


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You do not need to have access to the VHDL or Verilog files for this project, what you need to do is to do a simple search for the error you get and find the information in the documentation provided by Altera. This parameter is something you have to provide to the procedure call. #include "sys/alt_flash.h" And you replace EXT_FLASH_NAME with the ...


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Some important links: Board datasheet: http://www.digilentinc.com/Data/Products/BASYS2/Basys2_rm.pdf Board schematic: http://www.digilentinc.com/Data/Products/BASYS2/Basys2_sch.pdf FPGA datasheet: http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf I assume that you are talking about the I/O pins on JA, JB, JC, or JD. If you are asking ...


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A picture here would be really good to understand your setup. First: Crosstalk is inductively and/or capacitively coupled. If your wires are just individual widely spaced wires in the air, you most likely do not have much of either. At that length you will have reflections if you don't manage that correctly. Reflections can easily cause double-clocking. ...


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Some things I'd try: Use the slowest drive you can get away with. At these clock rates, you should be able to use very slow drivers. You don't mention a specific FPGA type, but if it were Xilinx, I'd be using the "quiet" drivers, or "slow" if not available, and a 4mA drive current. See how it looks on the scope, increase the drive current if necessary. ...


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That tutorial is for a different board. In particular, it appears from the Trenz docs that their board is emulating a Digilent JTAG cable, not a Xilinx one. I'm not sure that is automatically recognized by the "Auto Detect" option shown in Fig38 of the tutorial you are using - or even whether it is supported by Vivado at all... I would suggest you try ...


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A divider is a series of subtractions and multiplexers that select the value for the next step. If it is done purely combinatorially, then the critical path through all of this logic is quite long (even with carry lookahead on the subtractors) and the clock cycle must be very slow. But the process is easy to pipeline, and the number of pipeline stages you ...


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You're unlikely to be able to synthesise connecting your tristate I2C line via a process like that. I would do this (I'm assuming you already have SDA_IN and SDA_OUT signals which you are currently using to create your SDA)... LED_or_SDA <= gpio_reg when register = '0' else '0' when register = '1' and I2C_SDA_OUT = '0' else 'Z'; ...


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Your second "FSM" code has many problems, primarily in the last process — process (current_s, input). Just a few examples to start with: This is an asynchronous process, so you must list all of the signals used inside of it in the sensitivity list. Failing to do this means that the simulation will not match the behavior of the actual hardware. Since ...



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