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2

Here are some thoughts on hardware coasts: 8 bit shift register on virtex-5, spartan-6 A slices contains 4 LUTs and 4 registers. You'll need 2 slices to store 8 bits. 8 bit shift register on virtex-6, 7-series A slice contains 4 LUTS and 8 registers. You can store the complete byte in one slice. 3 bit counter Small counters are implemented using LUTs and ...


1

Crudely you could floor plan the FPGA and divide it into regular sections, then use assignments to move specific instances of the hierarchy into each block. This is probably going to give you worse timing score than giving the planner total freedom though, since it enforces a minimum routing delay between blocks that free placement would eliminate by moving ...


0

I think you have to call a ROM function in the Bootloader to configure these registers. Appendix D in the Texas Instruments Using the OMAP-L132/L138 Bootloader application note has the ROM function that writes the EMIF registers.


11

Xilinx Spartan 3AN FPGA's have internal flash making them nonvolatile. Your question is actually multiple questions. 1) Are FPGA's volatile or non-volatile? Most are volatile, requiring the configuration bitstream to be read into the FPGA from an external nonvolatile storage device at every power on. There are some that are nonvolatile. Like the Xilinx S3AN ...


7

It is possible to find FPGAs with an integrated non-volatile program memory. For example, Microsemi (formerly Actel) specializes in this type of device. Other vendors offer the option to mask-program an FPGA. For example, Xilinx calls their mask-programmed devices "EasyPath" FPGAs. This does require an NRE payment, as far as I know, so it isn't appropriate ...


6

I can at least speak for altera, I assume Xilinx will have something similar. They have the option of encrypting the file you put into external flash or EEPROM. Then you load the decryption key into the altera part, using its non volatile or battery backed key storage. Since you can't read the key out it protects your ip. They were losing design wins to ...


0

The only way you could accomplish this is by purchasing a separate Flash module (if you dont already have one on the PGA) and loading your code into ram, however this is not recommended for all the hassle, just purchase something like a CPLD if you plan on reprogramming at a later point or a ASIC if you have no intentions of reprogramming it again.


1

I assume that ctr_reg is of type (un)signed because it's a counter. VHDL expect normal indices to be of type integer (natural, positive are subtypes of integer). See the definition for std_logic_vector: type STD_LOGIC_VECTOR is array (NATURAL range <>) of STD_LOGIC; So you must convert your counter from (un)signed to integer: if ...


2

50000000/2 requires 25 bits, not 15 (log base 2 of 25000000 is 24.575, the ceil of that is 25). In the second module, counter gets set to 30783 instead of 25000000 so the 'BPM' is ~97456 instead of 120.


0

Firstly I'm assuming the signal clk is a nice clean clock signal driven from outside the FPGA, maybe by crystal oscillator, LVDS clock source or similar, preferably on a dedicated clock pin? Your code creates a roll-over counter stored in count_time that overflows to zero after 22-bits, where cycle with all-1's sets signal check high for one cycle. So far ...


0

Following this page https://embeddedmicro.com/tutorials/mojo/metastability-and-debouncing I added buffering to the control signals sent by the host. They weren't in my original question, since I was having strange results even with just usb_write. always @(posedge clk) begin astb_buf <= usb_astb; dstb_buf <= usb_dstb; end Buffering just ...


0

FPGA implement a hardware logic circuits or functional block, in theory it can implement anything you want. And those blocks are running concurrently, unlikely a conventional MCU running programming line by line. Therefore the performance of FPGA much better than MCU, but it requires to know HDL or VHDL language which different to programming language in ...


2

The reason Dave asked you what you want to do is because what path you pick will depend on your goal. What will the interface be to your camera? HDMI, Composite, YUV, directly to an image sensor etc? What frame rate and resolution do you want to work with? Do you want to process every frame? What are you going to do with the video data something simple? ...


4

Normally, FIFOs are self controlled to prevent overflows and underflows. This is done by implementing a forward and backward flow control. Forward flow control means that data words are marked valid in the FIFO so that the read side can distinguish valid from invalid words. Backward flow control is achieved by exporting fill state of a FIFO to the write ...


0

I think it's not a good solution to build a chain of 32 FPGAs. You should also consider the time for programming/reprogramming 32 FPGAs. I don't know the coast, but maybe you can add several USB to JTAG converts and a USB-Hub to your board. Other vendors employ a complete auxiliary FPGA for this job. Edit 1 Xilinx development boards are equipped with FTDI ...


2

You should read through the relevant Xilinx documentation; for Spartan-6's that would be UG393 (Spartan-6 FPGA PCB design & pin planning guide), UG380 (Spartan-6 Configuration), and possibly others. No doubt Xilinx have similar documentation for their other product lines. With regard to your particular problem, there is some fairly specific advice in ...


3

You have given c a default value of 1, but then at time 0 assign it to be equal to b (blocking). So the simulation copies the value of b to c before sequentially moving on to perform a <= b. What you have written is essentially: module block; reg a; reg b = 1'b0; reg c; initial begin c = b; a <= b; end endmodule


0

Is there a simulation model of the ICAP? If so, debug it in simulation first. If not, hang a chipscope off the ICAP signals so you can check they are doing the right thing. And hang a scope/logic analyser off the external flash device's pins so you can see what the FPGA is doing and whether it is attempting to find and load the code you expect. Write ...


2

Signal Tap may well be showing you what the FPGA is seeing the reset signal as. If it is bouncing around internally, then that may indicate you have problems on that signal (maybe it's too close to the threshold voltage) or maybe the supplies are noisy.


0

There's nothing (technical) to stop you routing the output of a LUT back to the input to create storage. But it's not a good idea as in most (all?) current FPGA families there is at least one flip-flop very closely coupled with each LUT. In some families some of those FFs can be configured as latches instead.


0

compile UNISIM libraries by runnin compxlib and following wizard. then in your modelsim, library pane add new library. after that add library from existing library and point to folder which contains compiled version of unisim, e.g. it is C:\Xilinx\10.1\ISE\vhdl\mti_se\unisim for me After that you can have fun with UNISIM :)


3

Yes, FPGA can outperform modern CPU (like Intel i7) in some specyfic task, but there are easier and cheaper methods to improve neural network performance. By cheaper - I mean total effort, not FPGA IC cost, but also very fast memory for FPGA (you would need it for neural network) and whole development process. Use SSE - I've seen pretty simple neural ...


5

There are roughly 3 levels of specialization of computing equipment: CPU (like in your laptop) is the most generic of them all. It can do everything, but this versatility comes at a price of slow speed and high power consumption. CPU is programmed on the go, the instructions come from RAM. Programs for CPU are quick, cheap and easy to write and very easy to ...


18

A colleague of mine benchmarked this and came to the conclusion that FPGAs would outperform a PC once you had more than about 100 independent, integer tasks that would fit in the FPGA. For floating point tasks GPGPU beat FPGA throughout. For narrow multithreading or SIMD operation then CPUs are extremely optimised and run at a higher clock speed than FPGAs ...


11

It depends a lot on the algorithm, but the principle can be explained quite simply. Suppose that your algorithm has to sum a lot of 8-bit numbers. Your CPU will still need to fetch each instruction, get the operands from the RAM or the cache memory, execute the sum, store the result in cache, and go on with the next operation. The pipeline helps, but you ...


15

An FPGA works completely differently from a processor. For a processor you write software that tells the hardware what to do. On an FPGA you describe "what the hardware should look like" internally. It is as if you are making a chip specially made for your algorithm. This speeds up a lot of things and can bring down the power consumption. But it has its ...


0

All FPGAs contain LUTs as well as configurable flip-flops/latches. Even with just LUTs, the routing network has enough capability to route a LUT output back to an input to get feedback within one LUT or between several LUTs. They also usually contain block RAM that can be configured with multiple ports of various widths or be used as a FIFO. The LUTs can ...


6

You've got the wrong device. In order to program the SPI Flash using the indirect JTAG method, you need to right click on the FPGA and select Add BPI/SPI Flash. It'll ask for the device type and your programming files. The type should be SPI Flash M25P16 according to this document, page 106. Then highlight the SPI Flash you just added and select the ...


3

I assume your question is, why doesn't Signaltap agree with your oscilloscope. Quartus Signaltap isn't a simulator, it's an embedded logic analyzer (synthesized into the FPGA configuration, alongside the design under test). It's basically a state machine that captures internal signals and communicates with the Quartus software to display. So unlike ...


1

As the current answers reflect, no, you can't do this directly: you need to implement an ADC that can convert the analog level from the sensor to a digital value that can be read by the digital input pins of the Altera. However, if turning an LED on if the sensor has a value higher than some threshold is really the only thing you need to do, there's a much ...


0

If your Altera has LVDS inputs, you've got a fairly good comparator. It's possible to make a crude Sigma-Delta (or PWM) DAC and thus get a crude ADC. It's not going to be a very good ADC- noisy and the default reference is the crummy digital supply rails and range will be limited, but if all you need is a few bits it might work for you.


1

No you can't sample analog values with digital inputs. You can either connect an ADC, and to do that you will have to refer to the datasheet of your chosen ADC, or use a comparator to compare the incoming voltage with a reference voltage, and output a digital HIGH / LOW signal which a digital pin can read.


0

No, the GPIO pins are digital. There are no onboard ADCs in the Cyclone IV series.


2

No, you've misunderstood how a PLL demodulator works. The NCO (or VCO in an analog system) must track the instantaneous frequency of the incoming signal, not just its average value. If it does this accurately, then then the control value is an accurate replica of the original modulating signal. If the oscillator only tracks the average frequency, then you ...


1

If the input signal drifts off in frequency, without having a mechanism that tracks the input centre frequency, eventually performance will degrade and demodulation will fail. It is imperative that the phase comparator has two inputs whose average frequency is the same.


0

A Virtex-5 can drive up to 24 mA per I/O pin depending on the selected I/O standard and I/O bank voltage (see DS202, page 7 in Virtex-5 FPGA Data Sheet - DC and Switching Characteristics). The drive strength can be set in an ucf file. Example ucf line: NET "ML505_GPIO_LED[0]" ....... IOSTANDARD = LVCMOS33 DRIVE = 12 SLEW = SLOW; See Xilinx Constraints ...


2

If you haven't connected Start or CLK to anything then your ADC0808 is just going to sit there doing nothing. CLK must be connected to a continuously running clock signal at a frequency somewhere between 10kHz and about 1MHz, and Start needs to get a pulse to tell the ADC to start a conversion. 8 clock cycles after your Start pulse, EOC ...


1

The short answer is yes, although it's really not a good fit for an FPGA project and the FPGA is mostly useless. Fundamentally a Theremin is a capacitative sensor device like a smartphone's touchscreen or proximity sensor, but tuned to very high sensitivity. See this Arduino theremin, which would be a good basis to adapt from. There may be capsense ...


3

Wow, using a Virtex-5 for this is massive overkill - on the scale of using a nuke to open a peanut. I'm not sure what voltage the I/O on the Genesys board runs at; as long as it's 3.3V (and it probably is) you should be able to connect a LED of any colour via a series resistor (higher or lower value for lower or higher brightness, start with 1kohm) to ...


5

always @(*) begin This means whenever any variable that appears on a right-hand side in the block changes, run the block. equals = equals + 1; This changes the variable equals. So whenever equals changes, you increment equals. Which means equals changes, which means you increment it again, and so on. So basically, equals just keeps incrementing as ...


2

As an answer to your question "What do you do next", here's some random things you should consider and measure: Does it get programmed OK? Do you use some JTAG cable to connect to it? Does it identify itself correctly with the JTAG cable and programming software? Or do you use some EEPROM/FLASH to load the configuration at startup? Do you program the ...


0

See this answer describing the VHDL Simulation Cycle In your case it means you can't evaluate an expression comprised of a signal assigned in the current simulation cycle. It's scheduled to take effect at some point in the simulation time future. This includes an assignment without a delay. Your code sample has defined four registers. ledica, tmp, sum ...


1

The <= assignment in the process is done in a special way. First all of the right side statements are evaluated, and then all of the left side signals are assigned. In your case, first the std_logic(tmp(n)); parts are evaluated with the 'old' value of tmp, and only then tmp and sum values are assigned.


5

You can get automotive-qualified FPGAs. There should be no issues so long as you get one that will work over the temperature range you need and you design the support circuitry correctly. An ASIP may be faster if you build it in silicon, but if the FPGA implementation is fast enough, it's not like it's going to suddenly get slower when you put it in the ...


0

They cannot provide that information. The only information they have is 'best case' and 'worst case'. It is impossible to know how any individual chip will perform unless you go measure the specific chip you're interested in. The timing performance of the logic elements is only guaranteed to be somewhere within the 'best case' and 'worst case' over the ...


0

The Atlys board has a USB UART chip on it. This is probably the simplest interface to use. There is an open source UART IP core with an example design for the ATLYS board here: https://github.com/alexforencich/verilog-uart . If this isn't fast enough, then you could look in to bringing up the Ethernet port and using that, but that is a significantly more ...


0

I would choose the Serial method as the easiest one to implement. I am talking about Asynchronous Serial protocol, which is logically compatible with computer's serial port (COM1, COM2, etc). Electrically it should be converted to the levels computer uses. The standard is called RS-232. You should look up for UART(Universal Asynchronous Receiver/Transmitter) ...



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