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Most synthesis tools don't support read/write support. Some of them report the usage of such functions as an error, others ignore such statement or even don't implement Std.TextIO. Xilinx ISE supports read/write in VHDL (I have not tested Verilog). Xilinx Vivado has some issues with file i/o. Contrary common consensus, there a good usecases for file i/o at ...


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SystemVerilog is a hardware description and verification language that has hooks into the host operating system that runs the simulation. None of these hooks are available to you in the actual hardware. However, if you are running your FPGA on a development board, then there may be hooks that the FPGA vendor provided to dump you memories to a file.


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No, obviously not - how could it? None of the $ extensions do.


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Your design has a signal called clk, but it isn't used as clock. You should add if(rising_edge(clk)) statements in the process body. Once you modify your desing, Quartus will detect that clk is used as clock and you will be able to proceed with your Fmax analysis.


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The problem is that you actually have no clock, or to be more precise, no clock is used. Check your process: process(clk) begin result <= a + b; end process; This process doesn't use the clock. You probably wanted to do this: process(clk) begin if rising_edge(clk) then result <= a + b; end if; end process; This code uses the ...


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Xilinx's Spartan-3E only support RAMB16, RAMB16WE being a primitive of a later architecture (Spartan-3A, and maybe others). You most likely generated your IP with the wrong project options. Make sure you generate the IP for a Spartan-3E, not a Spartan-3A or any other architecture.


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If you have already finished your design, use the Xilinx Power Estimator. But one of the reasons to use FPGAs is the ability to reconfigure them as needed, so you may want higher power later, then I can't see the point in finding precise current values. And eventually both if you require 1.63 or 1.87 A you'll end up with a 2 A regulator, don't you? ...


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If you are targetting an FPGA then signal initialisation can make sense and the tools do (in my experience) support it - and have for a number of years now. You usually want to use a reset clause though for most things as debugging can get very tedious if you have to reconfigure every time to stimulate a problem, rather than just wiggle the reset pin to get ...


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Your sensors seem to provide a timed pulse representing the measured value. In case of a micro-controller, this signal would trigger an interrupt, and the interrupt handler would use a timer to measure the pulse length and store it to a variable. In case of an FPGA the equivalent of such variable would be a counter with enable signal connected to the output ...


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Your assumption that you have metastability problem seems correct. I did only a survey of the spi slave code, and here what I found: The spi clock is used as is, i.e. it requires a clock buffer. The data you read from the spi core is not resynchronized to the 100MHz clock, it is on the spi clk domain. The data valid signal is resynchronized to the 100Mhz ...


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Metastability? Highly unlikely. Unsynchronised inputs? Very probable and they can cause the symptoms you describe. So clock each SPI input from your fast clock, and route the clocked versions to the SPI core. (Unless you're already certain that it reclocks them already).


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Depending on who else drives the signal, an initialization value could be treated arbitrarily by the tool (hopefully just ignored if it doesn't make sense). Besides, the concept of initialization makes in general no sense for a signal. A signal is a wire and a wire is driven (e.g. by logic or a flip flop), not initialized. Therefore it is usually more ...


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It's better to use reset. When simulating, everything is initialised to 'X'; when synthesised, it will randomly be 1 or 0. Initial values don't work in synthesis, so you need a reset.


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You need several HardIPs for: PCIe bridges PCIe Switches custom designs that use PCIe as a board-to-board communication ... Common cores support up to 8 lanes and Gen2. More lanes are possible but need a Soft-IPCore. Also Gen3 is mostly provided as a Soft-IPCore.


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There is two main way to use a PCI bus between a FPGA and a processor. Note that I say PCI in the answer because there is nothing in what I tell special about PCIe; it encloses PCI. The first one is using PCI BARs (Base Address Register). These are address spaces declared by the PCIe device (for example, a device could declare having a BAR0 of 4KB) that are ...


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** sorry I thought I was posting a comment ** @user3624 - as far as I can tell using the truth table or the above logic provided the counter is incremented/decremented only if count enable is high are the same. Of the 16 (not including X values) states, count_enable = (A xor prevA) xor (B xor prevB) disables 8 states. Of the remaining 8 states (A xor ...


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I have recently made a SD/MMC interface (for a FPGA). IMHO, the standard do not make much sense. Anyway : My init sequence starts with CMD0 / CMD8 / ACMD41 (repeated) / CMD2 / CMD3... You may need to send ACMD41 several times. In normal mode, the card changes outputs on falling edges, in high speed mode (up to 50MHZ), the card changes outputs on rising ...


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Could the post map simulation be a proof of the rightness of my vhdl code ? No. Especially if you are just "looking at the waveforms." If you have an independently created testbench which will tell you pass and fail information, then you can use that in simulation with either your RTL or post-map to provide evidence of correctness (but only for the ...


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What you are synthesizing are not memory blocks but rather register with synchronous reset - which should act exactly as you described so that is not the problem you are seeing. So it is not completely clear to me where the problem is. I suggest you add some details (e.g. version of the tools you are using to synthesize this, what other registers are in the ...


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I'm not sure what experience you have in embedded software design (mostly sequential instructions), but a true division takes FOREVER by comparison with just about anything else, even if such an instruction exists. So we have all kinds of tricks to accomplish the high-level goal without actually dividing. Two of them are: Bit-shifting: This is so cheap ...


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You are correct with the guessing the for loop. The for-loop logic is huge when it after it static unrolls. With your current code, you cannot handle the worst case scenario where n=1023. To cover this with your current code you'd need a for loop with 1024 iterations. Instead of a up counter, you can use a down counter and only examine a slice of the ...


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Your code has two ways to change sig_enable if falling_edge(tri_output) and sig_enable = '1' then if i = 8 then i := 0; sig_enable <= '0'; ... if rising_edge(SEND) then sig_enable <= '1'; end if; So you are asking for sig_enable to change on either a falling edge of tri_output or a rising edge of SEND. There is no ...


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The answers above, while correct, miss the point about why FPGAs (and custom ASICs) are especially good for bitcoin calculations. The real advantage is that a large proportion of the SHA-256 calculations are logical operations (for example, bit shifts) which can be done in wiring. When done this way, they require 0 clock cycles. Another important advantage ...


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Maybe it's not a direct answer to your question, but i want to draw your attention on the following possible workarounds: skew rate is controllable both at RGMII PHY and FPGA IC Typically RGMII PHY implements a de-skewing mechanism (e.g. KSZ9021 can absorb skews up to 1.8 ns, very near to that what you need), therefore (if your phy has it, of cause) you ...


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I found out what the problem was and why I wasn't able to pipeline this. Vivado HLS found a way to treat sum += ias a constant multiplication and so the latency remained constant. Therefore, if the latency is constant, the pipleine didn't make sense.


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You might be looking for an CPLD or a PAL which are programmable logic devices of less complexity than a FPGA and a quick search on digikey for CPLD shows that they are available in easy to use DIP packages from 20 pin to 44 pin


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What you describe would be to output 'Z' on the else branch, which translate to High-Impedance. If one driver outputs XYZ and all other drivers connected to it output 'Z', the result is XYZ. The 'Z' translate to a tri-state buffer inside the FPGA. However, tri-state buffers don't exist anymore on modern FPGAs for anything else than output drivers (i.e. on a ...


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The naming scheme on the primitives in your image suggests that this design is intended to be implemented in an FPGA. If this is the case, gating a clock network is not recommended. Clocked logic elements in an FPGA can usually only be clocked by dedicated clock networks. These networks are only available in very limited numbers (i.e, perhaps a dozen on the ...


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Here's how I understand this should work. I knocked this up and tested in Xilinx ISim. This synchronises the valid flag across the domains, holding it in the A domain until it is seen to arrive in the B domain, and using edge detection in the B domain to regenerate a single cycle strobe. The data bus is registered from A into B domain when we know it has ...


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You do not drive LEDR output at all. You need an assignment like: assign LEDR = M; You probably wanted to achieve that by assigning LEDR[3:0] to M (i.e. assign M = LEDR[3:0]), but this two assignments are not equivalent in Verilog.


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If some branches in the process are not explicitly assigning some net, it is implicitly assigned with the previous value with an inferred latch. So there is no situation the process won't drive this signal (unless explicitly assigning hi-Z to it..). Update: The possible solution, as states, is to mutually disable the driven net (put it in tri-state) in two ...


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You must supply VccInt for all pins named "VccInt". This is internal operating voltage and is not available on the outputs. The same applies to all Vccout I/O banks as well. All Vccout pins must be provided with voltages. Each I/O pin is designated to one of the device's banks, and each bank can have a different voltage, based on your needs (but, of course, ...


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I've had some success using a similar technique to what you have proposed above, which is to essentially create multiple registered duplicates of the high-fanout nets. You can use one per destination as you have, or what I have done in some cases is to duplicate them so that there is one registered duplicate for every n destinations. In theory, you should ...


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There's no need for any such book. The reason is that "all of the different Logic devices that can be implemented with basic logic gates" is just all the possible truth tables that can be constructed with any particular number of inputs. So a book of all the possible gates would be the equivalent of a list of all the numbers between 0 and 2n-1. In FPGAs, ...


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Licensing they usually try for a large licensing fee plus royalties, then you negotiate from there. Sometimes they'll give you a break on upfront cost if you agree to larger per chip royalties. Upfront is usually always required since they need to provide you with support to get going. Keep in mind just an h.264 encoder may not be all you need in your ...



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