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1

As the current answers reflect, no, you can't do this directly: you need to implement an ADC that can convert the analog level from the sensor to a digital value that can be read by the digital input pins of the Altera. However, if turning an LED on if the sensor has a value higher than some threshold is really the only thing you need to do, there's a much ...


0

If your Altera has LVDS inputs, you've got a fairly good comparator. It's possible to make a crude Sigma-Delta (or PWM) DAC and thus get a crude ADC. It's not going to be a very good ADC- noisy and the default reference is the crummy digital supply rails and range will be limited, but if all you need is a few bits it might work for you.


1

No you can't sample analog values with digital inputs. You can either connect an ADC, and to do that you will have to refer to the datasheet of your chosen ADC, or use a comparator to compare the incoming voltage with a reference voltage, and output a digital HIGH / LOW signal which a digital pin can read.


0

No, the GPIO pins are digital. There are no onboard ADCs in the Cyclone IV series.


2

No, you've misunderstood how a PLL demodulator works. The NCO (or VCO in an analog system) must track the instantaneous frequency of the incoming signal, not just its average value. If it does this accurately, then then the control value is an accurate replica of the original modulating signal. If the oscillator only tracks the average frequency, then you ...


1

If the input signal drifts off in frequency, without having a mechanism that tracks the input centre frequency, eventually performance will degrade and demodulation will fail. It is imperative that the phase comparator has two inputs whose average frequency is the same.


0

A Virtex-5 can drive up to 24 mA per I/O pin depending on the selected I/O standard and I/O bank voltage (see DS202, page 7 in Virtex-5 FPGA Data Sheet - DC and Switching Characteristics). The drive strength can be set in an ucf file. Example ucf line: NET "ML505_GPIO_LED[0]" ....... IOSTANDARD = LVCMOS33 DRIVE = 12 SLEW = SLOW; See Xilinx Constraints ...


1

If you haven't connected Start or CLK to anything then your ADC0808 is just going to sit there doing nothing. CLK must be connected to a continuously running clock signal at a frequency somewhere between 10kHz and about 1MHz, and Start needs to get a pulse to tell the ADC to start a conversion. 8 clock cycles after your Start pulse, EOC ...


1

The short answer is yes, although it's really not a good fit for an FPGA project and the FPGA is mostly useless. Fundamentally a Theremin is a capacitative sensor device like a smartphone's touchscreen or proximity sensor, but tuned to very high sensitivity. See this Arduino theremin, which would be a good basis to adapt from. There may be capsense ...


3

Wow, using a Virtex-5 for this is massive overkill - on the scale of using a nuke to open a peanut. I'm not sure what voltage the I/O on the Genesys board runs at; as long as it's 3.3V (and it probably is) you should be able to connect a LED of any colour via a series resistor (higher or lower value for lower or higher brightness, start with 1kohm) to ...


0

Goolge VHDL SPI driver or something similar. There are tonnes of code samples that are pretty easy to edit and incorporate (usually a bit more complicated than you need - extra signals and what not, but thats not an issue). With SPI you'll definitely want to analyse your waveforms to make sure its working, either with a logic analyser or at very least ...


5

always @(*) begin This means whenever any variable that appears on a right-hand side in the block changes, run the block. equals = equals + 1; This changes the variable equals. So whenever equals changes, you increment equals. Which means equals changes, which means you increment it again, and so on. So basically, equals just keeps incrementing as ...


2

As an answer to your question "What do you do next", here's some random things you should consider and measure: Does it get programmed OK? Do you use some JTAG cable to connect to it? Does it identify itself correctly with the JTAG cable and programming software? Or do you use some EEPROM/FLASH to load the configuration at startup? Do you program the ...


0

See this answer describing the VHDL Simulation Cycle In your case it means you can't evaluate an expression comprised of a signal assigned in the current simulation cycle. It's scheduled to take effect at some point in the simulation time future. This includes an assignment without a delay. Your code sample has defined four registers. ledica, tmp, sum ...


1

The <= assignment in the process is done in a special way. First all of the right side statements are evaluated, and then all of the left side signals are assigned. In your case, first the std_logic(tmp(n)); parts are evaluated with the 'old' value of tmp, and only then tmp and sum values are assigned.


5

You can get automotive-qualified FPGAs. There should be no issues so long as you get one that will work over the temperature range you need and you design the support circuitry correctly. An ASIP may be faster if you build it in silicon, but if the FPGA implementation is fast enough, it's not like it's going to suddenly get slower when you put it in the ...


0

They cannot provide that information. The only information they have is 'best case' and 'worst case'. It is impossible to know how any individual chip will perform unless you go measure the specific chip you're interested in. The timing performance of the logic elements is only guaranteed to be somewhere within the 'best case' and 'worst case' over the ...


0

The Atlys board has a USB UART chip on it. This is probably the simplest interface to use. There is an open source UART IP core with an example design for the ATLYS board here: https://github.com/alexforencich/verilog-uart . If this isn't fast enough, then you could look in to bringing up the Ethernet port and using that, but that is a significantly more ...


0

I would choose the Serial method as the easiest one to implement. I am talking about Asynchronous Serial protocol, which is logically compatible with computer's serial port (COM1, COM2, etc). Electrically it should be converted to the levels computer uses. The standard is called RS-232. You should look up for UART(Universal Asynchronous Receiver/Transmitter) ...


0

Sorry if this is too obvious, but do you have the scope probes set to 10:1 and 20MHz band limit 'off' on the 'scope?


0

If your circuit is made of simple logic, it will be difficult to really constraint the design to fit in the FPGA's matrix. You should probably let the FPGA vendor's tools do the work. It you had to make an ASIC, you could really design a cell then copy/paste it over the surface, with FPGAs, you have to deal with the fact that they are not as regular as they ...


0

During the boot sequence the I/O-pins are usualy pulled up with high impedance so they can not damage other parts. For the registers and the memory of the FPGA you can define the initialization with the constraints editor. If you build the PCB yourself it's your job (with the help of the data sheets) to provide the appropriate reset signals (perhaps ...


2

I would recommend using an asynchronous FIFO for the synchronization. Write a module that runs at 9 MHz and draws data from the FIFO to output to the display. You may need to send a few sideband signals through the FIFO as well as the data so the interface code knows where the frame and the rows start. Then write another piece of code that will read the ...


3

You'd have to set up synchronization registers across the clock boundaries. And as the clocks are out of phase with each others, there's always the possibility of metastability, but I suppose the FPGAs are not very susceptible to metastability. I would suggest to run your CPU at some "easy" multiple of 9 MHz, perhaps 9 x 4 = 36 MHz or 9 x 8 = 72 Mhz and ...


0

first of all you want to run linux on a core. How about running it on an ARM like some other suggestions in this thread. MCU are good at running OS but it gets kind of wasteful of FPGA resource building an MCU. MCUs can fit into a much smaller silicon area when custom designed for that and can thus be produced more cheaply. Then there are other ...


0

As an alternative, you could use some high-level synthesis techniques such as Xilinx's Vivado HLS and Altera's OpenCL solution. Maybe this will alleviate your curve to learn hardware description languages, considering your software background.


0

VHDL also provides features to describe different values for initial start-up and reset. signal myValue : std_logic := '1'; -- initial value after programming ... process(clock) begin if rising_edge(clock) then if (reset = '1') then myValue <= '0'; -- reset value else myValue <= not myValue; end if; end if; end process; ...


1

You are performing a division and a multiplication operation on a signal. At least the multiplication is mapped to a hardware multiplication circuit on your FPGA. Your module provides the generic parameter N, which could also be called PWM_RESOLUTION. Beside this, I miss two additional parameters or constants in your module: The clock frequency of the ...


2

Yes, this is possible. When the configuration is loaded onto the FPGA, all of the registers are initialized to initial values. In verilog, these can be specified when the reg is defined or in an initial block. All you need to do is have a register, say 'initialized', with initial value zero. First clock edge where it is clear, you run your init routine ...


1

In this case, it might be a good idea to preprocess the image into an intermediate format with a different programming language that actually has image manipulation libraries, such as Python with PIL. You really don't want to have to deal with parsing the MIF format in Verilog. Once you've read in the image, then you can write out a 160x120 array in a ...


0

That's a doozy of a question. What's the research for? I know the approach I'm going to suggest won't resolve the problem with the tools complaining, but it might minimize the skew in an actual implementation. I'm not familiar with Altera FPGA's, I've worked mostly with Xilinx S3 and S6 parts; I know this approach can be made to work in an S3, but not an ...


0

No, not as a flip-flop. It is a D latch. The difference occurs when clock is high. A flip-flop will register the input, d, at the clock edge. The d latch will allow the registered value to change when clock is high. A D-Latch Truth Table would look like: Clk D | Q(t+1) ----------------- 0 x | Q(t) 1 0 | 0 1 1 | 1 x = don't care ...


0

If you multiply two eight-bit numbers, the partial products will in general be single bits. However, assuming a row-based structure there will be eight rows of eight bits each, where each row is either 00000000 or the other input. With modified Booth encoding there will be four rows. However, as each row now will be -2, -1, 0, 1, or 2 times the other input, ...


2

I'm not familiar with that bit of kit (though it looks really tasty and I wish I had one), but I'd suggest breaking it down into steps and confirm each one. First just try and receive a signal without forwarding it - make sure that side of it is working fine and your receiver configuration / code is correct. When you have confirmed reception, create a ...


3

It might work, but it's hard to say what the synthesizer will do with that. It is a much better idea to use an always block when you want to do use a clock.


10

Build an 18 bit counter. Every time it hits 250,000, toggle a flip-flop. 50 MHz / 250,000 = 200 Hz. Toggling a pin at 200 Hz gives you 100 Hz with a 50 percent duty cycle. If you just need a pulse with a 100 Hz repetition frequency, then build a 19 bit counter and generate a pulse when it hits 500,000. Fortunately 250,000 and 500,000 are both even ...


0

The NRF8001 has an SPI interface which people routinely use with ATmega32U8 based Arduino boards running open source firmware. Therefore, you certainly don't need the dongle or any particular host operating system to ultimately utilize it. Talking SPI is quite natural for FPGA designs, with or without a soft core processor inside. It is possible though, ...


1

When repetitive operations like this are demanded, often a For loop (within a process) is the answer. People shy away from loops, and I'm not sure why : possibly some antique synthesis tools had trouble with them, but now they do quite a good job of synthesising loops, functions, procedures, etc - PROVIDED these are all written with a view to hardware ...


3

You are both setting and reading the signals f and done in the same process; this creates the feedback ("combinatorial loop") that the tools are complaining about. In order to eliminate that kind of feedback, you need to explicitly list every combination of req: architecture Behavioral2 of prEnc is begin process (req) begin if req(7) = '1' then ...


6

Yes, you can use a delay and ignore the response, but if it is a response to sending the actual SMS itself, then that could take some time. You would have to send several SMS messages by hand to judge how long it might take the OK to come back, and then add on some margin to the longest delay seen. It would be much better to actually look for the OK ...


3

If your VHDL description exhibits combinatorial dependency cycles, then the synthesizers will generate the exact same circuit. If you want it, you get it. However, warnings will be emitted, because it is difficult (but not impossible) to tell whether the circuit will oscillate or not (that is : will behave as pure combinatorial circuit circuits or sequential ...


1

RSA is not suitable for directly encrypting large amounts of data. Not only is it way too slow, but it is also weaker than some other algorithms against an opponent who has a large number of known plaintext/ciphertext pairs. To guard against this, data which is encrypted using RSA is usually padded with random bits beforehand. As a consequence, RSA ...


2

RSA will not be easy to implement and may require a very large FPGA. RSA is far better suited to running on a general purpose CPU than an FPGA. I have seen some implementations of RSA on an FPGA that use a softcore to run the algorithm and the FPGA to accelerate some of the math, but the complete algorithm is not implemented in Verilog. And generally when ...


0

This is pretty challenging and unless you use an open source or readily available rsa implementation, 2 weeks is a stretch. If you use some ready library for implementation it is possible to wrap up the the library to suit your needs. This assumes you have a proven devkit you can use.


1

ISE sorts the hierarchy out for you. Once you've instantiated a lower block, it will appear under the top block, not at the same level of hierarchy.


1

counter2 is reset to state 11. When the trig rising edge occurs, it starts counting down. Your code shows no way to ensure that the trig edge is syncronized with your clk signal. In your simulation, trig goes high very shortly before a clk rising edge. So on that edge, counter2 starts counting down --- going to the 10 state. But in between the trig edge ...



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