New answers tagged

1

Yes the pin is called "ADC_xx" but as Richard pointed out it doesn't appear anywhere in the documentation. Note though in the "connects to" column there it says they connect to the FDDR and GPIO pins. My guess is that the naming convention is standard across their breadboard areas and it's part of some scheme to help developers keep consistent across their ...


1

The SmartFusion device supports analogue, the SmartFusion2 does not Link From that information, it appears you cannot do this with the kit you have. This evaluation kit does support ADCs.


1

I see NOTHING in the block diagram that suggests that it has ANY kind of analog inputs or analog-to-digital conversion. Just because the name of some of the pins use the letters "ADC" does NOT imply it is an analog-digital converter. If you see something there that we missed, please identify it explicitly.


0

You'll either need to convert it to hdl or read it into a block RAM with readmem or similar so that it gets included in the bitstream or you'll need to add some additional nonvolatile memory on your board, store it there, and read it into the FPGA.


0

It looks like the max clock speed is 1.33 GHz for the ARM. But I'm not sure you can can clock the PL that fast. I imagine you can take advantage of the parallelism in the FPGA to do many MAC operations simultaneously. If the FPGA can access main memory though DMA, it can fill up the memory then send a flag to the CPU to offload the data when it's done. ...


0

regarding functionality MB vs ARM Cortex-M3, basically the Cortex-M3 contains a ARMv7-M CPU and that means it's based on ARMv6-M. Check out some screenshots showing off mainstream features. MB will definitely be better integrated on Xilinx FPGA fabric and its 'in the field' since many years. For more info on MB, search UG081 - MicroBlaze Processor Reference ...


0

Simulation is what you want - read up on how to make a simple testbench for your circuit (apply clock and reset). Tie low any inputs which can be ignored for the simple cases, work up to having a matching machine in the testbench side of the simulation to at least exersise (if not check) your design. Starting with trying to debug an FPGA is a waste of time, ...


0

You can't easily "single step" an FPGA design, unless that capability is part of the design itself. But Altera offers an embedded logic analyzer called SignalTap that you can use to probe signals in real time. But it's usually better to do the bulk of your debugging in the simulator; the visibility into what's going on and the ability to change things on ...


3

It's changed over time. It used to look like the bottom picture about 8 versions of Quartus ago. Now it looks like the top picture. However you can still view the logic, it's just not in the same place. The reason so far as I can tell is that FPGAs are getting more and more complex, and at some stage it becomes simpler to show the entire logic cell (which ...


1

Can you be more specific about what you want to do with these arrays? Are you outputting them to the terminal? What is it that you are trying to accomplish with your design? Is it something that could be done with a processor only or are you using the FPGA for a specific hardware algorithm? Have you read the Xilinx documentation or seen the Vivado ...


0

You might also want to check out: EDA Playground


1

This might save toggle power, but only in this module, and only before this logic is used once. You've spent a flop doing that, and added some gates. I don't think this is useful (but I don't have visibility of your whole system). You would be better off clamping the in1, in2 at source, and more frequently. Even better is gating the clock to a clop that ...


0

If you've got a fast pulse, then maybe just send it through a diode to an RC that will fix the decay time. (and some potentiometer after to set the height.) simulate this circuit – Schematic created using CircuitLab


0

A very simple answer might solve the problem. When you are performing synthesis, you are using a sub-set of the full expressive capabilities of the verilog language. In synthesised logic, you can have flops, latches and combinatorial logic. Flops and latches in particular are infered by the synthesis tool using templates. If you write a clocked function ...


1

EDIT: I tried to to ismulate this, but something is wrong in circuitlab simulator. You can controll a circuit similar to Marx generator. Where you have T_rise and T_fall, both exponential, but if input voltage is much hiher than needed peak, and R_rise is small enough you can get almost linear rise, perhaps adding an inductor can improve. ...


0

As your maximum voltage is 1v, and you can already generate fast square waves from your FPGA, consider this ... (if this isn't a solution, then in telling us why not, it may improve your ability to specify exactly what you want) Have a parallel RC to ground, with a time constant appropriate for your falling edge exponential decay. Switch a current into the ...


1

You have switched on your instantiation between reset and clock signals. Do not use signal connection by position, it is error prone and code is difficult to mantain. Use explicit port mapping like UUT: test port map( clk_i <= clk ...


1

Welcome to the world of Xilinx :) The problem is known, and I don't think they maintain this app very actively and if you search for the Answer Record mentioned in the error list, you will see that it requires some changes in the example code to make it compile with newer versions of ISE. You can find the solution to your problem at: Discussion about the ...


5

Here is a little overview on chip internal buses, which are suitable for FPGAs: Advanced Microcontroller Bus Architecture (AMBA) from ARM Ltd. Current version: 5 Specifications Further reading: Wikipedia Commonly known buses in that family: Adavance Peripherial Bus (APB) Advanced High-performance Bus Advanced Extensible Interface (AXI) Variants: ...


3

Most new IP uses the AXI bus, which is derived from the Advanced Microcontroller Bus Architecture introduced by ARM to support SoC designs. Newer FPGAs that include hard-core ARM processors pretty much use AXI exclusively.


3

Yes, there is the wishbone bus. Most modular IP cores you can find (e.g. on OpenCores) use it. Altera uses a variant, which is very close: the Avalon bus.


1

Normaly there are some spreadsheets supplied by your FPGA maker to estimate the power compsuption based on clock speed and resource usage. I never managed to get them to work thought :) i suggest you get your VHDL code synthetised , and then make it run in a dev board (same FPGA model & speedgrade), then measure the consumption of your "code". this ...


1

if it is a bug ,you will probably see it when analysing the frames in Chipscope .


3

I presume you are using the WebPack edition? In which case no, it is not supported. You need to use the ISE Design Suite version to support the Virtex 5 LX110. This requires you to purchase a software license.


1

A relatively simple C program to handle serial communication from a host to a microcontroller (originally Arduino) was published many years ago by TodBot The C source is on github I've used an older version. It has a few more options now, but is still short enough to be relatively understandable. It is written in C, so it should compile on most systems ...


1

The XAPP495 does not have any form of EDID handling. However, as you are using the Digilent Atlys board, and are having one HDMI input and one HDMI output, then as long as you use the correct HDMI ports, EDID handling becomes much simpler. Essentially you just need to pass the EDID signals from the output port (the one connected to your monitor) through to ...


1

Your circuit will work, but can be simplified. You don't need the schottky diode. When the IO is on, the max. current that could flow (assuming the driver RDSON is negligible) is (5V-VLED)/R1. If VLED is 3.2 V, and 100 ohm, this is 18 mA which is OK. Even if the '5 V' is within typical tolerances (say 5 %), you'll be OK. When the driver turns off, the ...


3

The voltage drop is easy to calculate for the resistor: U = R * I, and with a current of zero, the voltage drop is zero, too. In general, Ohm's Law cannot be applied this way to diodes, but for the special case of zero current, they behave the same: they do not drop any voltage. So when the output is off, the voltage at the I/O pin is 5 V. The datasheet ...


0

I also had some trouble with the Zynq SPI peripheral and as DoxyLover pointed out it has to do with the clock line being set to High-Z in Linux when data isn't being transferred. I solved this by bringing out the tristate pins for the clock line and manually feeding them into an IOBUF in my HDL, where instead of using the ZYNQ SPI tristate line I tied it low ...


2

The RTS (Ready to Send) or DTR (Data Terminal Ready) control signal is used by many microcontroller programming gadgets (Arduino et.al.) to reset the microcontroller in preparation for downloading the new code.


6

Quite a lot of RS232 is now transported over USB, and so is often not RS232 signal levels where it is used, but 5V or 3.3V. The signals from a USB-UART might be buried in a PCB. So it might not be as easy to see which signals are used as it was when looking at an RS232 cable. The move to USB, away from RS232, or a 'TTL' signal level of RS232, on the host PC ...


1

The only difference I'm aware of is that the latest xilinx parts have slightly higher maximum pin toggle rates (~1GHz vs 0.85GHz), I think that's it. FPGA's don't have analog IO, the VGA port is controlled by a set of simple DACs driven by digital data from the FPGA, but it won't do anything without being configured, an FPGA does absolutley nothing without ...


2

Honestly: it does not matter much. Both companies are about on par with features: lots of lookup tables, some dedicated blocks like multipliers or I/O), development environment (annoying) pricing (all the good features are available only for serious money) Deciding on a board without a very concrete project in mind is always difficult, so I'd pick a ...


1

You need to have different delays depending on whether the output is currently high or low. So rather than having 50000 cycles high and 50000 cycles low you have 10000 cycles high and 90000 cycles low. This will require a bit of conditional logic and likely also a larger counter. P.S. I think your current code actually has 50001 cycles high and 50001 ...


7

You can drive the clocks from the FPGA if you want to reduce part count. In general there are two downsides I can think of: Clock jitter - the I/O pins of the FPGA will add jitter to the clock - this is basically where the clock edges aren't at exactly the right place and as a result the frequency varies by a small amount cycle to cycle (the average ...


1

Yes, you can definitely do that. After all, the whole point of having a soft-core CPU is so that you can integrate it with custom logic. At its heart, the NIOS processor is just another HDL module. You can instantiate it within a top-level design just like any other module. However, I have found that the vendor tools (from both Altera and Xilinx) have ...


2

You can send a signal on to many many other destinations (the number of destinations is called the "fanout" of the signal). The more destinations it goes to, the longer your critical timing path potentially becomes though, so the fmax of your design may suffer. The tools will usually replicate the logic that drives those many nets if the timing becomes ...


1

The *.lpf file does indeed describe the pinout of the FPGA, however before explaining the lines, you should know that there is an easier way to assign them using the Lattice Diamond design software and there are some great tutorials out there showing how to do this, I've just found this one: https://youtu.be/SmdEP_ZsBgM He starts assigning pins at about ...


0

The second part of your question (2D array vs. RAM) really comes down to the resources available on your FPGA. Usually storing something as large as an image or frame of video in logic elements isn't recommended, the logic that is created during synthesis will be huge and your compiler will take an age to fit it in the FPGA if it fits at all. You should be ...


1

What you have to do is package sub modules as IP. Then you can use the IP as sub modules in a bigger design. The problem is that you can only package a whole block diagram. What you have to do is create a new block diagram, insert the blocks making a sub-module, package it as an IP and then add it to the main design. Repeat for all sub modules. Created IPs ...


1

See code below to combine 3 files together. --- top.vhd library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity top is port ( clock : in STD_LOGIC; clear : in STD_LOGIC; sel : in STD_LOGIC; y : out STD_LOGIC ); end top; architecture beh of top is signal freq1 : std_logic; ...


2

The majority of routing looks like MUX selections based on a fixed bitstream. Below is a fuse chart for a Manhattan-style FPGA that I made that was very similar to an older Xilinx 4000 series (Choices made because I have the graph router). The CLB contains 4-BLE blocks. The truth table from the LUT has 16-bit with inputs form the MUXes on the input lines ...


-1

There is actually some memory that controls the mux, in most FPGAs it's sram, some CLBs use eeprom and some low power CPLDs use flash, it's the memory that's being programmed when the chip is configured, it's not really user accessable as each manufacturer uses their own special way of structuring the configuration files but the configuration files program ...


3

Looking at a more detailed description of the slice (on page 204 of this UG) will provide us these details. As you can see, the select signal for the FiMUX comes from the BY input to the top half of the slice and the F5MUX is controlled by the BX input to the bottom half. These two inputs have additional functions and are described on page 207 of that same ...


0

Something important to remember is that sometimes FPGA development boards (buttons, LEDs, etc) are active-low. Meaning, the buttons are at '1' when they are unpressed, and '0' when they are pressed. The LEDs in this FPGA seem to be active-low as well (so they switch on when they are assigned '0'). This is my conclusion from looking at the schematic for this ...



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