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For synchronisation you need at least two flipflops between the pin and the logic that uses it. Those flipflops need to be very close together (in terms of the delay between the first Q output and the second D input). You also have to ensure that the second flipflop does not get replicated (which it might if it feeds various other logic) - if it does you ...


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So I think I found some answers to the problem and want to share them. I started to simulate the GTXE2_CHANNEL hardmacro. The simulation is behaving as "false" as the hardware. So I tried to simulate the MGT in Verilog and used an instance template from here: ...


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XST can automatically infer RAM blocks. Read Xilinx's "XST User Guide" ref. UG627 "Dual-Port RAM With Synchronous Read (Read Through)" architecture syn of rams_11 is type ram_type is array (63 downto 0) of std_logic_vector (15 downto 0); signal RAM : ram_type; signal read_a : std_logic_vector(5 downto 0); signal read_dpra : ...


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One thought - it sounds like the AXI bus may be waiting for the peripheral to respond (by acknowledging the write) and it isn't. This can be caused by a variety of things, but having the addresses wrong would be one to check. Can you add a Chipscope and see what bus transactions are taking place?


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It looks to me like you are not actively driving the SCL/SDA pins. They are probably configured as high-impedance by default in the bitstream and therefore simply show adjacent pin clock noise as others have suggested. It looks like the scope is showing 500mv per division so the magnitude of the noise seems large to me but that doesn't rule it out when in ...


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The default configuration is designed to be as passive as possible in order to make the device universally usable. For the Altera Cyclone series (which I have the most experience with) this means the I/O pins are weakly pulled up to VCCIO (to keep ICs with active-low chip enable lines off the bus), the CONF_DONE output is pulled low (you can connect this ...


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The answer (for the full version of Synplify at least) is to set the option for "Beta Features for VHDL" in the VHDL implementation options. Or via tcl with set_option -beta_vhfeatures 1. I've tested this with I-2014.03-SP1 on a very simple testcase consisting of a single line architecture asserting time equality. The assert triggers causing synthesis to ...


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you have not connected the body/bulk connection properly in your schematic. PMOS to VSS. But that circuit leaves the output node floating for the A=B=1 condition. Scan through the various solutions here, there is a robust TG version of XOR and XNOR, it uses 4 transistors though. If you look at all the possible states, you have 2 transistors each in 2 ...


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So, the unwanted signals are synchronised but not perfectly identical (although that could be the scope) and about 1Vpp. Crosstalk, perhaps? Is there another synchronised but digital signal on a nearby pin or trace? Do the unwanted signals disappear if you ground the pins rather than leaving them floating with pullups? If you don't include the I2C module ...


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Since this is your first FPGA project with this board, there are several things that could be going wrong. (I go through this kind of thing myself with every new development system) Maybe the board isn't powered -- the Amazon link doesn't say whether this board includes the required 5V DC power supply. If this is anything like the ones on ebay, the board ...


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The most straightforward thing to do (IMO) is to directly instantiate the device primitive in your VHDL. This way you are not relying on the tools to infer block RAM. In ISE, go to Edit -> Language Templates, and you will be able to bring up the template. (You will want to choose Spartan-3E, of course, although I think the primitive is the same in this ...


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I have seen at least two ways to use System Generator: Within Simulink, run all the way through synthesis and implementation and produce a .bit file Convert the System Generator design to the two VHDL files yourdesign.vhd and yourdesign_cw.vhd. Then run synthesis and implmentation in ISE or Vivado after importing the VHDL files into your project and tying ...


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I do not currently work with FPGAs, but I have been thinking about a very similar question. It is a bit beyond your budget, but Parallella offer several different boards with a Xilinx Zynq. T It runs Linux on its dual on-board ARM Cortex-A9's. I believe its FPGA development tools run on itself. That might be useful evidence for Linux-hosted tools. ...


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I think I'd have answered this interview question the same way you did. I believe the interviewer's requirement "to be done without a FIFO" was because a FIFO buffer is a valid, practical way to solve the problem of multiple clock domains -- but it can be done without the head/tail logic of a complete FIFO in many cases. And in the context of a job ...


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(Arguably this is not an answer, more a "confirmation of the question" using the full version of the tool). I'll delete it if people would rather... The reference manual for my version of Synplify Pro (I-2014.03-SP1) has this statement in it: The support of predefined physical time types includes the expanded range from –2147483647 to +2147483647 ...


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What we know - the data in and the data out are in serial form, the data is 8 bits and the clocks are asynchronous and different (unrelated) frequencies. Also we aren't allowed to use FIFO. I don't think synchronize is the correct terminology. Its more like a data buffering circuit, taking fast serial data in, storing it and clocking it out serially at a ...


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You don't need an arbitrary lane alignment barrel shifter in a TenG base-r MAC or PCS (TX or RX side). You can add two lane alignment positions in the TX PCS as an optimisation if want to use a running IPG that can add the next packet on a 4-lane boundary rather than 8-lanes, and you have a MAC that can emit with the half alignment. But that's only a layer ...


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What you are proposing to do, basically, is to take the FPGA 100 MHz clock, run it through a few flip-flops to reduce its frequency, and then output the reduced frequency. Your proposed output is not, in FPGA terms, a clock. It's just another registered output. So go ahead and run it out through a GPIO pin. You are, I think, confusing this with the need to ...


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The Spartan 6 family does not have dedicated clock outputs that connect directly to a clock network. For a slow clock, such as you are suggesting, that probably doesn't even matter, because jitter and rise/fall time differences for I/O pins are slower than the clock. For fast clocks, the recommendation I've found is to use an I/O pin in ODDR mode to make ...


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You can use any GPIO pin you want for output. It doesn't matter if it's balanced clock or arbitrary data. Also, output at units of MHz shouldn't give you any trouble. In sequential logic, there is a trend to use as little of clocks as possible. This is because clocks are very often the most important signals, as many others depend on them. I'll try to ...


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There are specific requirements for inputs that are clocks because of the way the clock is distributed throughout the FPGA fabric. However in your case, you are just outputting a divided clock on a GPIO pin so there are no specific requirements other than those that apply to the pin anyway - ie: it's an output with certain current limits etc. Here's a ...


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The fact that it takes one clock cycle means that it's done combinatorially, i.e. there are no memory blocks inside. The point is that in a digital system the clock is the time base, hence any time interval lasts an integer multiple of clock cycles. Since anything can't be instantaneous the smallest time interval is one clock cycle, so a purely combinational ...


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You are dealing with synchronous logic, which is FF -> logic cloud -> FF -> logic cloud ad nauseam. the relatching/catching of the new state and presentation for the next clock cycle is what is taking up the clock cycle. And the Muxing is likely to be done combinatorially.


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One case, that probably doesn't apply, is if you're using a standard older than VHDL-2002. Before than, buffer could not connect directly to out. So in a hierarchical design, the signal path would need to be declared as a buffer on all levels. Also, when adhering to these older standards, some tools have problems synthesizing buffers correctly. They may or ...


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The FPGA configuration itself is stored in SRAM (i.e. flip-flops). A newly started FPGA has an empty configuration where typically all pins are in a somewhat idle state (e.g. weak pull-up), and clocks are not forwarded inside the FPGA, so no activity takes place. From that state, either the FPGA boots actively by accessing an external device (usually, flash ...



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