New answers tagged

2

In general (99% of the time) you will need a clock signal for each register. But, verilog/VHDL you do not have to specify the exact register implementation. You just tell it, this is a bitnode which is either level triggered or rising edge controlled by some signals. For example if you are using a less common design style, like MS-CMOS, you may not need a ...


1

Assuming this is a Cortex-A9 Zynq 7000, you will find documentation on how to use interrupts with FreeRTOS on the following link: http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html - with worked examples in the official FreeRTOS download. Information on locating the example within the official FreeRTOS download can be found on the ...


1

C will be determined by the number and size of your logic gates (along with wire distance). For an entire processor this will be hard to calculate by hand. You would want to add up all of the node caps in the design. Software should be able to do this for you. With Altera software this is called PowerPlay As a simple example consider an inverter. ...


1

Since you are talking about a clocked signal assignment your code is inferring a D Flop register. From the diagram below, it should be clear that the current input (D) on any given clock will not be available for reading (Q) on the same clock edge.


0

You'd want some sort of byte-orientated fifo, preferably in a block RAM in the FPGA. Then only start the transfer to EMMC once the fifo is part-full. Even if I buffer a whole 512 bytes data array, I'll empty it faster than I fill it and it'll get slow again, eventually Then you have to design the system to tolerate this stall in a sensible way and not ...


0

I'm guessing that the author of http://www.louif.com/rbin/ ran the timing report with interconnect delays set to zero, which would mean the only delays taken into account were the combinatorial logic. A real-world implementation will have different delays due to place-and-route as other commenters have pointed out.


0

Looks like the code infers logic for fpga. Instead of initializing the register during declaration, you should use a reset signal. That models the hardware more accurately. In fpgas, the POR is implicit but you still should bring in external or internal reset into the logic. E.g. PLL locked output, etc. reg [15:0] counter; reg rst; always_ff @(posedge ...


0

The LRM is not very clear about initializers as a process. Since you could call a function in an initialization, that could be be considered a process. The purpose of the always_ff construct was strictly for design code not testbenches. Their purpose is to declare the intent of an always_* process up front in simulation so there are no surprises when you ...


1

There is no good reason why Altera FPGAs require an Altera configuration flash EPROM in master mode. Altera just enjoy the profits of their captive market. Xilinx were the same with their Spartan families until the Spartan 3 onwards, which can use cheap third-party flash EPROM for master configuration.


2

A LUT (Lookup Table) in modern FPGAs is nothing more than a RAM. The inputs are the address lines, and the output is the data output bus. There's really nothing more to it. FPGAs also tend to have more advanced logic modules (some vendors call them ALMs) which consist of one or more LUTs along with additional dedicated adders, high speed carry chains, and ...


4

In all likelihood, yes, the inout will be optimised away. In fact in almost all devices there are no internal tri-state buffers on routing, so inout ports usually get converted into a series of multiplexers. If you have an inout port always being driven inside a module, then the logic will simplify down. However, if you connect two inout ports together, ...


1

Further answer to point (1) beyond Tom Carpenter's answer: to run other devices, not necessarily interfacing with the FPGA digital I/O. I have worked with a custom-design expansion board for the 2x 40-pin GPIO connectors from Terasic products using Altera FPGAs where all of the digital signals were 3.3V, but some of the peripherals and other devices used +5V....


7

The FPGA doesn't use 5V, but some of the other parts on the board might. (The HD44780 LCD they're using often requires 5V on VCC, for instance.) Since it's there, they might as well provide it on the expansion connector in case you find it useful. Absolutely not. The clamp diodes are a last resort, and are only intended to protect the FPGA from brief ...


4

Level shifters. If you want to run a circuit at 5V, you can use the 5V line for power to your circuit. You then use the 3.3V and 5V to power level shifters to interface with the GPIO pins. If you want to run your circuit at 1.5V or 1.8V (for example high speed memories typically have those levels), you can simply use a regulator to get the power supply ...


0

Your logic analyzer plot does not have the necessary resolution. But the MISO and MOSI appear to be out of phase by half a cycle. There are normally 4 modes which SPI buses operate in. In one the data is expected to change on the falling edge and sampled on the rising edge of the clock. In another the opposite is true. If the master and slave were not ...


2

The difference between your acquisition speed and data speed is not enough. Increasing the speed of the FPGA or decreasing the speed of the SPI does fix the alignment problem. Your SPI clock and FPGA clock are not synchronized. This means your FPGA clock needs to run at minimum twice as fast as the SPI clock. However, since SPI is an external signal, it may ...


2

Unfortunately, you're walking in uncharted territory. Xilinx has provided very little documentation on the low-level structure of their FPGAs. That being said: the objects you're looking at are all different types of wires connecting elements in the FPGA. The names have to do with the length of the wires; for instance, OMUX is a very short wire, and HLONG ...


1

You need to feed tvalid through a chain of FFs that are clocked by the same clock that the multiplier uses. The number of FFs needs to match the number of pipeline registers inside the multiplier — probably 2, but verify this.


3

Explicit 'hands-on' control of the routing sounds like a good idea, but it isn't. Think back to the days when assembler programmers could squeeze a little bit more performance out of an algorithm by using manual assembly code instead of a compiler. There's only so much complexity you can think your way through. As the target becomes more complex, branch-...


1

Mostly all algorithms are heuristic and non-deterministic. You give a constraint into the problem solver, e.g. minimum frequency, and the tool will find a mapping, placement and routing for your problem. There are many many parameters which can be changed, so there is no easy algorithm to try all combinations / possibilities... Giving additional constraints ...


4

In addition to Tom's answer: BlockRAMs have one additional (mostly called parity) bit per byte giving you: 9(8+1), 18(16+2), 36(32+4), 72(64+8) bits. These bits can be used for simple parity algorithms to "secure" your data. Or you can implement ECC. You can also store meta information like Valid, StartOfFrame/EndOfFrame in these additional bits. ...


5

Correct, the remaining bits are unused. This is something you just have to accept in FPGAs, you are never going to use all of the resources. It's the price you pay for configurability. On the plus side, if at a later date you decide to add something like parity information or just make the data bus a little wider, you can do that essentially for free as ...


0

Is it necessary to reduce clk frequency for initialization? Yes. SD cards come up in open drain mode - you also need a pullup. This resistor limits the answer speed of the card until it switches into SPI mode fully.


0

I have finally solved the problem. By changing to Windows 7 and Qusrtus 13.1. Thanks Altera!!!


0

I assume you mean to ask if it's possible with a physical RAM, not a "virtual" RAM. In essence, many modern processor Memory Management Units (MMU) try to do this kind of lookahead, by prefetching the contents of the next few RAM locations during RAM bus cycles that would otherwise be idle. This strategy has been around for some time, and sounds simple, ...


0

I have the same issue though the host is ARM MPU. However, I believe CMD line should be pulled up by default, as my eMMC design guide states: "RCMD_PU:A 10K ohm pull-up resistor should be connected to the CMD signal to prevent bus floating."


1

CMD 1 is supposed to have the OCR Code with out the busy bit as the 32bit payload. You should be sending cmd <="01" & "000001" & x"80FF8080" & "0010110" & '1'; according to section A.6.1 for chips with capacity less than or equal to 2GB and cmd <="01" & "000001" & x"C0FF8080" & "1011111" & '1'; for chips greater ...



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