New answers tagged memory
If you store an image in an SRAM, generally you want to be able to split the address bus into an x and a y component. To do this, at least one of them must be a power of 2. For 320 x 240, you have to round 320 up to 512 to get a power of 2. 512 x 240 is 122880. If you shrink it down to 128x96, it's more efficient because 128 is already a power of 2 so ...
The minimum amount of RAM required to hold each row of an image will generally the number of pixels per row times the number of bits per pixel [most systems use the same number of bits for every pixel, though some historically have not]. In some cases, especially when this amount is close to being a multiple of some particular power of two, it may be ...
128*96 = 12288 pixels 160*120 = 19200 pixels thus there is no 1/10 relationship but 1.56..
Yes, your solutions for the homework are correct. Note that for the 4Mx32 you only use 8 bits per 32 bit word. If you want to use all bits you'd need a 32-to-8 multiplexer/demultiplexer. #2 and #3 of the lecture are a bit confusing. If the memory is word-addressable with 16-bit words, it's no longer a 4Mx8 memory but a 2Mx16 memory. To address 2M words you ...
Solutions to Homework: 2M x 32 = 21 x 220 x (25 / 23) = 21 x 220 x 22 = 223 Answer: 23 bits for byte-addressable 2M = 21 x 220 = 221 Answer: 21 bits for word-addressable
I agree with alex about framing. This can easily become complex, and then a solution may be the timing of the data sent. If you have a long pause between bursts you can use that to reset a RAM pointer. Use the FPGA's clock to downcount a register (width depends on clock speed and pause length). If the register reaches zero then reset the RAM pointer. Use a ...
The way I would do it is to implement something like a UART receiver section that can collect the serial data into an 8 bit register, and a small state machine that can take complete bytes and build the 16 bit words from them, and then store them into the RAM.
You'll need some higher level protocol for framing/packetization. Once you know which bytes need to go where, store them in registers as they come in. Once both the high and low bytes for each memory location are in registers, write them into the block RAM. Repeat for subsequent bytes.
Solutions: B = Capacity (C) / block size (b) B = 224 / 26 B = 218 blocks 224 = 24-bit address T = 24 - (8 + 6) = 24 - 14 = 10 bits B = 256 = 28 = 8 bits W = 64 = 26 = 6 bits 0x01BD36 = 0000000110 11110100 1101102 T = 00000001102 (10 bits) B = 111101002 (8 bits) W = 1101102 (6 bits) B = 111101002 = 244 Therefore, 0x01BD36 maps to cache block 244.
For X addresses, where 2^N+1 < X < 2^N, N address lines are not sufficient, N+1 is sufficient (but leaves some address space unused). Hence you have no other option than to use (at least) N+1 address lines.
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