New answers tagged memory
1
FRAM/MRAM/nvSRAM are NV memories that offer good speed (serial or parallel interface) and offer high endurance and long retention times. I would classify these in one bucket.
EEPROM/flash are in a different bucket. EEPROM are byte-writeable, higher endurance, slightly faster than flash equivalents. Both are floating gate technologies. But flash implements ...
6
Yes, you understand the definition of volatile and non-volatile memory. From that alone you'd think non-volatile is always better. However, in the real world that is not true since the different technologies for making these memories cause other attributes to appear beyond volatileness.
Tradeoffs that various different memory technologies force on us ...
1
"The watchdog is disabled while we are in this loop." - So you provided code that disables the watchdog? Note that it will not be disabled automatically by a normal reset.
The ATmega1284P datasheet quotes for example:
Note: If the Watchdog is accidentally enabled, for example by a
runaway pointer or brown-out condition, the device will be reset and
...
1
The speed of your communication depends on many different items such as:
The speed of your SRAM module
The type of interface you are using
The routing of the board
For the first one, you can get the info from the datasheet of your IC, many SRAMs have acess between 8ns to 120ns, so find that information and if the device is not very fast, then you can ...
0
If I were approaching a big project in this direction, I would consider PXI, http://en.wikipedia.org/wiki/PCI_eXtensions_for_Instrumentation
Essentially, this is a shared PCI bus with some extensions, and the bus is accessible by every device you plug into it. http://www.stmopen.net/intellective-pxi-bus-extended-card-design-based-on-arm-microcontroller/ ...
1
I think your understanding of what the cost of I/O is might be misguided. I'd put the MCU on the USB bus, and use a USB bus packet to send the updated data to the microcontroller. You can buy a USB bus microcontroller board all ready-made for < $15. The overhead of the USB bus transfer is unlikely to ever show up on a profile of the system performance.
0
memory can be bypassed at the memory controller.
Technically another memory controler may be substituted, but its substitution would be detectable. Most likely the bus would be off for a period of time while the substitution took place. The inability to communicate with RAM would be detected by the processor and result in OS failure.
Can linux (be ...
1
That patent doesn't do what he thinks it does. The patent is a method for changing the components of a memory controller during design so that you can support a collaborative bypass of the controller within the various components or stages of the memory controller itself. No where do they describe sitting on the external memory bus (to DRAM) and snooping ...
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