New answers tagged schematics
You cannot delete IO from a block, but ignore them. Some warnings may appear, but sometimes they are not important (always check!). The best solution is to program your own block and select the signals you want to use. The error with my clock was, that I did not placed it in the main schematic. So everything was fine until I tried to download it to my ...
The LM324 has an input common mode range of the negative rail up to two volts below the positive rail. So with a five volt supply, you need to make sure your signals are in the 0-3 volt range for proper operation. In no case should you apply a signal beyond the supply rails to the opamp's input, like 6.1 volts into a 5 volt-powered opamp.
A Form A relay contact is Normally Open, so since the data sheet says to delete terminals 1 and 3 for a Form A relay, those must be the Normally Closed contacts, and 4 and 6 are then the Normally Open contacts.
Zoom in to the image in the datasheet. You'll see that 7 is connected to 2 on the left image, and 7 to 1 / 9 to 3 on the right image. Those are the positions when the relay is unpowered.
I added the same object in eagle now too and it works fine here. Maybe the 'random' pins are also connected ground for example. If the shift register is closer to a component that is also connected to ground you will see a yellow line (from the unrouted layer) to that component. To check if this is the case you can use the show function on the board ...
You can use as a reference, any regulation or recommendation, such as ANSI / IEEE Std 91-1984, but more important is to maintain consistency across all documents. Use a standard, has the advantage that when you refer to it in your documents, there is no possibility of ambiguity. You can also write an internal document to your organization (such as a long ...
The ultimate answer here is "Do whatever your coworkers do". They're the ones who will need to understand it after all. That being said, 3 is the clearest and most difficult to misunderstand, and probably the best general practice for that reason when you don't have a coworker to ask.
It sounds like you have no connectivity between your VHDL design and your manually created sheet symbol. The issue here sounds like that VHDL doesn't have 'signal harness' 'pins' (ports). While you can have a port that's a composite (record) type, all it's elements are required to have the same mode (in, out, inout). Array type have the same name and ...
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