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1

As was mentioned in the comments, what you stated is actually opposite of what the outcome actually is. When you have an input of 5V, the LED is off, which means no photons to turn on the phototransistor, so the transistor is off. If the transistor is off, then your your output is 3.3V When you apply 0V to your input, you have current flow through the LED, ...


2

It's the EAGLE part designator for a single pin through hole header.


1

You can do it, it's not going to be pretty though. There's an import option called import artwork. After that you can make changes, but it's not going to take you back to the original database. So it's not like you can import gerbers and then have the same experience of rats nests, nets, drc and the nice things you would have if you had the native allegro ...


4

OK, I found an Eagle schematic file of this, and I checked the properties, like jwsc suggested. They seem to represent fiducials. Comment: fiducials don't belong on a schematic, they're purely PCB-related. You don't place mounting holes on a schematic either. When they appear on a schematic they will most likely show up in the BOM as well.


0

"What, if anything, am I missing?" The main thing would be that you are using non-isolated boost regulators. With a non-isolated boost, the minimum output voltage will be Vin-Vd or in this case ~11.6V, since Vin is 12V and D1 and D2 are Schottky diodes. A transformer coupled Flyback or Sepic would be needed to have standby output voltages less than Vin. ...


0

No, your feedback will not work. Your schematics has N-channel mosfets. They require gate to be more positive than source. In your design, when the system is on, you will have +24/+30v on source, and only 0/+12V on gate. Even if you change mosfets to P-channels, you will still have at least 12v across gate-source when system is on is open. You would not ...


2

There isn't any. If you are just viewing a file, you could install Altium Design Viewer.


0

Could you please explain what parts I've misunderstood and give me any ideas to solve it. The parallel impedance of (L+R) and (C+R) load cannot be simply expressed as: - \$\dfrac{Z_1 Z_2}{Z_1+Z_2}\$ This is because the phase angles of the currents in each limb are different and without using complex analysis you will be wasting your time. Imagine ...


0

I haven't tried it using your example, but I believe $$ Z = {\frac{\sqrt{X_{L}² + R_{L}²}*\sqrt{X_{C}² + R_{C}²}}{\sqrt{(X_{L}+X_{C})²+(R_{L}+R_{C})²}}} $$ should be: $$ Z = {\frac{\sqrt{X_{L}² + R_{L}²}*\sqrt{X_{C}² + R_{C}²}}{\sqrt{X_{L}² + R_{L}²}+\sqrt{X_{C}² + R_{C}²}}} $$


0

I think I figured it out. Sorry for the poor formatting, but I'm stuck on mobile right now. Here's the schematic:



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