New answers tagged

1

To confirm Mario's answer, I get gain: \$G = +\frac{I_{C1}I_{C2}R_{C2}}{V_T^2(\frac{1}{R_{C1}}+\frac{I_{C2}}{\beta V_T})}= +1766\$ where \$V_T = kT/q = 25.26\text mV\$


2

The gain A of a single transistor amplifier stage is given by $$ A = -g_m r_{out} $$ For two stages in cascade it's the product of the gains. The gm can be found using \$gm = I_C/V_T\$. The output resistance is \$R_C\$ in parallel to everything else that loads the output node. OK, here my calculation: gm1 = 100e-6 * q/(k*T) gm2 = 1e-3 * q/(k*T) rpi2 = ...


1

I believe that you misunderstand the circuit. If you set the components to the values implied by the equation, the load current will be limited to the value indicated. As long as the load resistance is low enough, and the input voltage high enough, to draw the current you'll be fine. Ignore the data interface unless you want to use the 9611 to produce a ...


2

Your equation for current limit is incorrect. According the Maxim datasheet, the expression in the brackets is (R4+R3), not (R2+R3). That may or may not have been confusing you, as R2 is closely associated with the PFET. With the correct expression, we can see that the circuit is servoing the drop across Rsense to be proportional (equal to 0.4x) to a ...


2

It is AP11SL60H, from APEC. http://www.alldatasheet.com/ may help you in similar situations.


0

The problem with the term saturation is that it means different things for bipolar and MOS transistors. For a MOS diffpair the transistors should work in saturation because then they act like voltage controlled current sources. The drain-source voltage has to be higher than the saturation voltage. For a bipolar diffpair the transistor should operate in ...


2

Most technologies are limited to VGS < 10 V, or 5 V in more modern ones, and need circuits like this. High voltage level shifters are needed in high voltage DC/DC converters and similar circuits. The general approach is to create a rail that is ~ 5 V below the HV supply and use this to limit the VGS of the high side FETs. You also don't drive the 10 pF ...


1

The usual technique is to use a cross-coupled level shifter. If you use "your favourite search engine" you gets scads of images. This one is grabbed from Freescale Although you will notice that the PMOS here has gates that are subjected to the full voltage swing. Having done this before I am wondering if your statement about Vgs is true. This might be ...


2

Maybe 'saturation' is not the proper description of what happens. By increasing the values of Rc eventually you will starve the transistors of any useful current, such that Vo1 and Vo2 can no longer rise above -Vee volts (or not by any useful amount). In fact they would approach -Vee the closer to 'saturation' they get. Lowering Vcc simply compounds the ...


7

The "4 pin transistor" is an integrated circuit such as the QX5251, which combines battery charging, light sensing, and voltage boost circuitry in a single package.


4

You are seeing exactly the behaviour I would expect. When turned on, Silicon BJT transistors need a \$V_{be}\$ (that's the voltage of the base relative to the emitter) of around \$\approx0.7\mathrm{V}\$. That means that if your Arduino output is at \$5\mathrm{V}\$, then if the emitter is higher than \$5-0.7=4.3\mathrm{V}\$, the transistor will be turned ...


0

1) The transconductance gm is the slope of the function Ic=f(Vbe). Because this function has an exponential shape the slope (differential quotient) can easily be derived. And the result is gm=Ic/VT (Ic is the collector DC current). 2) Because the input resistance rπ is the inverse slope of the exponential curve Ib=f(Vbe) and because of Ic=beta*Ib we easily ...


0

\$V_T\$ is the thermal voltage, and is given by the formula: $$V_T = \frac {kT} q$$ where \$k\$ is the Boltzmann constant (1.38e-23 J/K), \$T\$ is the temperature in Kelvin, and \$q\$ is the charge of an electron (1.6e-19 C). At room temperature, \$V_T\$ is about 25.9 mV


2

While it's a little bit tricky to compare the specs of an LDR to those of another light-sensing device, such as a photodiode, phototransistor, or solar cell (because they are very different devices), I'll try and summarize the main differences here: Response time: from the LDR datasheet, it has response times in the 10's of ms (20-40ms). Photodiodes and ...


2

Good bits. Their resistance varies over a wide range, many decades, from light to dark. Their resistance is in a 'nice' range for detecting with meters, and the analogue inputs of Arduinos and PICs, so are very easy for a noob to use. They are good linear resistors, so are useful in audio volume controls and for controlling the frequency of RC filters, ...


0

You find this by first determining the collector current requirements of the transistor, then working backwards to find the base current, then the resistor to support the base current. To find what current the transistor needs to switch, remove the transistor and close the switch with a ammeter instead. That will tell you how much current the string of R2 ...


4

As Andy pointed out, you are already abusing the transistor just when it's sitting there trying to be off. However, there are other issues. If the collector is connected to a load with inductive component, then the collector voltage can go considerably below ground when the transistor is switched off. You should put a Schottky diode from ground to the ...


4

The maximum collector emitter voltage for Q1 is 40V - read the data sheet - you are applying 42 volts.


1

From datasheet, TIP120 absolute max current is 5A. 11.1V / 0.319 ohms is 35A. Your intuition is correct.


1

A mosfet conducts equally well in both directions so when a mosfet is activated it will have similar on-resistances in both directions. Typically, the solid state relay: - When activated there is a reverse connected and a conventionally connected mosfet in series with the AC load. It's not the case that the parasitic diode inside the reverse connected ...


2

The Power mosfet can block the voltage only in one direction. In the other direction, Source to Drain, it is a diode (as the center portion of the simbol suggests) if the gate is OFF. If the Gate is ON it conduces with the same resistance then the Drain to Source case. Considering this case Erickson's ideal representation is correct.


8

From the notes underneath that part of the datasheet: Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). Fig. 11: From this, you can see that for 80% duty cycle (Duty factor, D = 0.8) we are beyond the scope of the graph (it only covers D <= 0.5). For that reason, you will need to work within the ...


5

You're over-saturating the transistor. In this context, saturation means \$V_{BE}>V_{CE} \$. If you imagine your NPN transistor as two diodes back-to-back as the image below shows, you can see that if you drive your base hard enough, \$V_{CE}\$ will drop to a very low voltage (e.g. 0.1 V). Since we are driving our base very hard, \$V_{BE}\$ might be about ...


0

Opto isolators are one way to accomplish a work-around for level shifting from your 3.3 volts to the necessary control voltage for the upper transistors of the H-bridge. However if you go to IGBT's rather than junction transistors you can radically improve the efficiency and get higher operating voltages. For stepper pulse rates both opto-isolators and IGBT ...


-2

Your R2 selection are not optimal, typically I would use a 1k to 4.7k resistor. The capacitance in the transistor is probably accounts for the delay using the 10k resistor. I assumed he was looking for some other value between 6 ohm and 10k. If you read the second part of the question he was using a 10k ohm collector resistor which was way too high."http" ...


1

The problem with the reset circuit is that you have the reset hard tied to the 9V supply. The Transistor, when it turns in tries to short the 9V to GND. Remove this connection and place a resistor from 9V to the RESET input. Something like 4.7K to 10K would be appropriate. Now the NPN transistor will be able to operate the reset input. To make this a ...


1

When you cascade the amplifiers, the net input impedance will the input impedance of the first stage and the net output impedance will be simply equal to the output impedance of the last stage. What needs to be taken care of are the central impedance or the impedance between any two stages. You need to make sure that the output impedance of one stage should ...


0

A transistor is a current controlled device. This means that you have the freedom to alter the current in any transistor circuit. I assume that you already know that the transistor can be configured into three different modes namely the common emitter, common collector and common base. For my explanation, I am going to consider the common emitter ...


3

Because current flows into the base of the transistor, causing the voltage divider to "droop". Basically, a voltage divider only behaves as you expect when no current is drawn or sourced from the middle node. As more current is drawn, the voltage at the middle of the voltage divider drifts further away from "what you expect". Your base current Ib has to ...


1

Electronic peek-a-boo! simulate this circuit – Schematic created using CircuitLab Figure 1. Open circuit switch loaded by voltmeter impedance. I think you are expecting about 1.5 V across TA and TB. If you redraw your circuit as open switches (transistor bases pulled to ground) it should become more obvious what's happening. The internal ...


2

Here is the NOR that is probably being referred to: In the state where both C&D signals are high both of the lower NMOS transistors are on and thus discharge the "Out" node faster than a single NMOS could (in the case of when only one of C or D is high). Basically you don't worry about it, because there are other more dominant effects. And to fully ...


1

In such a case you have to consider the worst case, i.e. only one transistor active in the pull down network and of course you have to account for the series connection of two PMOS transistors in the pull up network. The design should use the inverter as reference for the worst case, so that you have equal delays. Of course for some transitions the gate ...


2

The problem is probably because the battery voltage collapses when the motor is loaded. That runs the IR receiver out of spec, and it pulls its output low regardless of what it is receiving. That keeps the fan on, which keeps the power voltage low, etc. This is just a guess on my part from looking at the schmatic and the symptoms, but it seems quite ...


1

I think this circuit needs a pull-up resistor of about 2.2k 1/4 watt from the base to the emitter of Q1. This is from the spec sheet for this part:Voh = Vcc-0.5 Volts.Vol = 0.2 to 0.4 volts maxEven though the output is not OC type, the LFN out rail is low enough to induce a trickle current in Q1, so it may NOT shut off even if LFN out = high. A pull-up ...


1

simulate this circuit – Schematic created using CircuitLab Figure 1. Your circuit. A search for LFN shows up the PIC-1018SCL via this site. It's an infra-red receiver with built-in logic to pull its output low when IR is received. In normal operation it will draw current from the base of Q1 via R1 when an IR signal is received. This will pass ...


0

Output impedance depends on if the gain is for extra current, or for extra voltage or voltage swing. Current gain is normally taken off the emitter (of a transistor )and implies there is no voltage gain, but the drive impedance is lowered, possibly a great deal. This is sometimes called a 'Buffer', because it isolated the previous stage from the next stage, ...


0

Voltage gain can be increased (for BJT) by increasing the collector current. as gm = Ic/Vt. For a MOSFET gm increases with the square root of the drain current. Of course that has the effect of increasing the power dissipation and in the case of the BJT it lowers the input impedance so that current gain stays the same.


2

In a single amplifier stage you can't have low output impedance and high gain at the same time. The active device (bipolar or MOSFET) is voltage controlled and generates a current. In order to get a voltage again you need a resistor. Therefore you have to make a tradeoff between gain and low output resistance. The output resistance is only of concern when ...


2

If the diode and transistor are perfectly matched, then the thing you can say about them is that the diode current and the emitter current will be the same in this circuit. But it is necessary to also account for the transistor's base current IB: simulate this circuit – Schematic created using CircuitLab Start iwth IB. The collector current is ...


0

In the dynamic case: you are charging a capacitor, and then draining voltage off of it based on the pull down network. \$\Phi\$ exists to set the initial condition on the node. What is not drawn is that you need a large enough capacitance to store charge on, so the inverter gate is larger than minimum. The drawback of this is that is all very timing ...


0

connect two LDR in parallel it will increase the sensitivity and it will operate in dim light sources. you can also eliminate the 1.2K base resistance.


2

The key to the effect can be found in the photographed text: If the compensating diode and the emitter diode have identical current/voltage curves From the schematic, the voltage across the diode and the voltage across the base-emitter junction have identical voltages (they are, after all, shorted together at base and ground). This means that each ...


3

What is wrong with this circuit? Typically a circuit like this has a gain that is roughly numerically the collector impedance divided by emitter impedance. So if you had 2k2 in the collector and 220 ohms in the emitter you'd get a voltage gain of ten. This type of circuit is usually pushed to have much higher gains by bypassing the emitter resistor ...


1

In your circuit you have posted, remove R7, replace it with a 680uF capacitor. And then, connect the base of that transistor to the ground/emitter using a 1Megaohm resistor. This way transistor will get the base drive through the cap for about 10 minutes until it is fully charged by the 1 megaohm resistor. This mod is the easiest one to accomplish your ...


0

We must assume that by "sleep functionality" you mean that the LEDs will turn off after some time period after being powered? The simplest way to do this would be to use a resistor/capacitor time-constant to remove the base drive current to the transistor after the desired time period.


2

Back many, many years ago I made a simple inverter using a center-tapped 'filament' (yeah, that's what they were called) transformer and two 2N3055s and a couple base resistors. Something like this: simulate this circuit – Schematic created using CircuitLab The frequency depends on the magnetic saturation of the transformer so it will tend to ...


4

A 2N3055 is a large NPN power transistor. Instead of having it be part of the oscillator, consider making a separate oscillator that is then used to drive the 2N3055. That way you separate the power handling from the oscillating parts.


0

Output of BJT can be voltage as well as current That is not correct, a BJT is basically a current amplifying device. If a voltage comes out of a BJT based amplifier that voltage is either the BJT's collector current which is turned into a voltage by a resistor connected to the BJT's collector or the BJT is used as a voltage buffer (common collector or ...


-1

The max collector current from a transistor is determined by the current going from the base to the emitter. While for a FET the on-resistance Rds (Resistance drain source) is determined with the Gate to Source voltage:


0

Because BJT collector current \$I_C\$ is controlled by base current \$I_B\$, while FET Drain \$I_D\$current is controlled by \$V_{gs}\$. UPDATE: I'll explain with the basic relactions between currents and voltages; The basic equation fro the BJT is: \$I_C=h_{FE} I_B\$ For the FET, in the saturation region, \$I_D \propto V_{gs}^2\$. N.B. the voltage is NOT ...



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