Hot answers tagged vhdl
18
I use ONLY VHDL. It is far from dead. A couple of years ago it seemed like a 50/50 split between people using VHDL or Verilog (anecdotal evidence at best), but I doubt that it has changed much since then.
The most recent version of VHDL is "VHDL-2008", which in language standard terms was just yesterday.
14
Typically ASIC design is a team endeavor due to the complexity and quantity of work. I'll give a rough order of steps, though some steps can be completed in parallel or out of order. I will list tools that I have used for each task, but it will not be encyclopedic.
Build a cell library. (Alternatively, most processes have gate libraries that are ...
13
In VHDL, a for loop executes in zero time. This means that instead of waiting a clock cycle between each iteration, the entire loop is run within one clock cycle, with only the final result of the loop being shown at the end. This is what's happening in your code. The entire loop is executing in a single clock cycle, and the value of s_out is only going to ...
10
Short answer: yes.
There are a few simulators: GHDL is an open source simulator. Not as good as the mainstream simulators, but it will get you started.
There is Sigasi, a VHDL design entry and code comprehension tool, which works on Mac. This will help you write your code before you send it to the simulator.
As for synthesis tools, you should take a look ...
9
I'm almost in the same situation as you.
What I'm doing:
I'd took a free very basic course of VHDL in the college that I'd studied. I'd played with Spartan 3E board.
So, I bought the board and I will start to play.
A friends of mine have suggested these books:
Rapid Prototyping of Digital Systems , James O. Hamblen, Michael D. Furman
Doone ...
9
Hmmm, this all depends on what exactly you are trying to learn. A counter or adder in VHDL is super easy:
signal count :std_logic_vector (7 downto 0) := (others=>'0');
. . .
process (clk)
begin
if rising_edge(clk) then
if count_enable='1' then
count <= count + 1; -- could be +2 also
end if;
end if;
end ...
9
If you plan on working with programmable logic (e.g. FPGAs, not MCUs), VHDL and Verilog are the two languages you'll have to know. As a student, you'll probably have to learn both, use both and be examined in both. That was certainly the case for me (and I only took a few courses in ASIC design), though it was a long time ago.
Chances are either VHDL or ...
9
The whole issue of CPU verification is super large and difficult. There are people who make a career out of just this. I'll just give you the overview...
Write an assembly language program that tests every instruction and every tiny detail of every instruction. For example, when testing the ADD instruction you might test it with numbers that are both ...
8
To me, the job titles are very similar, but not exactly the same. "Logic design," in my opinion, implies writing VHDL or Verilog to design digital logic to go onto FPGAs, CPLDs, or maybe even ASICs.
"Digital Circuit Design," on the other hand, means to me that in addition to (potentially working on) the HDL stuff, you are also designing the entire digital ...
8
Short Answer Nope!
I have investigated this in the past, and sure you can use a text editor to write the code, but none of the major (xilinx and altera) have any design flows for the mac os x platform, so synthesizing and place and route are out.
On the simulation front, I did find a program that claims to perform simulation for the mac platform, but I ...
8
Integers are fine in synthesis, I use them all the time.
I use std_logic at top level ports, but internally I was using ranged integers all over the place
That's fine!
Be aware:
You are simulating first aren't you :) - Integer types don't automatically "roll-over" in simulation - it's an error to go out of the range you've specified for them. If ...
8
There are so many things in this question that it is difficult to know where to start.
I am assuming that your FPGA logic is a SPI slave, not a master. If it is a master then you have a whole different set of issues which I'm going to avoid going into right now.
The simple direct answer to your question is that you need to sample an async signal at least ...
8
Please, please, please don't take what I'm about to say personally. I think your question is one that a lot of people have probably wondered about at one point or another. I even up-voted the question. Unfortunately, the answer is "it doesn't work that way". And there is no good way to answer your question without possibly making you feel bad for asking ...
7
This file is commonly called a "bitstream". Xilinx devices' bitstreams have the extension '.bit' and are generated by a program called 'bitgen'. '.bit' files are binaries and those are generated by default; if you want the ASCII representation of the bitstream, run
bitgen -b <your design>.ncd
and then a '.rbt' file will be generated in addition to ...
7
I think you're confused about the nature of VHDL. There isn't a 1-1 mapping between VHDL keywords and gates, rather, most of the keywords you listed are composed of many gates.
The standard logic gates are:
NOT
AND
OR
XOR
NAND
NOR
XNOR
There are a few additional structures, such as flip-flops, but the number of basic representations is small. ...
7
That board is a CPLD board, similar but you state an FPGA board in the question. Programming will be by JTAG, and various vendors do things differently so there is no (satisfactory) "one programmer for all vendors" solution (let me know if you find one :-) ) There are things like OpenOCD and OpenJTAG and Presto, Wiggler, etc.
You would need the Xilinx JTAG ...
7
The worst case scenario for a Ripple-Carry Adder (RCA) is when the LSB generates a carry out, and the carry ripples through the entire adder from bit 0 to bit (N - 1). An example pattern would be 00000001 + 11111111. In adder terminology, bits 7-1 are "Propagators", and bit 0 is a "Generator". The critical path is from the carry-out of the LSB to the ...
7
Both Xilinx ISE and Altera Quartus II IDEs run under Linux. Free downloads are available:
http://www.xilinx.com/products/design-tools/ise-design-suite/ise-webpack.htm
https://www.altera.com/download/software/quartus-ii-we
There is also Symphony EDA:
http://www.symphonyeda.com/
which might be better if you don't need synthesis. It's a nice piece of ...
7
1st of all: welcome to the world of logic design.
2nd you need to understand the "designflow" (important buzzword!) designflow in VHDL/Verilog is :
think about a design you want to implement, e.g. an adder
implement the design in VHDL/Verilog
implement a testbench in VHDL/Verilog
use the testbench for simulating your design (from step 2)
if this works and ...
7
If you multiply 2 5-bit numbers (A and B are both std_logic_vector(4 downto 0)) don't you need 10 bits (not 9) to store it in (so P should be std_logic_vector(9 downto 0)? (31*31 = 961: needs 10 bits)
But also - don't use std_logic_arith/_unsigned. Use ieee.numeric_std and then use the unsigned data type.
7
Assuming you need a read cycle on each port on each clock cycle, each BRAM will give you two read ports. Beyond that, you have to replicate the contents of the memory.
Is the bandwidth required at each port less than the raw bandwidth of the BRAM? In that case, you might consider multiplexing the ports. Use a counter that runs at the full speed of the BRAM ...
7
It has to do with what can be easily evaluated at elaboration time, formally, what is called a "locally static expression". This is an obscure looking rule, but it deserves some thought - eventually it does make some sense, and your simulator is quite correct in alerting you by generating non-obvious results.
Now, temp(1) can be evaluated at compile time ...
7
With HDL languages, you have to understand you are describing hardware, not software. I think this is fundamental to "getting the hang of it". The order of the code in your module doesn't matter, it all happens at once.
It's not so bad once you get going - after you have designed a few simple modules (e.g. counter, adder, mux, etc) your mind should adapt ...
6
As LoneTech says, use ieee.numeric_std is your friend. You can convert a std_logic_vector to an integer, but you'll have to cast it as signed or unsigned first (as the compiler has no idea which you mean). VHDL is a strongly typed language. I've written more on this subject on my blog
Fundamentally, I'd change your 7seg converter to take in an integer ...
6
Can you clarify what HDL you want to use? The choices are basically Verilog or VHDL, [EDIT], and their relatives, Verilog-ASM and VHDL-ASM (Analog mixed-signal). [/EDIT]Verilog has some C-like syntax, which makes it easier to pick up if you've worked with C before, but this also makes it easy to develop bad habits - You can't program hardware in C, because ...
6
The first problem is that he code, even when formatted so you can read it, is not very good. You'd be lucky if it synthesizes at all, and if it does then it won't work very well. The main problem is that there are multiple clocked and not-clocked chunks of logic inside the process. If it did synthesize then there are still D-Flip-Flops that have nasty ...
6
You must use some signals, you can't map straight from one pin to another (I'm also using direct instantiation to avoid creating component declarations - see also my answer here):
signal aout : std_logic_vector(5 downto 0);
A: entity work.componentA port map(
output_pin => aout
);
B: entity work.componentB port map(
input_pin => aout(5 ...
6
Here's an analogy which helps some people (esp. from a physical hardware background):
A component tells the compiler "there's going to be something with these sorts of pins on it called this at some point, but don't worry for now". It sort of defines a "socket". You can go on to describe what "wires up" to that "socket" etc.
An entity is something ...
6
To avoid latches, you need to make sure all of your outputs are assigned at all possible branches of the code.
for example,
if a = '1' then
b(0) <= '1';
else
b(1 downto 0) <= "00";
end if;
would generate a latch, because in the first condition, the value of b(1) is not specified, so the compiler decided you wanted to keep the previous value ...
6
This is where you can tell that VHDL was invented by a government committee. If VHDL was designed to be consistent then what you're referring to as "to" would be called "upto"-- as in the opposite of "downto". In this answer I will refer to "upto". Just understand that I'm using this term for clarity-- it still isn't an official VHDL keyword.
Vectors, or ...
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