Tim

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714 reputation
111
bio website stackoverflow.com/users/…
location San Jose, CA
age 27
visits member for 10 months
seen yesterday
stats profile views 34

Professional ASIC engineer with experience in RTL design, Verilog, synthesis, power, and timing issues on billion+ gate ICs.

Other hobbies include:

  • Computer Graphics
  • Android Programming
  • C++ Programming

Personal released projects:

Portfolio Map-----------Electron Flux


41 Tags

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system-verilog
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asic × 2
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vhdl
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