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Greg

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Sr. Verification Engineer for imbedded solid state memory controllers.


181 reputation
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9 Answers

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3
 Detecting 1'bx and 1'bz bits in a Verilog variable
1
 Most efficient way to select between 10 large buses?
1
 Code Error 9 In Modelsim
0
 Data transfer from Latch to PIPO
0
 concatenate inputs in verilog
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181 Reputation

+45 Detecting 1'bx and 1'bz bits in a Verilog variable
+10 Most efficient way to select between 10 large buses?
+15 2d arrays specification in verilog
+10 Code Error 9 In Modelsim
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digital-logic × 2
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