fatai

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242 reputation

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visits	member for	2 years, 2 months
	seen	Jan 18 '12 at 7:56
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please delete me

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11 Questions

votes activity newest

5	How to avoid latches during synthesis
5	In VHDL, what is the difference between “downto” and “to”?
3	how to write output of the monitor to a file
2	purpose of driver
2	process and signal assignment

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242 Reputation

+25	In VHDL, what is the difference between “downto” and “to”?
+10	purpose of driver
+5	generic and generic map \| total time delay for each files
+5	How to avoid latches during synthesis

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2 Answers

votes activity newest

2	how to write output of the monitor to a file
0	recommandation webpage/book to learn asmd chart over using verilog

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2 verilog × 5	0 tutorial
2 hdl × 4	0 books
0 vhdl × 6	0 design
0 digital-logic × 5

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